CN106449414A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN106449414A CN106449414A CN201610984921.5A CN201610984921A CN106449414A CN 106449414 A CN106449414 A CN 106449414A CN 201610984921 A CN201610984921 A CN 201610984921A CN 106449414 A CN106449414 A CN 106449414A
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000002360 preparation method Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 13
- 230000012010 growth Effects 0.000 claims description 20
- 239000013078 crystal Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 229910021332 silicide Inorganic materials 0.000 abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 229910005883 NiSi Inorganic materials 0.000 description 6
- 230000008859 change Effects 0.000 description 3
- 230000009647 facial growth Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a PMOS (P-channel Metal Oxide Semiconductor) device and a preparation method thereof. The preparation method of the semiconductor device comprises the following steps: 1, providing a semiconductor substrate, and performing patterned etching on the semiconductor substrate to form a pit; 2, epitaxially growing an SiGe material in the semiconductor substrate pit; 3, epitaxially growing a first cap layer on the SiGe material; and 4, epitaxially growing a second cap layer on the first cap layer. After the dual-cap process of the preparation method of the semiconductor device is adopted, the shapes of the cap layers can be remarkably improved, and formation of subsequent metal silicide can be benefited.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of semiconductor device and its preparation
Method, especially PMOS semiconductor device and preparation method thereof.
Background technology
With the development of integrated circuit, field effect size is less and less, introduces stress technique in semiconductor manufacturing to change
Become the lattice structure in raceway groove, so as to improve the mobility of the carrier in raceway groove；Apply on raceway groove from from the point of view of existing research
Plus tension can improve the mobility of electronics, and apply the mobility that compressive stress can then improve hole.Embedded SiGe technology quilt
Extensively application is to improve the performance of PMOS, and embedded SiGe technology passes through to be embedded in sige material in PMOS in source region and drain region,
Compressive stress can be applied to channel region so that the performance of PMOS is obviously improved.
In embedded germanium silicon technology, by improving the content of Ge in SiGe layer improving stress of the SiGe to raceway groove, from
And reach the lifting of device performance.Yet with epitaxial growth have crystal orientation selectivity (<100>Epitaxial growth is most fast,<110>
Secondly,<111>Extremely difficult growth), easily formed in the both sides of epitaxial layer when SRAM region SiGe epitaxial layer is higher than base plane<
111>Crystal face.And<111>Crystal face is unfavorable for the growth of follow-up cap so that the uniformity of SRAM region SiGe cap is very poor
(<111>The cap thickness low LCL of crystal face growth, hardly grows).And the SiGe epitaxial layer of high Ge content, it is impossible to metal
Nickel reactant, forms metal silicide (NiSi or NiGeSi), so as to cause the contact between follow-up CT and SiGe layer not good, causes
The problems such as electric leakage, resistance are raised, resistance is uncontrollable.And adopt the cap that Distributed Control System (DCS) grows then easily to occur
The technological problemses of PPU short circuit.
For this reason, it may be necessary to a kind of new technical scheme, improves cap pattern, be conducive to subsequent metal silicide (NiSi)
Formed.
Content of the invention
The technical problem to be solved is there is drawbacks described above in prior art, and providing one kind can improve
Cap pattern method in embedded SiGe technique, is conducive to the formation of subsequent metal silicide (NiSi), while can keep away
Exempt from the PPU short circuit in SRAM region.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided a kind of semiconductor device preparation method, including：
First step：Semiconductor substrate is provided, and pattern etched semiconductor substrate is to form depression；
Second step：In the interior epitaxial growth sige material of semiconductor substrate depression；
Third step：The first cap is formed in sige material Epitaxial growth；
Four steps：In first the second cap of cap Epitaxial growth.
Preferably, in described semiconductor device preparation method, the semiconductor device preparation method is used for manufacturing
PMOS semiconductor device.
Preferably, in described semiconductor device preparation method, the first cap exists<111>Face with<100>On the face of face
Growth rate ratio be 1～50%.
Preferably, in described semiconductor device preparation method, the second cap exists<111>Face with<100>On the face of face
Growth rate ratio be 50～100%.
Preferably, in described semiconductor device preparation method, the thickness of the first cap and the second cap is than being situated between
Between 0.5 to 2.
Preferably, in described semiconductor device preparation method, the semiconductor substrate is made up of monocrystal silicon.
Preferably, in described semiconductor device preparation method, the semiconductor substrate is by soi semiconductor material structure
Become.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided a kind of using above-mentioned semiconductor device preparation method
The semiconductor device that makes.
Cap pattern can be significantly improved after double-canopy cap technique using the semiconductor device preparation method of the present invention, have
Formation beneficial to subsequent metal silicide (NiSi).
Description of the drawings
In conjunction with accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 schematically shows the first step of semiconductor device preparation method according to the preferred embodiment of the invention and obtains
The the first section semiconductor structure diagram for arriving.
Fig. 2 schematically shows the first step of semiconductor device preparation method according to the preferred embodiment of the invention and obtains
The the second section semiconductor structure diagram for arriving.
Fig. 3 schematically shows the second step of semiconductor device preparation method according to the preferred embodiment of the invention and obtains
The the first section semiconductor structure diagram for arriving.
Fig. 4 schematically shows the second step of semiconductor device preparation method according to the preferred embodiment of the invention and obtains
The the second section semiconductor structure diagram for arriving.
Fig. 5 schematically shows the third step of semiconductor device preparation method according to the preferred embodiment of the invention and obtains
The the first section semiconductor structure diagram for arriving.
Fig. 6 schematically shows the third step of semiconductor device preparation method according to the preferred embodiment of the invention and obtains
The the second section semiconductor structure diagram for arriving.
Fig. 7 schematically shows the four steps of semiconductor device preparation method according to the preferred embodiment of the invention and obtains
The the first section semiconductor structure diagram for arriving.
Fig. 8 schematically shows the four steps of semiconductor device preparation method according to the preferred embodiment of the invention and obtains
The the second section semiconductor structure diagram for arriving.
It should be noted that accompanying drawing is used for the present invention to be described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Also, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
The present invention relates in terms of semiconductor device processing technology, a kind of more particularly to embedded SiGe epitaxial growth of improvement
The method of cap pattern in technique, using this method using cap pattern can be significantly improved after double-canopy cap technique, favorably
In the formation of subsequent metal silicide (NiSi), while the PPU short circuit in SRAM region can be avoided.
Fig. 1 to Fig. 8 schematically shows each of semiconductor device preparation method according to the preferred embodiment of the invention
The section semiconductor structure diagram that step is obtained.
Specifically, as shown in Figures 1 to 8, semiconductor device preparation method according to the preferred embodiment of the invention includes：
First step：Semiconductor substrate is provided, and pattern etched semiconductor substrate is to form depression 10；
Second step：In the interior epitaxial growth sige material 20 of semiconductor substrate depression；
Third step：The first cap 30 is formed in 20 Epitaxial growth of sige material；
Four steps：In 30 the second cap of Epitaxial growth 40 of the first cap.
For example, the semiconductor substrate is made up of monocrystal silicon.Or, for example, the semiconductor substrate is by soi semiconductor material
Material is constituted.
Preferably, the first cap 30 exists<111>Face with<100>Growth rate ratio about 1～50% or so on the face of face.
Preferably, the second cap 40 exists<111>Face with<100>Growth rate on the face of face is more left than about 50～100%
Right.
It is further preferred that the thickness proportion of two-layer cap arbitrarily can be adjusted as needed.For instance, it is preferred that first
The thickness ratio of cap 30 and the second cap 40 is between 0.5 to 2.
It should be noted that can first grow the first cap when concrete growth to grow the second cap again, it is also possible to first
Long second cap grows the first cap again, and the growth sequencing of two-layer cap is not limited.
For example, the semiconductor device preparation method is advantageously used for manufacturing PMOS semiconductor device.
Cap pattern can be significantly improved after double-canopy cap technique using the semiconductor device preparation method of the present invention, have
Formation beneficial to subsequent metal silicide (NiSi).
Furthermore, it is necessary to illustrate, unless stated otherwise or point out, term " first " otherwise in description, "
Two ", the description such as " 3rd " is used only for each component in differentiation description, element, step etc., rather than for representing each
Logical relation or ordering relation between component, element, step etc..
It is understood that although the present invention is disclosed as above with preferred embodiment, but above-described embodiment it is not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Many possible variations being made all to technical solution of the present invention using the technology contents of the disclosure above and modify, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
Interior.
And it should also be understood that the present invention is not limited to specific method described herein, compound, material, system
Technology, usage and application is made, they can change.It should also be understood that term described herein be used merely to describe specific
Embodiment, rather than be used for limiting the scope of the present invention.Must be noted that herein and claims used in
Singulative " one ", " one kind " and " being somebody's turn to do " include complex reference, unless context explicitly indicates that contrary.Therefore, example
Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
Multiple steps or the citation of device, and potentially include secondary step and second unit.Should be managed with broadest implication
All conjunctions that solution is used.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as also quoting from the function of the structure
Equivalent.Can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
And, the method for the embodiment of the present invention and/or the realization of system may include manual, automatic or execute in combination selected
Task.And, the real instrument of the embodiment of the method according to the invention and/or system and equipment are logical using operating system
Cross hardware, software or its combination and realize several selected tasks.
Claims (8)
1. a kind of semiconductor device preparation method, it is characterised in that include：
First step：Semiconductor substrate is provided, and pattern etched semiconductor substrate is to form depression；
Second step：In the interior epitaxial growth sige material of semiconductor substrate depression；
Third step：The first cap is formed in sige material Epitaxial growth；
Four steps：In first the second cap of cap Epitaxial growth.
2. semiconductor device preparation method according to claim 1, it is characterised in that the semiconductor device preparation method
For manufacturing PMOS semiconductor device.
3. semiconductor device preparation method according to claim 1 and 2, it is characterised in that the first cap exists<111>Face
With<100>Growth rate ratio on the face of face is 1～50%.
4. semiconductor device preparation method according to claim 1 and 2, it is characterised in that the second cap exists<111>Face
With<100>Growth rate ratio on the face of face is 50～100%.
5. semiconductor device preparation method according to claim 1 and 2, it is characterised in that the first cap and the second lid
The thickness ratio of cap layers is between 0.5 to 2.
6. semiconductor device preparation method according to claim 1 and 2, it is characterised in that the semiconductor substrate is by list
Crystal silicon is constituted.
7. semiconductor device preparation method according to claim 1 and 2, it is characterised in that the semiconductor substrate is by SOI
Semi-conducting material is constituted.
8. the semiconductor device that a kind of semiconductor device preparation method using according to one of claim 1 to 7 is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610984921.5A CN106449414B (en) | 2016-11-09 | 2016-11-09 | Semiconductor devices and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610984921.5A CN106449414B (en) | 2016-11-09 | 2016-11-09 | Semiconductor devices and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106449414A true CN106449414A (en) | 2017-02-22 |
| CN106449414B CN106449414B (en) | 2019-07-23 |
Family
ID=58207286
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610984921.5A Active CN106449414B (en) | 2016-11-09 | 2016-11-09 | Semiconductor devices and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112201691A (en) * | 2020-09-28 | 2021-01-08 | 上海华力集成电路制造有限公司 | Germanium-silicon source drain structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244263A (en) * | 2015-10-21 | 2016-01-13 | 上海集成电路研发中心有限公司 | Manufacturing method for improving quality of SiGe source and drain area |
| CN105261567A (en) * | 2015-10-27 | 2016-01-20 | 上海华力微电子有限公司 | Method for preparing cap layer of embedded epitaxial silicon-germanium layer |
| CN105742284A (en) * | 2016-02-26 | 2016-07-06 | 上海华力微电子有限公司 | Fabrication method of semiconductor device and semiconductor device |
-
2016
- 2016-11-09 CN CN201610984921.5A patent/CN106449414B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244263A (en) * | 2015-10-21 | 2016-01-13 | 上海集成电路研发中心有限公司 | Manufacturing method for improving quality of SiGe source and drain area |
| CN105261567A (en) * | 2015-10-27 | 2016-01-20 | 上海华力微电子有限公司 | Method for preparing cap layer of embedded epitaxial silicon-germanium layer |
| CN105742284A (en) * | 2016-02-26 | 2016-07-06 | 上海华力微电子有限公司 | Fabrication method of semiconductor device and semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112201691A (en) * | 2020-09-28 | 2021-01-08 | 上海华力集成电路制造有限公司 | Germanium-silicon source drain structure and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN106449414B (en) | 2019-07-23 |
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