CN106409686A - Method of manufacturing oxide semiconductor film transistor - Google Patents

Method of manufacturing oxide semiconductor film transistor Download PDF

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Publication number
CN106409686A
CN106409686A CN201510480819.7A CN201510480819A CN106409686A CN 106409686 A CN106409686 A CN 106409686A CN 201510480819 A CN201510480819 A CN 201510480819A CN 106409686 A CN106409686 A CN 106409686A
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CN
China
Prior art keywords
oxide semiconductor
semiconductor layer
acid
crystal
state
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CN201510480819.7A
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Chinese (zh)
Inventor
张锡明
黄彦馀
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Chunghwa Picture Tubes Ltd
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Chunghwa Picture Tubes Ltd
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Priority to CN201510480819.7A priority Critical patent/CN106409686A/en
Publication of CN106409686A publication Critical patent/CN106409686A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The invention discloses a method of manufacturing an oxide semiconductor film transistor. The method comprises the following steps of providing a patterning amorphous oxide semiconductor layer; carrying out polycrystallization on the patterning amorphous oxide semiconductor layer so as to form a patterning polycrystalline oxide semiconductor layer; forming a source electrode and a drain electrode on the patterning polycrystalline oxide semiconductor layer; providing a grid electrode; and providing brake dielectric layers between the grid electrode and the patterning polycrystalline oxide semiconductor layer, and the source electrode and the drain electrode. In the method, the patterning polycrystalline oxide semiconductor layer which has an etching solution resistance characteristic is firstly formed, and then the source electrode and the drain electrode are formed too. Therefore, the etching solution is used to form the source electrode and the drain electrode, the patterning polycrystalline oxide semiconductor layer is not damaged.

Description

The method manufacturing oxide semiconductor thin-film electric crystal
Technical field
The present invention relates to a kind of method manufacturing oxide semiconductor thin-film electric crystal.
Background technology
Display panels comprise thin film transistor base, colored filter substrate and are located at membrane transistor Layer of liquid crystal molecule between substrate and colored filter substrate.Multiple films are configured on thin film transistor base Electric crystal, each membrane transistor comprises grid, gate dielectric layer, semiconductor layer, source electrode and drain electrode. The material of semiconductor layer for example can comprise non-crystalline silicon, polysilicon, microcrystal silicon, monocrystalline silicon, organic semiconductor, Oxide semiconductor or other suitable materials.
Compared to amorphous silicon membrane electric crystal, oxide semiconductor thin-film electric crystal has higher carrier and moves Shifting rate (Mobility), and have preferably electrical performance.But after forming oxide semiconductor layer, When forming source electrode and drain electrode, easily damage oxide semiconductor layer, and then lead to oxide semiconductor thin Film electric crystal lost efficacy.Therefore, it is badly in need of a kind of manufacture oxide semiconductor thin-film electric crystal of improvement at present Method, to solve the above problems.
Content of the invention
As stated in the Background Art, after forming oxide semiconductor layer, when forming source electrode and drain electrode, Easily infringement oxide semiconductor layer, and then lead to oxide semiconductor thin-film electric crystal to lose efficacy.This be because By being used etching solution meeting etching of oxides semiconductor layer when forming source electrode and drain electrode.Therefore, the present invention Purpose be to provide a kind of method manufacturing oxide semiconductor thin-film electric crystal, its be initially formed against corrosion Carve the patterned polysilicon state oxide semiconductor layer of liquid, re-form source electrode and drain electrode.Consequently, it is possible to make When forming source electrode and drain electrode with etching solution, patterned polysilicon state oxide semiconductor layer will not be hurt, and Can problem described in effectively solving prior art.
The present invention provides a kind of method manufacturing oxide semiconductor thin-film electric crystal, and it comprises:Figure is provided Case non-crystal oxide semiconductor layer;Polycrystallization patterns non-crystal oxide semiconductor layer, to be formed Patterned polysilicon state oxide semiconductor layer;Source electrode is formed on patterned polysilicon state oxide semiconductor layer And drain electrode;Grid is provided;And provide positioned at grid and patterned polysilicon state oxide semiconductor layer, source Gate dielectric layer between pole and drain electrode.
According to one embodiment of the invention, pattern non-crystal oxide semiconductor layer comprise amorphous state indium oxide, Amorphous state indium gallium zinc, amorphous state indium gallium, amorphous state indium zinc oxide or a combination thereof.
According to one embodiment of the invention, polycrystallization patterning non-crystal oxide semiconductor layer step is included into Row heat treatment, laser treatment, infra red treatment or its group.
According to one embodiment of the invention, the wherein temperature of heat treatment is more than or equal to 250 DEG C, patterns amorphous State oxide semiconductor layer comprises amorphous state indium oxide.
According to one embodiment of the invention, patterning non-crystal oxide semiconductor layer step is provided to comprise:Shape Become non-crystal oxide semiconductor layer;And non-crystal oxide semiconductor layer is carried out with the first lithographic and One etch process, to form patterning non-crystal oxide semiconductor layer, wherein to non-crystal oxide half Conductor layer carries out the first lithographic and the first etch process step comprises using the first acid etching non-crystal oxide Semiconductor layer.
According to one embodiment of the invention, the wherein first acid comprises oxalic acid, citric acid, acetic acid or a combination thereof.
According to one embodiment of the invention, source electrode and leakage are formed on patterned polysilicon state oxide semiconductor layer Pole step comprises:Form conductive layer;And conductive layer is carried out with the second lithographic and the second etch process, with Form source electrode and drain electrode, wherein the second lithographic is carried out to conductive layer and the second etch process comprises to use second Acid etching conductive layer, the pKa value of the second acid is more than the pKa value of the first acid.
According to one embodiment of the invention, the wherein second acid comprises hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, hydrogen fluorine Acid or a combination thereof.
According to one embodiment of the invention, the wherein erosion to the second acid for the patterned polysilicon state oxide semiconductor layer Etching speed is less than or equal to 20 nm/minute.
According to one embodiment of the invention, conductive layer is to the second acid and patterned polysilicon state oxide semiconductor layer 30 are more than or equal to the etching selectivity of the second acid:1.
Brief description
It is that above and other purpose, feature, advantage and the embodiment of the present invention can be become apparent, institute Being described as follows of accompanying drawings:
Figure 1A-Fig. 1 I is the method illustrating the manufacture membrane transistor according to one embodiment of the invention in each technique The generalized section in stage.
Fig. 2 is the film illustrating according to obtained by the method for the manufacture membrane transistor of another embodiment of the present invention The generalized section of electric crystal.
Specific embodiment
As described in prior art, after forming oxide semiconductor layer, when forming source electrode and drain electrode, Easily infringement oxide semiconductor layer, and then lead to oxide semiconductor thin-film electric crystal to lose efficacy.This be because By being used etching solution meeting etching of oxides semiconductor layer when forming source electrode and drain electrode.Therefore, the present invention Purpose be to provide a kind of method manufacturing oxide semiconductor thin-film electric crystal, its be initially formed against corrosion Carve the patterned polysilicon state oxide semiconductor layer of liquid, re-form source electrode and drain electrode.Consequently, it is possible to make When forming source electrode and drain electrode with etching solution, patterned polysilicon state oxide semiconductor layer will not be hurt, and Can problem described in effectively solving prior art.
Figure 1A-Fig. 1 I is each work of the method illustrating the manufacture membrane transistor according to one embodiment of the invention Skill stage generalized section.First, as shown in Figure 1A, form grid G on substrate 110.One In embodiment, when forming grid G, form scan line (not illustrating) on substrate 110, grid G simultaneously And scan line belongs to same patterned conductive layer.Grid G and scan line can be single or multiple lift structure, its Material can be metal or alloy, for example molybdenum (Mo), chromium (Cr), aluminium (Al), neodymium (Nd), titanium (Ti), copper (Cu), Silver-colored (Ag), golden (Au), zinc (Zn), indium (In), gallium (Ga), other suitable metals or combinations of the above.Lift For example, available sputter (sputtering), evaporation (evaporation) technique or other film deposition techniques Be initially formed layer of metal layer (not illustrating) on substrate 110, recycle lithography technique formed grid G with Scan line.
As shown in Figure 1B, form gate dielectric layer 120 and cover grid G.In one embodiment, gate dielectric layer 120 also cover scan line.Gate dielectric layer 120 can be single or multiple lift structure, and its material can be organic dielectric Material or Inorganic Dielectric Material.Organic dielectric materials can be pi (Polyimide, PI);Inorganic dielectric Material is, for example, silica, silicon nitride, silicon oxynitride or combinations of the above.Chemical gaseous phase for example can be utilized Sedimentation (chemical vapor deposition, CVD) or other suitable film deposition techniques form lock and are situated between Electric layer 120.
Then, as shown in Fig. 1 C- Fig. 1 D, formed patterning non-crystal oxide semiconductor layer PAOS in On gate dielectric layer 120.Specifically, as shown in Figure 1 C, first code-pattern forms non-crystal oxide and partly leads Body layer AOS is on gate dielectric layer 120.Available vacuum coating (such as sputter or evaporation) or wet (such as rotary coating (spin coating), slot coated (slit coating) or ink jet printing (ink jet printing)) Form non-crystal oxide semiconductor layer AOS.In one embodiment, non-crystal oxide semiconductor layer AOS Comprise amorphous state indium oxide, amorphous state indium gallium zinc, amorphous state indium gallium, amorphous state indium zinc oxide Or a combination thereof.In other embodiments, non-crystal oxide semiconductor layer AOS comprise amorphous zinc oxide, Amorphous zinc oxide tin, amorphous state chromium oxide tin, amorphous state gallium oxide tin, amorphous titanium peroxide tin, non- Crystalline state cupric oxide aluminium, amorphous state strontium oxide strontia copper, amorphous state sulphur lanthana copper, other be suitable for materials or on The combination stated.
Then, as shown in figure ip, non-crystal oxide semiconductor layer AOS is carried out with the first lithographic and One etch process, to form patterning non-crystal oxide semiconductor layer PAOS.In one embodiment, scheme Case non-crystal oxide semiconductor layer PAOS comprise amorphous state indium oxide, amorphous state indium gallium zinc, Amorphous state indium gallium, amorphous state indium zinc oxide or a combination thereof.In one embodiment, the first lithographic and One etch process comprises to form photoresistance (not illustrating) on non-crystal oxide semiconductor layer AOS;To photoresistance It is exposed and developing process, to form patterning photoresistance;Baking patterning photoresistance;According to patterning light Resistance, etching method for amorphous state oxide semiconductor layer AOS;And strip pattern photoresistance.In one embodiment, Non-crystal oxide semiconductor layer AOS is carried out with the first lithographic and the first etch process step comprises to use One acid etching non-crystal oxide semiconductor layer AOS.In one embodiment, the first acid comprises oxalic acid, lemon Lemon acid, acetic acid or a combination thereof.In one embodiment, the pKa value of the first acid is more than or equal to 1.38.? In one embodiment, the pKa value of the first acid is more than or equal to 4.74, even greater than or equal to 4.76.
Subsequently, as referring to figure 1e, polycrystallization patterning non-crystal oxide semiconductor layer PAOS, with shape Become patterned polysilicon state oxide semiconductor layer PPOS.In one embodiment, patterned polysilicon state oxide Semiconductor layer PPOS comprises polycrystalline state indium oxide, polycrystalline state indium gallium zinc, polycrystalline state indium gallium, many Crystalline state indium zinc oxide or a combination thereof.In one embodiment, polycrystallization patterning non-crystal oxide semiconductor Layer step comprises to be heat-treated (can use high temperature furnace), and the temperature of heat treatment is more than or equal to 250 DEG C, very To more than or equal to 300 DEG C.In one embodiment, the temperature of heat treatment is less than or equal to 1400 DEG C, very To less than or equal to 1000 DEG C.In one embodiment, patterning non-crystal oxide semiconductor layer comprise non- Crystalline state indium oxide, its crystallization temperature is more than or equal to 250 DEG C, and the temperature of therefore heat treatment is more than or equal to 250℃.In one embodiment, patterning non-crystal oxide semiconductor layer comprises amorphous state indium gallium zinc, Its crystallization temperature is more than or equal to 700 DEG C, and therefore the temperature of heat treatment is more than or equal to 700 DEG C.Real one Apply in example, polycrystallization patterning non-crystal oxide semiconductor layer step comprises to carry out to be heat-treated, laser (laser) Process, infrared ray (IR) process, other suitable techniques or a combination thereof, but not limited to this.
Next, as shown in Fig. 1 F- Fig. 1 G, forming source S and drain D and aoxidize in patterned polysilicon state On thing semiconductor layer PPOS.Specifically, as shown in fig. 1f, first code-pattern formed conductive layer CL in On patterned polysilicon state oxide semiconductor layer PPOS.Sputter, evaporation process for example can be utilized or other are thin Film deposition technique forms conductive layer CL on patterned polysilicon state oxide semiconductor layer PPOS.Conductive layer CL can be single or multiple lift structure, and its material can be metal or alloy, for example molybdenum, chromium, aluminium, neodymium, titanium, Copper, silver, gold, zinc, indium, gallium, other suitable metals or combinations of the above.
Then, as shown in Figure 1 G, the second lithographic and the second etch process are carried out to conductive layer CL, with shape Become source S and drain D.In one embodiment, when forming source S and drain D, form money simultaneously Stockline (not illustrating) on patterned polysilicon state oxide semiconductor layer PPOS, source S, drain D and money Stockline belongs to same patterned conductive layer.In one embodiment, the second lithographic and the second etch process comprise Form photoresistance (not illustrating) on conductive layer CL;Photoresistance is exposed and developing process, to form pattern Change photoresistance;Baking patterning photoresistance;According to patterning photoresistance, etch conductive layer CL;And strip pattern Change photoresistance.In one embodiment, conductive layer CL is carried out with the second lithographic and the second etch process comprises to use Second acid etching conductive layer CL.In one embodiment, the pKa value of the second acid is more than the pKa of the first acid Value.In one embodiment, the second acid comprises hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, hydrofluoric acid or a combination thereof. In one embodiment, the pKa value of the second acid is less than or equal to 3.15.In one embodiment, second acid PKa value is less than or equal to 2.12.In one embodiment, the pKa value of the second acid be less than or equal to 0, or even It is less than or equal to -1, -2 or -3.
It should be noted that in one embodiment, patterned polysilicon state oxide semiconductor layer PPOS is to The etch-rate of diacid is less than or equal to 20 nm/minute, even less than or equal to 2 nm/minute.? In one embodiment, conductive layer CL is to the second acid and patterned polysilicon state oxide semiconductor layer PPOS to the The etching selectivity of diacid is more than or equal to 30:1, even greater than or equal to 300:1.Therefore, make During with the second acid etching conductive layer CL to form source S and drain D, patterned polysilicon state will not be injured Oxide semiconductor layer PPOS, thus the problem described in effectively solving prior art.
Then, as shown in fig. 1h, form protective layer 130 overlay pattern polycrystalline state oxide semiconductor layer PPOS, source S and drain D.Protective layer 130 has the drain electrode that a contact hole 130a exposes a part D.Protective layer 130 be single or multiple lift structure, its material can comprise organic dielectric material, inorganic dielectric material or Combinations of the above, for example, can be utilized chemical vapour deposition technique or other suitable film deposition techniques to be formed and protect Protective material layer (does not illustrate), recycles lithography technique to form contact hole 130a.
As shown in Figure 1 I, form pixel electrode PE on protective layer 130 and contact hole 130a (see Fig. 1 H) Interior, make pixel electrode PE connect drain D.Pixel electrode PE can be single or multiple lift structure, its material May be, for example, tin indium oxide, hafnium oxide, aluminum zinc oxide, aluminum oxide tin, gallium oxide zinc, indium oxide titanium, Indium oxide molybdenum or other transparent conductive materials.For example can be first with sputtering process or other film deposition techniques shapes Become layer of transparent conductive layer (not illustrating) on protective layer 130, recycle lithography technique to form picture element electricity Pole PE.
Fig. 2 is to illustrate according to thin obtained by the method for the manufacture membrane transistor of another embodiment of the present invention The generalized section of film electric crystal.The difference of Fig. 2 and Fig. 1 I is, Fig. 2 is top lock type membrane transistor, Fig. 1 I is bottom lock type membrane transistor.As shown in Fig. 2 first, form patterning non-crystal oxide half On substrate 110, then polycrystallization patterns non-crystal oxide semiconductor layer to conductor layer (not illustrating), To form patterned polysilicon state oxide semiconductor layer PPOS.Then, formed source S and drain D in On patterned polysilicon state oxide semiconductor layer PPOS.Form gate dielectric layer 120 overlay pattern polycrystalline state Oxide semiconductor layer PPOS, source S and drain D.Form grid G on gate dielectric layer 120.Shape Protective layer 130 is become to cover grid G.Form pixel electrode PE on protective layer 130, and pixel electrode The contact hole (sign) that PE passes through protective layer 130 connects drain D.Above-mentioned steps refer to above-mentioned reality Apply example.
In sum, because patterned polysilicon state oxide semiconductor layer has extremely low etching to the second acid Speed, and conductive layer etching choosing to the second acid with patterned polysilicon state oxide semiconductor layer to the second acid Select ratio high, therefore when with the second acid etching conductive layer to form source electrode and drain electrode, pattern will not be injured Change polycrystalline state oxide semiconductor layer, thus the problem described in effectively solving prior art.
Although the present invention is open as above with embodiment, so it is not limited to the present invention, any Those skilled in the art, without departing from the spirit and scope of the present invention, when can make various change with retouching, Therefore protection scope of the present invention is worked as and is defined depending on as defined in claim.

Claims (10)

1. a kind of method manufacturing oxide semiconductor thin-film electric crystal is it is characterised in that described manufacture oxygen The method of compound semiconductive thin film electric crystal comprises:
Patterning non-crystal oxide semiconductor layer is provided;
Non-crystal oxide semiconductor layer is patterned, to form patterned polysilicon state oxide described in polycrystallization Semiconductor layer;
Source electrode and drain electrode are formed on described patterned polysilicon state oxide semiconductor layer;
Grid is provided;And
There is provided and be located at described grid and described patterned polysilicon state oxide semiconductor layer, described source electrode and institute State the gate dielectric layer between drain electrode.
2. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 1, its feature exists In described patterning non-crystal oxide semiconductor layer comprises amorphous state indium oxide, amorphous state indium gallium Zinc, amorphous state indium gallium, amorphous state indium zinc oxide or a combination thereof.
3. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 1, its feature exists In patterning non-crystal oxide semiconductor layer step described in described polycrystallization comprises to carry out being heat-treated, swashs Light process, infra red treatment or a combination thereof.
4. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 3, its feature exists In the temperature of described heat treatment is more than or equal to 250 DEG C, described patterning non-crystal oxide semiconductor layer Comprise amorphous state indium oxide.
5. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 1, its feature exists In, provide described patterning non-crystal oxide semiconductor layer step comprise:
Form non-crystal oxide semiconductor layer;And
First lithographic and the first etch process are carried out to described non-crystal oxide semiconductor layer, to be formed State patterning non-crystal oxide semiconductor layer, wherein institute is carried out to described non-crystal oxide semiconductor layer State the first lithographic and described first etch process step comprises using non-crystal oxide described in the first acid etching Semiconductor layer.
6. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 5, its feature exists In described first acid comprises oxalic acid, citric acid, acetic acid or a combination thereof.
7. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 5, its feature exists In described source electrode being formed on described patterned polysilicon state oxide semiconductor layer and described drain electrode step comprises:
Form conductive layer;And
Described conductive layer is carried out with the second lithographic and the second etch process, to form described source electrode and described leakage Pole, wherein carries out described second lithographic to described conductive layer and described second etch process comprises to use second Conductive layer described in acid etching, the pKa value of described second acid is more than the pKa value of described first acid.
8. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 7, its feature exists In described second acid comprises hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, hydrofluoric acid or a combination thereof.
9. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 7, its feature exists In described patterned polysilicon state oxide semiconductor layer is less than or equal to the etch-rate of described second acid 20 nm/minute.
10. the method manufacturing oxide semiconductor thin-film electric crystal as claimed in claim 7, its feature It is, sour to the described second and described patterned polysilicon state oxide semiconductor layer of described conductive layer is to described The etching selectivity of the second acid is more than or equal to 30:1.
CN201510480819.7A 2015-08-03 2015-08-03 Method of manufacturing oxide semiconductor film transistor Pending CN106409686A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192844A (en) * 2021-04-09 2021-07-30 电子科技大学 Based on CO2Oxide film crystallization method of laser annealing process

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CN102122673A (en) * 2010-11-30 2011-07-13 友达光电股份有限公司 Oxide semiconductor thin film transistor structure and manufacturing method thereof
US20120001179A1 (en) * 2010-07-02 2012-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102569413A (en) * 2011-12-13 2012-07-11 华映视讯(吴江)有限公司 Thin film transistor and manufacturing method thereof
CN102646716A (en) * 2011-02-17 2012-08-22 索尼公司 Thin film transistor, manufacturing method of thin film transistor and display
CN103794652A (en) * 2014-02-25 2014-05-14 华南理工大学 Metal-oxide semiconductor thin film transistor and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120001179A1 (en) * 2010-07-02 2012-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
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CN102646716A (en) * 2011-02-17 2012-08-22 索尼公司 Thin film transistor, manufacturing method of thin film transistor and display
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* Cited by examiner, † Cited by third party
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CN113192844A (en) * 2021-04-09 2021-07-30 电子科技大学 Based on CO2Oxide film crystallization method of laser annealing process

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Application publication date: 20170215