CN106409669A - Method for forming a wafer structure, a method for forming a semiconductor device and a wafer structure - Google Patents
Method for forming a wafer structure, a method for forming a semiconductor device and a wafer structure Download PDFInfo
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- CN106409669A CN106409669A CN201610824797.6A CN201610824797A CN106409669A CN 106409669 A CN106409669 A CN 106409669A CN 201610824797 A CN201610824797 A CN 201610824797A CN 106409669 A CN106409669 A CN 106409669A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
- H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Ceramic Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention relates to a method for forming a wafer structure, a method for forming a semiconductor device and a wafer structure. A method of producing a semiconductor device and a wafer structure are provided. The method includes attaching a donor wafer (10) comprising silicon carbide to a carrier wafer (20) comprising graphite, splitting the donor wafer (10) along an internal delamination layer (13) so that a split layer (1) comprising silicon carbide and attached to the carrier wafer (20) is formed, removing the carrier wafer (20) above an inner portion of the split layer (1) while leaving a residual portion (20') of the carrier wafer (20) attached to the split layer (1) to form a partially supported wafer (100, 200), and further processing the partially supported wafer (100, 200).
Description
Technical field
Embodiments of the invention are related to chip architecture, more particularly, to include the chip knot of silicon carbide wafer and supporting construction
Structure, method and the method for forming semiconductor device for forming chip architecture.
Background technology
In order to improve the device property of semiconductor device, make trial to reduce the final thickness of semi-conducting material.Especially
It is for power semiconductor it is usually desirable to the semiconductor body of this device has simply be enough to containment device or circuit
Thickness.
Make it easy to rupture because the brittle semiconductor materials of such as carborundum (SiC) are once thinning, therefore thin quasiconductor
The manufacture of chip and chip and process are typically complexity.Additionally, monocrystal SiC is costly.In order to improve thin quasiconductor material
The mechanical stability of material, has been developed for carrier system.A kind of approach is using the polycrystalline Si C (poly- being attached to monocrystal SiC layer
SiC) carrier wafer.Can peel off subsequently by single crystal SiC substrate is bound directly to carrier wafer and from this carrier wafer
This single crystal SiC substrate leaves the single crystalline substrate of part on this carrier wafer simultaneously, to form this structure.Although comparing monocrystal SiC
Inexpensively, but poly-SiC carrier wafer is still costly.Additionally, the boundary being formed between poly-SiC and monocrystal SiC
Face needs special care.Which increase processing cost.
Due to these and other former so that the present invention.
Content of the invention
According to the embodiment of the method forming semiconductor device, the method includes：The donor wafer of carborundum will be included
(donor wafer) is attached to the carrier wafer including graphite；Along internal peel ply (delamination layer) division
Donor wafer makes to be attached to carrier wafer including the cleavage layer of carborundum；Form the chip being partially supported through his arms；And further
Process the chip being partially supported through his arms.Form the chip being partially supported through his arms to include removing carrier crystalline substance on the interior section of cleavage layer
Piece leaves the remainder of the carrier wafer being attached to cleavage layer simultaneously.
According to the embodiment of the method for forming chip architecture, the method includes：The carborundum with the first side is provided
Chip；High energy particle is injected from the first lateral silicon carbide wafer；First side switch of silicon carbide wafer is bonded to including graphite
Carrier wafer；And divide ground floor from silicon carbide wafer.The method further includes at moves on the interior section of ground floor
Except carrier wafer only partly covers the supporting construction of this ground floor with formation at ground floor, or depositing silicon on cleavage layer
Remove after silicon layer carrier wafer and at silicon carbide layer formed supporting construction make supporting construction only part cover carborundum
Layer.
According to the embodiment of chip architecture, chip architecture includes silicon carbide wafer and supporting construction, supporting construction include silicon,
At least one of carborundum, graphite and glass.Supporting construction is glued in the outer peripheral areas of silicon carbide wafer, and only part
Ground covers silicon carbide wafer, and when viewed from above, outer peripheral areas are around the device area of silicon carbide wafer.
Reading detailed description below and when checking accompanying drawing, it would be recognized by those skilled in the art that additional feature and excellent
Point.
Brief description
Part in accompanying drawing is not necessarily to scale, but focuses in the principle of the explanation present invention.Additionally, in accompanying drawing
In, same reference specifies corresponding part.In the accompanying drawings：
Figure 1A to 1G illustrates according to embodiment respectively for forming the method and step of the method for chip architecture and semiconductor device；
Fig. 2A to 2F illustrates according to embodiment respectively for forming the method and step of the method for chip architecture and semiconductor device；
Fig. 3 A to 3D illustrates according to embodiment respectively for forming the method and step of the method for chip architecture and semiconductor device；
Fig. 4 A to 4E illustrates according to embodiment respectively for forming the method and step of the method for chip architecture and semiconductor device；
Fig. 5 A illustrates the top view of the chip architecture according to embodiment；
Fig. 5 B illustrates the top view of the chip architecture according to another embodiment；
Fig. 5 C illustrates the vertical cross-section of the through-wafer structure according to embodiment；And
Fig. 5 D illustrates the vertical cross-section of the through-wafer structure according to embodiment.
Specific embodiment
In the following detailed description reference is carried out to accompanying drawing, accompanying drawing forms a part of this paper and passes through in the accompanying drawings
The mode of diagram illustrates wherein can put into practice only certain embodiments of the present invention.At this point, the term of directivity such as " push up ",
" bottom ", "front", "rear", " first ", " tail " etc. to use with reference to the orientation of just (one or more) accompanying drawing of description.Due to embodiment
Part can be positioned in multiple different orientations, so the term of directivity is used and absolutely for illustration purposes
It is not to limit.It is understood that using other embodiments and structure or logical changes can be made without deviating from this
The scope of invention.The following detailed description therefore must not be construed in a limiting sense, and the scope of the present invention is by appended
Claim limits.
Various embodiments will be carried out referring in detail to one or more of embodiment example is illustrated in accompanying drawing now
In.Each example is provided by way of explaining, and is not intended to the restriction as the present invention.For example it is illustrated that or being described as
The feature of the part of one embodiment can be used in other embodiments or be used together to produce together with other embodiments
Still further embodiment.It is intended that the present invention and include this modifications and variations.Example is described using language-specific, and this should not
It is understood to limit scope of the following claims.Accompanying drawing is not proportional and for illustrative purposes only.In order to clear
Chu Qijian, identical element or manufacturing step have passed through identical reference markss in different drawings and have been designated, without
In addition if stating.
Term " level " is intended to the first side of description and Semiconductor substrate or body as used in this specification
Or the orientation that main horizontal side is substantially parallel.This can be the surface of such as chip or tube core.
As used in this specification term " vertical " be intended to description be substantially arranged to vertical with first side
The i.e. orientation parallel with the normal direction of Semiconductor substrate or the first side of body.
In this manual, n doping is referred to as the first conduction type and p doping is referred to as the second conduction type.Replaceable
Ground, semiconductor device can be formed with contrary doping relation, thus the first conduction type can be p doping and second
Conduction type can be n doping.Additionally, some figures by be close to doping type indicate "-" or "+" diagram relatively doping is dense
Degree.For example, " n-" mean to be less than the doping content of the doping content of " n " doped region, and " n+" doped region has than " n " doped region
Bigger doping content.However, the doped region that instruction relative doping concentration is not intended to identical relative doping concentration must have
The absolute doping content of identical, unless otherwise stated.For example, two different n+Doped region can have different absolute doping
Concentration.This is equally for example applied to n+Doped region and p+Doped region.
The specific embodiment of this specification description is related to and is not limited to manufacture the SiC semiconductor device of wafer scale and SiC is brilliant
Piece.
SiC semiconductor device to be manufactured can be power semiconductor.
Term " power semiconductor " as used in this description be intended to description on a single chip there is high electricity
Pressure and/or the semiconductor device of high current switching ability.In other words, power semiconductor is intended for high current, typical case
Be in an ampere scope.In this specification, term " power semiconductor " and " power semiconductor component " are by synonymous use.
Term " field effect " as used in this description is intended to description using insulated gate electrodes or schottky gate electrode
The electric field mediation of the conduction " raceway groove " in semiconductor region is formed and/or the electric conductivity of raceway groove and/or the control of shape.
Figure 1A to 1G illustrates the method for forming chip architecture 100 and SiC semiconductor device on a wafer level respectively
Technique.
SiC donor wafer 10 is provided.SiC donor wafer 10 can be that 101 and Si sides are (also referred to as with C side (also referred to as C face)
For Si face) 102 4H-SiC is polymorphous.Additionally, SiC donor wafer 10 can cut from SiC ingot.
In the example embodiment of diagram in the Figure 1A illustrate the vertical cross-section running through donor wafer 10, particle is typically
Proton is injected into entrance given depth donor wafer 10 from C side 101.In Figure 1A, arrow represents particle injection by a dotted line.
Injection depth can be adjusted by selecting Implantation Energy.
The injection of atom or ion (typically gas ion such as proton) may result in the formation of peel ply 13 respectively, stripping
Absciss layer 13 can be the microscopic bubble layer or microporous layers along donor wafer 10.
Injection depth defines the position of peel ply 13, and therefore the thickness of the stratum disjunctum 1 of carrier wafer 20 is transferred in definition
Degree.For example, have in 5*1016cm-2And 8*1016cm-2Between the 80keV of dosage proton be mainly injected into big in SiC
About 0.5-2 μm of depth.Typically, H+implantation energy is in the range of about 50keV to about 200keV.
Carrier wafer 20 has downside 201 and the upside 202 relative with downside 201, and includes graphite wafer or by stone
Smoky quartz piece is formed.As shown in Figure 1B, carrier wafer 20 typically has the size bigger than donor wafer 10 (parallel to downside
201 and/or upside 202 horizontal direction on extend).However, carrier wafer 20 and donor wafer 10 also can be in the horizontal direction
There is identical extend.
Graphite is one of allotrope known to three kinds of carbon.In this specification, term " graphite wafer " and " carbon is brilliant
Piece " is by synonymous use.
In order to protect graphite wafer not oxidized and prevent the release of carbon particle, carrier wafer 20 is typically by by thin guarantor
Sheath (typically thin SiC layer) around graphite wafer (that is, be made up of graphite or the chip that is substantially made up of graphite) shape
The composite crystal becoming.The SiC layer of carrier wafer 20 can have the thickness in the range of from about 10 to about 2000nm, more typically exists
Thickness in the range of from about 50 to about 500nm.For the sake of clarity, protective layer not shown in the section of Figure 1A and Figure 1B.
Carrier wafer 20 extend vertically typically in the range of from about 10 μm to about 2500 μm, more typically, from about 50 μm to
In the range of about 1500 μm.
In order to form wafer stacking 50, donor wafer 10 is typically injected side with it and is attached to carrier wafer 20, in demonstration
In embodiment, the injection side of donor wafer 10 is C side 101.
Complete for donor wafer 10 to be attached to carrier wafer 20 typically via bonding.Correspondingly, donor wafer 10 and load
Body chip 20 is combined by the bonded layer (also not illustrating in fig. ib) of wafer stacking 50.
Typically implement the bonding between donor wafer 10 and carrier wafer 20 connect so that its can stand for after
It is referred to as the transfer of smart-cut (smart-cut) layer and subsequent epitaxially grown at least about 1300 DEG C or at least about 1450 DEG C
Temperature, for example, be up to about 1600 DEG C of temperature.
Bonding can be realized by bonding.For this reason, ceramic forming polymer precursor (ceramic-forming can be used
Polymer precursor) as adhesive layer.For example, available SiC ceramic forming polymer precursor executes bonding.
Alternatively, spin-coating glass (SoG) can be used as adhesive layer.SoG using promoting initial low-temperature bonding, and can be through
Its middle level must be lived and separate the thermal stress under generable high temperature (800-900 DEG C).SoG adhesive layer can be only used to peel ply 13 foot
When enough deeply being manufactured with device after allowing.
As jointing material, high-temperature technology can be avoided by using the ceramic molding precursor of bonding (for example, bonding SiC precursor)
Lower thermal mismatching between active layer and bond area and the undesirable formation of the conversion zone between bonded layer and active layer.
Ceramic forming polymer precursor may include carbon, silicon and hydrogen or (for example, only) is made up of carbon, silicon and hydrogen.When in bonding
During technique during hydrogen diffusion, only polycrystal carborundum can retain.For example, ceramic forming polymer precursor can be that allyl group gathers
Carbon silane or another Polycarbosilane.
In an embodiment, the one or both sides on bonding side or surface 101,201 are coated with ceramic forming polymer precursor, after
Face is tempering between 200 to 700 DEG C.For example, tempering can be performed at a temperature of about 530 DEG C and reach about 4 hours.
As the Part I of bonding code, ceramic forming polymer precursor can be applied to carrier wafer 20 or donor wafer
10.Alternatively, ceramic forming polymer precursor can be applied on the surface 101,201 of both carrier wafer 20 and donor wafer 10
On.Spin coating or spraying coating process application ceramic forming polymer precursor can for example be passed through.
As indicated by by the pecked line arrow in Figure 1B, carrier wafer 20 hereafter can be with donor wafer 10 in the face of wherein
Side 101,201 ground of application polymer precursor combines, to form composite construction or wafer stacking 50.Make the chip so combining
10,20 through heat-treated (tempering) to form stable and lasting bonding between carrier wafer and donor wafer 10.
In conjunction with after, wafer stacking 50 can be heated to form bonding.For example, temperature range can from about room temperature to about 600 DEG C or
From 200 to 700 DEG C.
Can complete to be tempered wafer stacking 50, second temperature model in the range of second temperature with subsequent in the first temperature range
Enclose different from the first temperature range.Second temperature scope can cover the temperature higher than the first temperature range.For example, second temperature model
Enclosing can be from about 500 DEG C to about 1000 DEG C or even more high.
When being used allyl group Polycarbosilane as precursor, it can be hot under such as 1500 DEG C to 1700 DEG C of high temperature
Solve as polycrystal carborundum (for example, in order to precursor layer is completely converted into polycrystalline Si C).Therefore, during bonding technology, SiC and
Bonded layer between carrier wafer can be changed into SiC itself, therefore, ignores when using the issuable shadow of other kinds of material
Ring, and ensure electrical connectivity in addition.For example, bonded layer can be n doping SiC.
Additionally, by bonded layer is converted to SiC, mechanically or thermally extremely stable bonding can be formed and connects.
The strengthening that bonding connects and the separation (seeing below) of carborundum donor wafer 10 may issue at 700 DEG C -1800 DEG C
Raw.
Therefore, it is usable in three tempering process of execution under different temperatures.However, tempering process is also combined into tool
There is the single technique of given temperature distribution.Additionally, tempering can at least occur under (compacting) pressure temporarily.
In an embodiment, tempering occur in comprising the atmosphere of nitrogen and/or noble gases, for example blanket of nitrogen, argon atmospher,
In the atmosphere of the atmosphere of nitrogen and argon or nitrogen and hydrogen.Because nitrogen is low alms giver in SiC, therefore during being tempered, this is likely to result in
The doping of the adjacent n monocrystal SiC layer of stratum disjunctum and bonded layer (polycrystalline Si C for example, being produced by polymer) is so that vertically lead
Electrically may be increased.
As shown in Figure 1 C, donor wafer 10 is detached along internal peel ply 13.This can be occurred by separating wherein
At least 800 DEG C of high temperature under tempering realizing.This can be further tempering step, such as solution bonding at about 1450 DEG C
(de-bond) annealing reaches about 3 hours, or completes with hardening to be bonded to be connected as the explanation above for Figure 1B simultaneously.
As a result, the SiC stratum disjunctum 1 (being also referred to as smart-cut SiC layer and the first SiC layer below) of donor wafer 10 is protected
Stay at carrier wafer 20.By this way, stratum disjunctum 1 is transferred to carrier wafer 20 (smart-cut layer from donor wafer 10
Transfer).The graphite of carrier wafer 20 can be turbostratic graphite, pyrolytic graphite, isostatic pressing graphite (isostatically
One of pressed graphite) and its mixture.Graphite has the thermal expansion system similar with the thermal coefficient of expansion of SiC
Number.This makes graphite become the most promising carrier material for SiC.Additionally, the thermal coefficient of expansion of graphite can be many by it
Permeability is finely adjusted.
Hereafter, for example stratum disjunctum 1 can be polished by using CMP (chemically mechanical polishing).
The separate section 10 ' of donor wafer 10 can be easily reused (for example, more than 5 times or be more than 10 times) as alms giver, because
The suitable original state for the transfer of smart-cut layer can be recovered as it by polishing and/or extension.This can right and wrong
Often cost-effective.
Replaceable in mentioned code, also additive method (for example, oxygen injection) is suitably adapted for separating and partly leads with transfer
Body layer.
As shown in figure ip, epitaxial sic layer (being also referred to as other silicon carbide layer below) 2 can subsequently be respectively formed at and separate
On layer 1 and at the Si side 11 of stratum disjunctum 1.Epitaxial layer 2 and stratum disjunctum 1 can together with form device wafer 1,2.
Before epitaxial growth, stratum disjunctum 1 can have the thickness of 5 μm, 2 μm, 1 μm or even only 0.5 μm.
In other embodiments (not in the drawings illustrate), stratum disjunctum 1 has and substantially corresponds to device to be manufactured
The thickness of semiconductor body thickness.
Due to executing extension at the Si side 11 of stratum disjunctum 1, therefore can achieve the high-quality crystalline pattern of epitaxial sic layer 2,
Even than the crystalline pattern crystalline pattern evenly of stratum disjunctum 1.Additionally, compared with C side, can at Si side 11 between male extension
Better control over doping.Furthermore, it may be desired to the donor wafer 10 of less (thickness).Correspondingly, transfer donor wafer 10 is thin
The technique of SiC layer 1 can be repeated more often.
In addition, the outer of some difference doping types, different levels of doping and/or different-thickness can be formed on stratum disjunctum 1
Prolong SiC layer 2.For example, the first epitaxial sic layer of high n doping can be formed at stratum disjunctum 1, and can be at the first epitaxial sic layer
Form the second epitaxial sic layer of low n doping.The thickness of the first epitaxial sic layer can be selected according to mechanical stability requirements.Can basis
Type of device and electric pressure are selecting thickness and the doping content of the second epitaxial sic layer.For example, the second epitaxial sic layer can have
There are about 4.5 μm of thickness and about 2*1016/cm3The SiC-MOSFET to be formed at 650V grade to be fabricated for the doping content
In drift region.
The doping of (one or more) epitaxial sic layer 2 can be adjusted during epitaxial growth, but (one or more) extension
The doping of SiC layer 2 may also include the injection of (one or more) dopant and subsequent annealing.
Hereafter, carrier wafer 20 can be removed on the interior section of stratum disjunctum 1, stay simultaneously and be attached to stratum disjunctum 1
The remainder 20 ' of carrier wafer 20.As referring to figure 1e, this can be realized by mask etching.
For example, the mask 7 (for example, silicon nitride mask or silicon oxide mask) in device area with opening can be with respect to
SiC device chip 1,2, is typically formed on carrier wafer 20 at upside 202.The area of the opening of mask 7 is typically big
In about the 50% of stratum disjunctum 1 area, more preferably greater than about the 80% of separation layer area or even 90%.In addition, the opening of mask 7
Mouth can be continuous and/or substantially placed in the middle with respect to stratum disjunctum 1.When viewed from above, the opening of mask 7 can be round
(and mask 7 is continuous) of shape, but can also have thin part, if mask 7 is separated into stem portion by it, such as ring-section.
Hereafter, SiC, such as stratum disjunctum can be exposed using ion beam etching and/or chemical etching and/or plasma etching
1 C side 12.Hereafter, removable mask 7.
For example, the SiC protective layer of carrier wafer 20 can be removed using ion beam etching.Can be (special using plasma etching
It is not plasma ashing) remove graphite on stratum disjunctum 1.Additionally, the inside portion of bonded layer can be removed using chemical etching
Divide and stratum disjunctum 1 is exposed with part.
The enforcement that bonded layer is made up of high conductivity (n doping, typically N doping or phosphorus doping) SiC wherein
In example, the interior section of bonded layer is not typically removed.In addition, even mask 7 can be removed before plasma etching.This
It is because that the remainder of the SiC protective layer at the outer peripheral areas of carrier wafer 20 may also used as plasma etching
Mask.
Alternately or additionally, remove carrier wafer 20 on the interior section of stratum disjunctum 1 and may include milling
(milling) and/or grinding carrier chip 20 one or more techniques.For example, can be removed except thin using cutting machine
The interior section of the carrier wafer 20 beyond remainder, thin remainder is by being parked in stratum disjunctum 1 and/or at stratum disjunctum 1
Plasma ashing at SiC removes.
Hereafter, any opening of the SiC protective layer on the remainder 20 ' (place of graphite can be exposed) of carrier wafer 20
Can be closed by depositing silicon and thermal procession.
Fig. 1 F illustrates the institute of the inclusion SiC protective layer 25 after stratum disjunctum 1 removes the silicon of any deposition in vertical cross-section
The chip 100 being partially supported through his arms obtaining, this removes can be realized by etching.Fig. 1 G is the remainder illustrating including bonded layer 42
Fig. 1 F of the left part 110 of the chip 100 being partially supported through his arms enlarged drawing.
As explained above, bonded layer 42 can also be SiC.In this embodiment, bonded layer 42 even can cover completely
Lid stratum disjunctum 1.In addition, typically removing bonded layer 42 from stratum disjunctum 1.
Correspondingly, form the chip 100 being partially supported through his arms, it can be entered from the both sides 12,21 of its SiC device chip 1,2
One step is safely processed.In the embodiment explained with regard to Figure 1A to Fig. 1 G, C side 12 is typically formed SiC device chip 1,2
The back side, and the typically polished side 21 of (one or more) single crystal silicon carbide layer 2 is typically formed SiC device chip 1,2
Front.
In the exemplary embodiments, the expose portion of SiC protective layer 25 and remainder 20 ' form the SiC wafer being supported
1,2 supporting construction 20 ', 25.Supporting construction 20 ', 25 are glued to the outer peripheral areas of SiC wafer 1,2.Typically, support knot
Structure 20 ', 25 are glued bonding (by bonding bonding attachment, for example, using the band viscous ceramic of such as adhesive SiC precursor
Molding precursor adheres to) arrive SiC wafer 1,2.
Typically, the remainder 20 ' of the chip 100 being partially supported through his arms when viewed from above is annular.Real at these
Apply the chip 100 in example, being partially supported through his arms to be formed by SiC film, SiC film by annular carrier (also referred to as annular carbon carrier and
Ring-shaped graphite carrier) support.
Process further and may include device process, such as process stratum disjunctum 1, form back-side gold particularly in stratum disjunctum 1
Genusization, forms pn-junction, at (one or many in (one or more) silicon carbide layer 2 or at (one or more) silicon carbide layer 2
Individual) form groove in silicon carbide layer 2, form gate electrode in the trench, grid electricity is formed on (one or more) silicon carbide layer 2
Pole, forms front-side metallization on (one or more) silicon carbide layer 2, and/or the chip being partially supported through his arms 100 is separated into individual
Body semiconductor device.These techniques will be construed as manufacturing the unrestricted of performed typical process for wafer scale device
Property example.
In addition, mentioned device handling process can differently complete, and/or may include some steps.For example, shape
Back face metalization is become to may include deposition, plating, applied metal sintering slurry, annealing and/or polish.
In order to reduce the thermic load of the structure having manufactured at front 21, can be used for forming back-side gold using laser annealing
Genusization.
In being related to the embodiment of manufacture of SiC-MOSFET, back face metalization is typically formed drain metallization.
In being related to the embodiment of manufacture of SiC diode, back face metalization is typically formed cathode metallization.
Before device is processed, the chip 100 being partially supported through his arms can be stored and even be shipped after suitable encapsulation.
In another embodiment, after completing device process at front 21, remove on the interior section of stratum disjunctum 1
Carrier wafer 20.
It is front 21 or the back side completes to can be dependent on the temperature budget of technique first.
Explain the method for forming chip architecture 100 ' and wafer scale SiC semiconductor device respectively about Fig. 2A to Fig. 2 F
Technique, it is similar to the method technique explained above for Figure 1A to Fig. 1 G.However, by high energy particle from Si side 102 note
Enter in SiC donor wafer 10, as illustrating in the Fig. 2A of the vertical cross-section running through donor wafer 10.In addition, SiC
Donor wafer 10 is bonded to carrier wafer 20 with its Si side 102 gluing, as illustrated in Fig. 2 B.Correspondingly, in fig. 2 c
After the smart-cut layer transfer of diagram, the C side 12 of the stratum disjunctum 1 of transfer is accessible (accessible) and the separation shifted
The Si side 11 loaded body chip 20 of layer 1 covers.This process sequence is formed at (one or more) at C side 11 after may result in
The extra high conductivity of MOS channel region.
Hereafter, similar with explain above for Fig. 1 D, (one or more) epitaxial sic layer can be formed on stratum disjunctum 1
2’.The vertical cross-section of the chip architecture obtained by running through shown in Fig. 2 D.
In the exemplary embodiments, the accessible side 21 ' of (one or more) silicon carbide layer 2 ' is typically formed SiC device
Chip 1,2 back side.Correspondingly, (one or more) silicon carbide layer 2 ' can cost-effectively be formed as polycrystalline Si C (poly-
SiC).(one or more) silicon carbide layer 2 ' is typically the highly doped low vertical resistivity to guarantee structure.In addition, can lead
To use (one or more) poly-SiC layer 2 ' for stability reasons.
After epitaxial deposition (one or more) SiC layer 2 ', dopant can be injected into (one or more) polycrystalline or list
Brilliant SiC layer 2 '.In addition, executable rear implantation annealing for example at 1700 DEG C.
Hereafter, by removing the crystalline substance that carrier wafer 20 formation is partially supported through his arms on the interior section of stratum disjunctum 1 completely
Piece 100 '.
Technique for forming the chip 100 ' being partially supported through his arms of diagram in Fig. 2 E and Fig. 2 F is typically similar to above
The technique explained with regard to Fig. 1 E and 1F.However, in Fig. 2 E, removing bonded layer from the Si side 11 exposing completely.This is because
It is used as the front of SiC wafer 1,2 ' after Si side 11.
Hereafter, the chip 100 ' being partially supported through his arms can be processed further.This may include such as in (one or more) extension
The upper device forming back face metalization of SiC layer 2 ' is processed, and processes stratum disjunctum 1 further and by the chip being partially supported through his arms 100
It is separated into individual semiconductor device.Process stratum disjunctum 1 further may include：Form pn at stratum disjunctum 1 or in stratum disjunctum 1
Knot；Form groove in stratum disjunctum 1；Form gate electrode in the trench；Gate electrode is formed on stratum disjunctum 1；And/or in stratum disjunctum
Form front-side metallization on 1.Furthermore, these techniques will be construed as manufacturing performed typical work for wafer scale device
The non-limiting example of skill.
Also can be described as above for the method that Figure 1A to 2F is explained：
From donor wafer 10 shift silicon carbide layer 1 to include graphite carrier wafer 20, and part remove carrier wafer 20 with
Formation supporting construction 20 ' at silicon carbide layer 1,25, so that supporting construction 20 ', 25 only partly cover silicon carbide layer 1.
Do so, the chip 100,100 ' that chip architecture is particularly partially supported through his arms can be formed with to carry and be less than
100 μm, the relatively thin silicon carbide layer 1 (and optional epitaxial layer 2,2 ') less than 75 μm or even less than 50 μm of thickness, its
Can due to supporting construction 20 ', 25 and safely processed further from both sides.This allows the flexible and efficient wafer scale of cost
SiC device manufactures.
Typically, silicon carbide layer 1 is transferred as stratum disjunctum 1.This may include and adheres to the donor wafer 10 including carborundum
Separate donor wafer 10 to carrier wafer 20 and along internal peel ply 13.
Fig. 3 A to Fig. 3 D illustrates the further work for forming chip architecture 200 and wafer level semiconductor device respectively
Skill.After forming structure as shown in Figure 2 D, (for example, cheap (poly-) Si chip or glass are brilliant for temporary carrier chip 30
Piece) it is glued and be bonded to (one or more) silicon carbide layer 2 '.Fig. 3 A diagram runs through the vertical cross-section of obtained chip architecture.
Hereafter, carrier wafer 20 can be removed completely by following：For example pass through to grind, ashing (in oxygen atmosphere plasma
Body etches), form putting down of the bonded layer at the Si side 11 of the stratum disjunctum 1 in front of chip architecture after being followed by also removing completely
Smoothization.Fig. 3 B illustrates the vertical cross-section of the chip architecture obtained by running through.
Hereafter, supporting construction 40 can be formed at stratum disjunctum 1, the glass structure of such as substantially annular.Supporting construction 40
Can be directly glued or gluing is bonded to stratum disjunctum 1 in the outer part office of Si side 11.Alternatively, chip is supported to may be affixed to point
Absciss layer 1 and being removed with the interior section of rear support chip leaves the residue of the support chip 40 being attached to Si side 11 simultaneously
Part 40.Fig. 3 C diagram runs through the vertical cross-section of obtained chip architecture.
In one embodiment, it is used for adhering to supporting construction 40 using the bonding of glass glue.For example, business can be used
The silicate adhesive of (for example, from Dow Corning) can be obtained on industry.Depending on the characteristic of glass glue, bonding is even
Connect and can stand the up to 250 DEG C temperature to 300 DEG C or even as high as 450 DEG C in an inert atmosphere at short notice.This for
Semiconductor wafer is enough for completing many manufacturing process that semiconductor device is stood.
Depending on the material of supporting construction 40, can be using any suitable bonding technology for attachment to stratum disjunctum.Example
Be be bonded with and without the anode linkage of the diamond like carbon layer (DLC) in stratum disjunctum 1, glass medium, melting bonding and
Bonding using glass glue.
Hereafter, temporary carrier chip 30 can be removed again.The chip 200 being partially supported through his arms obtained by illustrating in Fig. 3 D.
Hereafter, similar with explain above for Fig. 2 F, the chip 200 being partially supported through his arms can be processed further.
Fig. 4 A to Fig. 4 E illustrates the further technique for forming chip architecture 200 ' and wafer level semiconductor device.In shape
After becoming structure as shown in figure ip, temporary carrier chip 30 (for example cheap poly-Si chip or chip glass) is glued key
Close (one or more) silicon carbide layer 2.Fig. 4 A diagram runs through the vertical cross-section of obtained chip architecture.
Hereafter, carrier wafer 20 can be removed completely by following：For example pass through to grind, ashing (under oxygen atmosphere plasma
Body etches), and the planarization also removing stratum disjunctum 1 completely.Fig. 4 B diagram runs through the vertical cross-section of obtained chip architecture.
Hereafter, supporting construction 40 can be formed at the exposed side 22 of (one or more) silicon carbide layer 2, for example substantially ring
The glass structure of shape.This can be accomplished analogously with explaining above for Fig. 3 C.Fig. 4 C diagram runs through obtained chip architecture
Vertical cross-section.
Hereafter, temporary carrier chip 30 can be removed again.The chip 200 ' being partially supported through his arms obtained by illustrating in Fig. 4 D.
Fig. 4 E is the amplification of Fig. 4 D of the left part 210 of the chip 200 ' being partially supported through his arms illustrating the remainder including bonded layer 42
Figure.
Hereafter, the chip 200 ' being partially supported through his arms can be processed further to manufacture using the chip 200 ' being partially supported through his arms
If dry units.
Also can be described for forming chip architecture particularly by part above for the method that Figure 1A to 4E explains
The method of the chip of support, has steps of：
- shift silicon carbide layer 1 to the graphite including chip 20 from donor wafer 10；And
- the graphite that removes on the interior section of silicon carbide layer 1 including chip 20 is only partly covered with being formed at silicon carbide layer 1
The supporting construction 20 ' of lid silicon carbide layer 1,25；Or
Remove the graphite including chip 20 after the-supporting construction 40 of the graphite with respect to inclusion chip 20 in formation, support knot
Structure 40 only part covers silicon carbide layer 1 and/or the other silicon carbide layer 2,2 ' depositing on silicon carbide layer 1.
Correspondingly, chip architecture can be formed, it has SiC wafer, SiC wafer in the outer peripheral areas of this SiC wafer by
Supporting construction 40,20 ', 25 supports.Depending on process sequence and/or other optional step, SiC wafer can be by silicon carbide layer 1
And/or other silicon carbide layer 2,2 ' is formed.
Due to supporting construction 40,20 ', 25, SiC wafer for processing further (such as by outer peripheral areas around core
Device in panel region is processed) be enough mechanically stables, even if SiC wafer relative thin, e.g., less than 100 μm, less than 75 μm,
Or even less than 50 μ m-thick.Notice the amount forming the monocrystal SiC that the membranaceous SiC wafer being supported decreases costliness.In addition, carbon
SiClx chip can reach for processing further from both sides.Even further, caused due to the thermal characteristicss mismatch of SiC and graphite
Heat problem during manufacture can be reduced by least partly removing including the graphite of chip.This allows flexible and high cost
The manufacture of the wafer scale SiC device (SiC chip) of effect, particularly has the power SiC device example of the up to blocking voltage of 6.5kV
Manufacture as power SiC crystal pipe.However, SiC wafer also can have bigger thickness, for example, at least 120 μm or even more high
Thickness, for manufacturing, there is the SiC device of even more high blocking voltage.
The top view of Fig. 5 A chip 100,100 ', 200 being partially supported through his arms of pictorial image 1F, Fig. 2 F and Fig. 3 D respectively, its
Can be corresponding to the section along the line 8 in Fig. 5 A.
In the exemplary embodiments, the chip 100 being partially supported through his arms is formed by respective silicon carbide wafer 1,100 ', 200, its by
Each supporting construction 20 ' of continuous circular shape, 25,40 supports, supporting construction 20 ', 25,40 include polysilicon or glass (40), or
Person includes carborundum (25) and graphite (is hidden by protection SiC layer 25, this is also applied for may be formed at silicon carbide wafer in fig. 5
Stratum disjunctum 1 at epitaxial layer).Supporting construction 25,40 are glued in the outer peripheral areas of silicon carbide wafer 1, this outer peripheral areas
The accessible device area not covered by supporting construction 25,40 around silicon carbide wafer 1.
Typically, at most the 50% of silicon carbide wafer 1, more typically at most 80% or even 90% by supporting construction 25,
40 coverings.
For example, supporting construction 40,25 can only cover the outer peripheral areas of annular, and it has at least about 1mm and typically arrives
The width of 10mm, simultaneously horizontal-extending (wafer size) of silicon carbide wafer 1 may be up to 100mm, 200mm or even 300mm.
Extend vertically (thickness) of silicon carbide wafer 1 is smaller than 100 μm, is less than 80 μm or 60 μm or even less than 50 μm.
In other embodiments, the supporting construction shown in Fig. 5 A is glued and is bonded to epitaxial layer (2, Fig. 5 A are not shown).
The top view of Fig. 5 B chip 100,100 ', 200 being partially supported through his arms of pictorial image 1F, Fig. 2 F and Fig. 3 D respectively, its
Can be corresponding to the section along the line 8 in Fig. 5 B.
Supporting construction is similar with explain above for Fig. 5 A, but is spaced apart in couples each other by by respective path
Four rings-section shape 25a, 40a, 25b, 40b, 25c, 40c, 25d, 40d of demonstration constitute.Although path, by part
The chip supporting also can process sufficiently stable for later device.Path can promote the later rotation using during device manufactures
Apply technique (improving the discharge of excess material).
In other embodiments, the supporting construction shown in Fig. 5 B is glued and is bonded to epitaxial layer (not shown in 2, Fig. 5 B).
Fig. 5 C diagram run through the chip 100 being partially supported through his arms " vertical cross-section.The chip 100 being partially supported through his arms " similar to
The chip 100 ' being partially supported through his arms explained above for Fig. 1 F, 5A, 5B.However, the chip 100 being partially supported through his arms " have and prop up
Support structure 20 ', 25, it is stepped in vertical cross-section.This is attributable to manufacture and may additionally facilitate spin coating proceeding.
Fig. 5 D diagram run through the chip 100 being partially supported through his arms " ' vertical cross-section.The chip 100 being partially supported through his arms " ' it is similar to
In the chip 100 being partially supported through his arms explained above for Fig. 5 C ".However, the chip 100 being partially supported through his arms " ' there is chip knot
Structure, it is shaped to improve further the row of the excess material of spin coating proceeding application using during being manufactured by device afterwards
Go out.
While there has been disclosed that the various example embodiments of the present invention, but will be apparent to those skilled in the art
It is to make various changes and modifications, it is by some advantages realizing the present invention without departing from the spirit and scope of the present invention.Right
This area suitable those skilled in the art will be obvious that, the miscellaneous part of execution identical function can suitably be substituted.Should
Refer to, can be with the combinations of features of other figures, even if this is not explicitly mentioned wherein with reference to the feature that specific pattern is explained
In the case of those.
The relative term in space such as " ... under ", " below ", D score, " ... on ", " on " etc. be used for letter
Change description to explain the positioning that an element is with respect to second element.These terms are intended to the different orientation of device, remove
Outside the orientations different from those orientations described in figure.In addition, term such as " first ", " second " etc. are also used to
Describe various elements, area, section etc., and be also not intended to be restricted.Run through description, same unit specified in same term
Part.
As used in this article, term " having ", " containing ", "comprising", " inclusion " etc. be opening term, its
Indicate the element of statement or the presence of feature but be not excluded for additional element or feature.Article " one ", " one " and " being somebody's turn to do " meaning
Comprising plural number and odd number, unless the context clearly dictates otherwise.
In view of above change and application scope it should be understood that the present invention is not limited by the foregoing description is limited, also not
By accompanying drawing, institute is limited.Alternatively, the present invention is only limited by appended claim and its legal equivalents.
Claims (20)
1. a kind of method for forming semiconductor device, including：
- donor wafer (10) including carborundum is attached to the carrier wafer (20) including graphite；
- separate donor wafer (10) so that formation includes carborundum and is attached to carrier wafer along internal peel ply (13)
(20) stratum disjunctum (1)；
- form the chip (100,200) being partially supported through his arms, remove carrier wafer including on the interior section of stratum disjunctum (1)
(20), leave the remainder (20 ') of the carrier wafer (20) being attached to stratum disjunctum (1) simultaneously；And
- process the chip (100,200) being partially supported through his arms further.
2. the method for claim 1 wherein that attachment donor wafer includes at least one of the following：
- ceramic forming polymer precursor is deposited on the bonding surface (101,102) of donor wafer；
- in carrier wafer (20) upper deposition ceramic forming polymer precursor；
- forming the stacking (50) including carrier wafer (20), donor wafer (10) and bonded layer (42), bonded layer (42) includes pottery
Porcelain forming polymer precursor, and be arranged between carrier wafer (20) and the bonding surface (101,102) of donor wafer (10)；
And
- tempering stacking (50) at a temperature of between 200 DEG C to 700 DEG C.
3. the method for claim 2, wherein ceramic forming polymer precursor includes Polycarbosilane.
4. the method for Claims 2 or 3, wherein tempering occur in the atmosphere including nitrogen, argon and/or hydrogen.
5. the method for aforementioned any claim, at least partly remove also include before carrier wafer (20) following at least
One：
- in the other silicon carbide layer (2) of the upper deposition of stratum disjunctum (1)；
- injection dopant is in stratum disjunctum (1) and/or in other silicon carbide layer (2)；And
- thermal annealing.
6. the method for aforementioned any claim, wherein supporting construction (20,25) are formed to cover the external zones of stratum disjunctum (1)
The ring in domain.
7. the method for aforementioned any claim, wherein removes carrier wafer (20) and includes at least one of the following：
The interior section of-milling carrier wafer (20)；
The interior section of-grinding carrier chip (20)；
The mask etching of-carrier wafer (20)；
The interior section of-exposure stratum disjunctum (1)；
- silicon carbide layer (25) inclusion deposition silicon and thermal procession are formed on the remainder (20 ') of carrier wafer；And
- silicon of deposition is removed from stratum disjunctum (1).
8. the method for aforementioned any claim, also includes injecting high energy particle in donor wafer (10) with attachment alms giver
Form peel ply (13) before chip (10).
9. the method for aforementioned any claim, wherein processes chip (100, the 200) inclusion being partially supported through his arms following further
At least one of：
- process stratum disjunctum (1)；
- form pn-junction in stratum disjunctum (1)；
- in the upper depositing silicon carbide layers (2,2 ') of stratum disjunctum (1)；
- metallize in upper formation of stratum disjunctum (1)；
- form other pn-junction in silicon carbide layer (2,2 ')；
- in the other metallization of the upper formation of silicon carbide layer (2,2 ')；And
- chip being partially supported through his arms (100,200) is separated into individual semiconductor device.
10. one kind is used for the method forming chip architecture (100,200), including：
- silicon carbide wafer (10) with the first side (101,102) is provided；
- inject high energy particle to silicon carbide wafer (10) from the first side；
First side of-bonded silicon carbide chip (10) is to the carrier wafer (20) including graphite；
Separate ground floor (1) from silicon carbide wafer (10)；One of and following：
- remove carrier wafer (20) on the interior section of ground floor (1) and cover the to form only part at ground floor (1) place
The supporting construction (20 ', 25) of one layer (1)；With
- in the upper depositing silicon carbide layers (2,2 ') of stratum disjunctum (1) and be formed at silicon carbide layer (2,2 ') place and only part covers carbon
Carrier wafer (20) is removed after the supporting construction (40) of SiClx layer (2,2 ').
The method of 11. claim 10, is wherein bonded the first side and includes at least one of the following：
- coat ground floor (1) with ceramic forming polymer precursor；
- with the bonding surface of ceramic forming polymer precursor coated carrier chip (20)；
- forming the stacking including carrier wafer (20), silicon carbide wafer (10) and bonded layer (42), bonded layer (42) includes pottery
Forming polymer precursor and being arranged between carrier wafer (20) and silicon carbide wafer (10)；And
- it is tempered stacking at a temperature of between 200 DEG C to 700 DEG C.
The method of 12. claim 10 or 11, wherein forms supporting construction (40) and includes at least one of the following：
- adhere to temporary carrier chip (30) before removing carrier wafer (20) to silicon carbide layer (2,2 ')；
- attachment supports chip (40) to ground floor (1) and removes on the interior section of ground floor (1) and supports chip (40) same
When leave the remainder (40) of the support chip (40) being attached to stratum disjunctum (1)；
Ground floor (1) is arrived in-attachment supporting construction (40)；
- remove temporary carrier chip (30) after ground floor (1) place forms supporting construction (20 ', 25)；
- remove ground floor (1) after removing carrier wafer (20)；
Silicon carbide layer (2,2 ') is arrived in-attachment supporting construction (40)；
- attachment supporting construction (40) is arrived silicon carbide layer (2,2 ') and is removed support on the interior section of silicon carbide layer (2,2 ')
Structure (40) leaves the remainder (40) of the support chip (40) being attached to silicon carbide layer (2,2 ') simultaneously；And
- remove temporary carrier chip (30) after silicon carbide layer (2,2 ') place forms supporting construction (40).
The method of 13. claim 12, wherein attachment temporary carrier chip (30), attachment supports chip (40) to arrive ground floor (1),
Ground floor (1) is arrived in attachment supporting construction (40), and silicon carbide layer (2,2 ') is arrived in attachment supporting construction (40) and/or attachment supports chip
(40) arrive silicon carbide layer (2,2 ') to include glued and/or realize by respective adhesion layer.
The method of any one in 14. claim 10 to 13, wherein forms supporting construction at silicon carbide layer (2,2 ') place
(40) remove carrier wafer (20) after and include at least one of the following：
- polishing；With
- ashing.
The method of 15. claim 10 or 11, wherein internally removes on part in below carrier wafer (20) inclusion extremely
Few one：
- in carrier wafer (20) upper formation mask (7)；
- use mask (7) chemical etching carrier wafer (20)；
- use mask (7) ion beam etching carrier wafer (20)；
- use mask (7) plasma etching carrier wafer (20)；And
- machinery removes at least part of of carrier wafer (20).
A kind of 16. chip architectures (100,200), including：
- silicon carbide wafer (1,2)；With
- supporting construction (20 ', 25,40), including at least one of silicon, carborundum, graphite and glass, wherein when viewed from above
When, supporting construction (20 ', 25,40) is glued at the silicon carbide wafer (1,2) of the device area around silicon carbide wafer (1,2)
In outer peripheral areas, and wherein supporting construction (20 ', 25,40) only part covers silicon carbide wafer (1,2).
The chip architecture of 17. claim 16, wherein when viewed from above, supporting construction (20 ', 25,40) is annular or base
It is annular in basis, and/or wherein supporting construction (20 ', 25,40) only covers the major part of outer peripheral areas or outer peripheral areas.
The chip architecture of 18. claim 16 or 17, the wherein thickness of silicon carbide wafer (1,2) are less than 100 μm, and/or wherein
Silicon carbide wafer (1,2) inclusion monocrystalline stratum disjunctum (1), the single crystal epitaxial SiC layer (2) being formed at monocrystalline stratum disjunctum (1) place and shape
At least one of one-tenth on-monocrystalline epitaxial sic layer (2) at monocrystalline stratum disjunctum (1) and/or single crystal epitaxial SiC layer (2) place.
The chip architecture of any one in 19. claim 16 to 18, wherein supporting construction (20 ', 25,40) cover carborundum
At most the 50% of chip (1,2) and/or wherein supporting construction (20 ', 25,40) at least substantially cover outer peripheral areas, external zones
Domain is limited by the loop configuration with least width of 1mm.
The chip architecture of any one in 20. claim 16 to 19, wherein supporting construction (20 ', 25) include graphite body
(20 '), wherein supporting construction (20 ', 25) are glued in epi region using ceramic forming polymer precursor, and/or wherein carbon
Bonded layer (42) between SiClx chip (1,2) and supporting construction (20 ', 25) is n doping.
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| DE102015112648.6 | 2015-07-31 | ||
| DE102015112648.6A DE102015112648B4 (en) | 2015-07-31 | 2015-07-31 | METHOD OF FORMING A WAFER STRUCTURE, METHOD OF FORMING A SEMICONDUCTOR COMPONENT AND A WAFER STRUCTURE |
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| CN110435022A (en) * | 2018-05-04 | 2019-11-12 | 英飞凌科技股份有限公司 | SiC material is sliced by wire electrodischarge processing |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200321242A1 (en) * | 2015-09-18 | 2020-10-08 | Bing Hu | Method of separating a film from a brittle material |
| US10319599B2 (en) * | 2017-05-31 | 2019-06-11 | Infineon Technologies Ag | Methods of planarizing SiC surfaces |
| KR102434021B1 (en) | 2017-11-13 | 2022-08-24 | 삼성전자주식회사 | Method of debonding a carrier substrate from a device substrate, apparatus for performing the same, and method of singulating semiconductor chips including the same |
| US10643860B2 (en) | 2018-03-26 | 2020-05-05 | Infineon Technologies Ag | Methods of thinning and structuring semiconductor wafers by electrical discharge machining |
| DE102018132447B4 (en) | 2018-12-17 | 2022-10-13 | Infineon Technologies Ag | Semiconductor device and method of manufacturing a semiconductor device |
| FR3102608B1 (en) * | 2019-10-28 | 2021-09-24 | Commissariat Energie Atomique | A thin film transfer process using a charged preceramic polymer |
| DE102020206233B3 (en) * | 2020-05-18 | 2021-08-12 | Disco Corporation | METHOD FOR MANUFACTURING A SUBSTRATE AND SYSTEM FOR MANUFACTURING A SUBSTRATE |
| TWI745001B (en) * | 2020-07-24 | 2021-11-01 | 環球晶圓股份有限公司 | Bonding wafer structure and method of manufacturing the same |
| CN113178383A (en) * | 2021-03-10 | 2021-07-27 | 华为技术有限公司 | Silicon carbide substrate, silicon carbide device and substrate thinning method thereof |
| TW202425078A (en) | 2022-08-31 | 2024-06-16 | 比利時商烏明克公司 | Compound semiconductor layered structure and processes for preparing a compound semiconductor layered structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003282845A (en) * | 2002-03-20 | 2003-10-03 | Mitsubishi Electric Corp | Fabricating method of silicon carbide substrate, schottky barrier diode and silicon carbide film and silicon carbide substrate fabricated with this method |
| WO2004001819A1 (en) * | 2002-06-25 | 2003-12-31 | Sanken Electric Co., Ltd. | Semiconductor device manufacturing method and ring-shaped reinforcing member |
| CN102804334A (en) * | 2009-06-04 | 2012-11-28 | 三美电机株式会社 | Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and method for manufacturing semiconductor device |
| CN104716080A (en) * | 2013-12-13 | 2015-06-17 | 英飞凌科技股份有限公司 | Compound structure and method for forming a compound structure |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10223496A (en) | 1997-02-12 | 1998-08-21 | Ion Kogaku Kenkyusho:Kk | Single-crystal wafer and manufacture thereof |
| US8404562B2 (en) * | 2010-09-30 | 2013-03-26 | Infineon Technologies Ag | Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core |
| JP2012142385A (en) | 2010-12-28 | 2012-07-26 | Sumitomo Electric Ind Ltd | Semiconductor device manufacturing method |
| JP2013124196A (en) | 2011-12-14 | 2013-06-24 | Sumitomo Electric Ind Ltd | Method for inspecting adhesion state of seed crystal |
| FR2995136B1 (en) * | 2012-09-04 | 2015-06-26 | Soitec Silicon On Insulator | PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USE OF MONOCRYSTALLINE MATERIAL |
| US9349804B2 (en) | 2013-02-12 | 2016-05-24 | Infineon Technologies Ag | Composite wafer for bonding and encapsulating an SiC-based functional layer |
| US11721547B2 (en) * | 2013-03-14 | 2023-08-08 | Infineon Technologies Ag | Method for manufacturing a silicon carbide substrate for an electrical silicon carbide device, a silicon carbide substrate and an electrical silicon carbide device |
-
2015
- 2015-07-31 DE DE102015112648.6A patent/DE102015112648B4/en active Active
-
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- 2016-07-29 CN CN201610824797.6A patent/CN106409669B/en active Active
- 2016-07-29 US US15/224,076 patent/US9793167B2/en active Active
- 2016-07-29 JP JP2016149957A patent/JP2017034254A/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003282845A (en) * | 2002-03-20 | 2003-10-03 | Mitsubishi Electric Corp | Fabricating method of silicon carbide substrate, schottky barrier diode and silicon carbide film and silicon carbide substrate fabricated with this method |
| WO2004001819A1 (en) * | 2002-06-25 | 2003-12-31 | Sanken Electric Co., Ltd. | Semiconductor device manufacturing method and ring-shaped reinforcing member |
| CN102804334A (en) * | 2009-06-04 | 2012-11-28 | 三美电机株式会社 | Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and method for manufacturing semiconductor device |
| CN104716080A (en) * | 2013-12-13 | 2015-06-17 | 英飞凌科技股份有限公司 | Compound structure and method for forming a compound structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110435022A (en) * | 2018-05-04 | 2019-11-12 | 英飞凌科技股份有限公司 | SiC material is sliced by wire electrodischarge processing |
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| CN106409669B (en) | 2020-06-30 |
| DE102015112648A1 (en) | 2017-02-02 |
| US9793167B2 (en) | 2017-10-17 |
| JP2017034254A (en) | 2017-02-09 |
| DE102015112648B4 (en) | 2021-02-04 |
| US20170033010A1 (en) | 2017-02-02 |
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