CN106407138A - LVDS (Low Voltage Differential Signaling) interface and DSI (Display Serial Interface) multiplexing circuit - Google Patents
LVDS (Low Voltage Differential Signaling) interface and DSI (Display Serial Interface) multiplexing circuit Download PDFInfo
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- CN106407138A CN106407138A CN201510466134.7A CN201510466134A CN106407138A CN 106407138 A CN106407138 A CN 106407138A CN 201510466134 A CN201510466134 A CN 201510466134A CN 106407138 A CN106407138 A CN 106407138A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
Abstract
The invention discloses a LVDS (Low Voltage Differential Signaling) interface and DSI (Display Serial Interface) multiplexing circuit, and is used for solving the problem of interface resource waste caused in a way that the LVDS interface and the DSI can not be multiplexed. The circuit comprises a data clock selection circuit, a data clock synchronization circuit, a mode control circuit, a data conversion circuit and a driving circuit, wherein the data clock selection circuit selects a current interface mode, receives a data signal and a clock signal input from outside, and provides the data signal and the clock signal to the data clock synchronization circuit; the data clock synchronization circuit carries out synchronization on the data signal and the clock signal, provided the synchronized data signal and clock signal for the data conversion circuit; the data conversion circuit converts the synchronized data signal to be serial from parallel, and outputs a differential data signal to the driving circuit; and the driving circuit utilizes the differential data signal to control the range of the output signal so as to realize the multiplexing of the LVDS interface and the DSI and reduce resource waste.
Description
Technical field
The present invention relates to display interface field, the side of more particularly, to a kind of LVDS interface and DSI interface duplex
Method and circuit.
Background technology
Low Voltage Differential Signal (Low Voltage Differential Signaling, LVDS) transmission is as a kind of
Ripe signal transmission technology, is widely used in display interface field, especially LCDs.But with
The fast development of mobile terminal, proposes requirements at the higher level to the bandwidth of display interface.Therefore (Mobile
Industry Processor Interface, MIPI) alliance propose display serial (Display Serial
Interface, DSI) interface specification, to meet the demand of higher resolution display screen.Consumer for movement
For electric terminal, in order to meet the wider market demand, two kinds of display interface technology all can occur in shifting
In dynamic processor interface, to meet different customer demands, and client then only can select according to actual scheme
Using a kind of interface therein.
Fig. 1 is the LVDS interface and DSI interface exemplary implementations in mobile processor.This method
There are disadvantages that：First, area is larger, and the interface circuit of LVDS and DSI is separate, needs each
From circuit module to realize；Secondly, power consumption is larger, and two circuit are respectively necessary for individually powering；3rd,
Packaging cost is larger, LVDS and DSI module is independent, needs individually to go out pin (pin), LVDS in encapsulation
It is usually constructed with 5 passages (lane) with DSI, this is accomplished by encapsulating out 10 pin respectively, and actual
In application, only one of which can be selected according to development plan, this inevitably results in the resource wasting 10 pin.
It follows that due to independent mutually when LVDS interface of the prior art and DSI Interface design, that is,
Both are not multiplexed, then will necessarily waste certain interface resource, increase the cost of mobile processor.
Content of the invention
It is an object of the invention to provide a kind of LVDS interface and DSI interface multiplexing circuit, with solve due to
The interface resource that LVDS interface and DSI interface can not be multiplexed and lead to wastes problem.
The purpose of the present invention is achieved through the following technical solutions：
A kind of Low Voltage Differential Signal LVDS interface and display difference DSI interface multiplexing circuit, including：Data
Clock selection circuit, data clock synchronous circuit, mode control circuit, data converting circuit and drive circuit；
Wherein,
Described data clock selection circuit, with described mode control circuit and described data clock synchronous circuit phase
Connect, for selecting current interface modes under the Schema control of described mode control circuit, receive outside
The data signal of input and clock signal be supplied to described data clock synchronous circuit；
Described data clock synchronous circuit, is connected with described mode control circuit and described data converting circuit
It is connected, for entering to described data signal and clock signal under the Schema control of described mode control circuit
Row is synchronous, and the data signal after synchronization and clock signal are supplied to described data converting circuit；
Described data converting circuit, is connected with described mode control circuit and described drive circuit, for
Under the Schema control of described mode control circuit by the data signal after synchronization from Parallel transformation be serial, and defeated
Go out differential data signals to described drive circuit；
Described drive circuit, is connected with described mode control circuit, in described mode control circuit
Described differential data signals are utilized to control amplitude range and the common mode range of output signal under Schema control.
So, both achieved the multiplexing of LVDS interface and DSI interface additionally it is possible to reduce the number of packaging pin
Mesh, reduces packaging cost, thus reduce interface resource wasting.
Optionally, described drive circuit includes the first circuit, impedance control circuit, first switch group and second
Circuit；
Described first circuit, is connected with described mode control circuit and described first switch group, in institute
State the electric current exporting corresponding modes under the Schema control of mode control circuit to described first switch group；
Described first switch group, is connected with described data converting circuit, in described differential data signals
Control and lower receive the electric current of described first circuit output and export to described second circuit；
Described second circuit, is connected with described first switch group and described impedance control circuit, for receiving
The electric current of described first circuit output, shunts to described electric current under the control of described impedance control circuit
To export corresponding differential signal.
Optionally, described second circuit includes the first variable resistance, the second adjustable resistance and first resistor, institute
State first switch group and include first switch and second switch；
The first end of described first resistor is connected with the described first variable-resistance first end, described first switch
As the negative output terminal of described differential signal, the second end of described first resistor and described the second adjustable resistance
First end, described second switch connect the positive output end as described differential signal, described first variable resistance
The second end and described the second adjustable resistance the second end all with source electrode ground power supply be connected；
Threeth end variable-resistance with described first and described second can power transformation respectively for described impedance control circuit
The three-terminal link of resistance, for controlling the resistance size of described first variable resistance and described the second adjustable resistance
Second circuit is made to export corresponding differential signal.
Optionally, this LVDS interface and DSI interface multiplexing circuit further include：
The negative output of the differential data signals that the grid of described first switch is exported with described data converting circuit
End connects, and the source electrode of described first switch is connected with the outfan of described first circuit, described first switch
Drain electrode be connected with the first end of described first resistor, the grid of described second switch and described data conversion electricity
Positive output end connection, the source electrode of described second switch and described first circuit of the differential data signals of road output
Outfan connect, the drain electrode of described second switch is connected with the second end of described first resistor；
The differential data signals that described first switch and described second switch export in described data converting circuit
Control under open.
Wherein, described first switch and described second switch are P-type transistor.
Optionally, this LVDS interface and DSI interface multiplexing circuit further include：
The positive output of the differential data signals that the grid of described first switch is exported with described data converting circuit
End connects, and the source electrode of described first switch is connected with the outfan of described first circuit, described first switch
Drain electrode is connected with the first end of described first resistor, the grid of described second switch and described data converting circuit
The negative output terminal connection of the differential data signals of output, the source electrode of described second switch and described first circuit
Outfan connects, and the drain electrode of described second switch is connected with the second end of described first resistor；
The differential data signals that described first switch and described second switch export in described data converting circuit
Control under open；
Wherein, described first switch and described second switch are N-type transistor.
Optionally, described first variable resistance includes second resistance and the first N-type transistor, and described second
Variable resistance includes 3rd resistor and the second N-type transistor, wherein said second resistance and described 3rd resistor
Resistance size identical and be more than 0, the first end of the first end of described second resistance and described first resistor is even
Connect, the source electrode of described first N-type transistor is connected with the second end of described second resistance, described 3rd electricity
The first end of resistance is connected with the second end of described first resistor, the source electrode of described second N-type transistor and institute
The second end stating 3rd resistor connects, the leakage of described first N-type transistor and described second N-type transistor
Extremely all it is connected with source electrode ground power supply, the grid of described first N-type transistor and described second N-type transistor
All it is connected with described impedance control circuit；
Described impedance control circuit includes common mode feedback unit and operational amplifier, described common mode feedback unit
Positive input terminal is connected with the second end of described first resistor, the negative input end of described common mode feedback unit with described
The first end of first resistor connects, and the outfan of described common mode feedback unit is just defeated with described operational amplifier
Enter end to connect, the input of the negative input end of described operational amplifier for the reference voltage under different mode, described
The outfan of operational amplifier is connected with the grid of the first N-type transistor grid and the second N-type transistor respectively
Connect, described reference voltage is the common-mode voltage of the standard difference signal of different mode lower interface circuit output；
The differential signal that described common mode feedback unit and described operational amplifier export to described second circuit enters
Row clamper, and export bias voltage described first N-type transistor and described second N-type transistor are carried out
Biasing, to control the resistance size of described first variable resistance and described the second adjustable resistance, makes second circuit
Export corresponding differential signal.
Optionally, described first variable resistance is the 3rd N-type transistor, and described the second adjustable resistance is the
Four N-type transistor, the source electrode of described 4th N-type transistor is connected with the first end of described first resistor
Connect, the source electrode of described second N-type transistor is connected with the second end of described first resistor, described first N-type
The drain electrode of transistor and described second N-type transistor is all connected with source electrode ground power supply, and described first N-type is brilliant
The grid of body pipe and described second N-type transistor is all connected with described impedance control circuit；
Described impedance control circuit includes common mode feedback unit and operational amplifier, described common mode feedback unit
Positive input terminal is connected with the second end of described first resistor, the negative input end of described common mode feedback unit with described
The first end of first resistor connects, and the outfan of described common mode feedback unit is just defeated with described operational amplifier
Enter end to connect, the input of the negative input end of described operational amplifier for the reference voltage under different mode, described
The outfan of operational amplifier is connected with the grid of the first N-type transistor grid and the second N-type transistor respectively
Connect, described reference voltage is the common-mode voltage of the standard difference signal of different mode lower interface circuit output；
The differential signal that described common mode feedback unit and described operational amplifier export to described second circuit enters
Row clamper, and export bias voltage described first N-type transistor and described second N-type transistor are carried out
Biasing, to control the resistance size of described first variable resistance and described the second adjustable resistance, makes second circuit
Export corresponding differential signal.
Optionally, described impedance control circuit include calibrate current source, calibrate variable resistance, comparator, plus
Subtract device and controller calibration,
Described calibration current source, for producing calibration electric current, and exports to calibration variable resistance；
The positive input terminal of described comparator and the described outfan calibrating current source, calibration variable-resistance first
End connects, the input of the negative input end of described comparator for the calibration voltage under different mode, for input
Magnitude of voltage carry out size and compare, and export comparative result to described adder substracter, described calibration voltage is difference
Pattern index will definitely variable resistive value and the product calibrating current value；
The input of described adder substracter is connected with the outfan of described comparator, for the comparison knot according to input
Fruit produces corresponding plus-minus and instructs and export to described controller calibration；
The input of described controller calibration is connected with the outfan of adder substracter, the output of described controller calibration
End with described calibrate variable-resistance 3rd end, the first variable-resistance 3rd end, the second adjustable resistance the
Three-terminal link, for according to input plus-minus instruction control described calibration variable resistance, the first variable resistance and
The resistance size of described the second adjustable resistance makes second circuit export corresponding differential signal, wherein said standard
Variable-resistance second end is connected with source electrode ground power supply.
Optionally, described calibration variable resistance is that M cell resistance is in parallel, and described cell resistance is to set
The NMOS tube of resistance, M is to set positive integer.
Brief description
Fig. 1 is the existing LVDS interface and DSI interface schematic diagram in mobile processor；
Fig. 2 is the access diagram of existing DSI and LVDS；
Fig. 3 A is the typical structure schematic diagram of LVDS interface drive circuit；
Fig. 3 B is the typical structure schematic diagram of DSI interface driving circuit；
Fig. 4 is LVDS interface and DSI interface multiplexing circuit structural representation in the embodiment of the present invention；
Fig. 5 is the principle of drive circuit in LVDS interface in the embodiment of the present invention and DSI interface multiplexing circuit
Schematic diagram；
Fig. 6 is drive circuit in a kind of LVDS interface in the embodiment of the present invention and DSI interface multiplexing circuit
Specific example figure；
Fig. 7 A is a kind of connection diagram of first switch in Fig. 5；
Fig. 7 B is a kind of connection diagram of second switch in Fig. 5；
Fig. 8 is variable-resistance a kind of schematic diagram in Fig. 5；
Fig. 9 is drive circuit in LVDS interface another kind of in the embodiment of the present invention and DSI interface multiplexing circuit
Specific example figure.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, be fully described by it is clear that described embodiment is only a part of embodiment of the present invention, be not
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creation
Property work under the premise of the every other embodiment that obtained, broadly fall into the scope of protection of the invention.
For the passage of DSI and LVDS, generally all can be realized using the structure shown in Fig. 2.Mainly
It is data processing circuit and drive circuit including two modules, wherein：
That data processing circuit mainly realizes input data and turn string manipulation, the parallel data of n+1bit is turned
Change the serial data of 1bit into, usual serial data is difference.For the passage of LVDS, Data [n：
0] it is 7bit, the parallel data of 7bit will be converted into the serial data of 1bit；For DSI passage,
Data[n：0] it is 8bit, the parallel data of 8bit will be converted into the serial data of 1bit.
Drive circuit mainly realizes the swing-scanning control of serial differential data and the reinforcement of driving force.For
For LVDS, the amplitude range of output difference signal is 250～450mv, and common mode range is in 1.125～1.375v
Between；For DSI, the amplitude range of DSI output difference signal is 140～270mv, common mode range
For 150～250mv.
Because data processing circuit is all some logic circuits, it is less to be commonly designed difficulty, and adopts low pressure
Device is realized, area occupied also very little.And drive circuit can be related to some analogue signals and Electro-static Driven Comb
(Electro-Static discharge, ESD) process etc., is usually used high tension apparatus and realizes, design difficulty
Larger, area occupied is very big, therefore becomes emphasis and the key of Interface design.
Specifically, Fig. 3 A is the typical structure of LVDS interface drive circuit, and the specification according to LVDS will
Ask, the amplitude output signal scope of LVDS is 250～450mv, and common mode range is in 1.125～1.375v
Between.Output voltage swing is 350mv in typical case, and common-mode voltage is 1.25v, now using two 3.5mA
Current source, and NM1, NM2, PM1, PM2 amount to 4 MOS switch come switching electric current path,
The electric current making 3.5mA flows through 100 Ω resistance of receiving terminal to obtain the differential signal that the amplitude of oscillation is 350mv,
Wherein NM1 and NM2 is N-type mos pipe, PM1 and PM2 is p-type mos pipe.
Fig. 3 B is the typical structure of DSI interface driving circuit, according to the code requirement of DSI, fast mode
Under, the amplitude range of DSI output signal is 140～270mv, and common mode range is 150～250mv.Typical feelings
Under condition, output voltage swing is 200mv, and common-mode voltage is 200mv, and now DSI uses accurate load resistance
R1, R2 shunt to reach the purpose producing differential signal together with external 100 Ω, in order to obtain common mode electricity
Press as 200mv, need Ib=8mA and R1, the resistance of R2 is accurate 50 Ω.
Based on the structure of existing LVDS interface drive circuit and DSI interface driving circuit, the present invention is implemented
Example provides a kind of circuit by LVDS interface and DSI interface duplex, and concrete structure refers to shown in Fig. 4, bag
Include data clock selection circuit 40, data clock synchronous circuit 41, mode control circuit 42, data conversion
Circuit 43 and drive circuit 44；Wherein,
Data clock selection circuit 40, is connected with mode control circuit 42 data clock synchronization circuit 41,
For selecting current interface modes under the Schema control of mode control circuit 42, receive outside input
Data signal and clock signal are simultaneously supplied to data clock synchronous circuit 41.
Data clock synchronous circuit 41, the data change-over circuit 43 that is connected with mode control circuit 42 is connected
Connect, for carrying out to the data signal and clock signal of input under the Schema control of mode control circuit 42
Synchronous, and the data signal after synchronization and clock signal are supplied to data converting circuit 43.
Data converting circuit 43, is connected with mode control circuit 42 and drive circuit 44, for being somebody's turn to do
Under the Schema control of mode control circuit 42 by the data signal after synchronization from Parallel transformation be serial, and defeated
Go out differential data signals to drive circuit 44.
Drive circuit 44, is connected with mode control circuit 42, for the pattern in mode control circuit 42
The lower differential data signals using input are controlled to control amplitude range and the common mode range of output signal.
Specifically, refering to shown in Fig. 5, the embodiment of the present invention gives the principle schematic of drive circuit 44,
This drive circuit 44 includes the first circuit 50, impedance control circuit 51, first switch group 52 and the second electricity
Road 53, wherein；
First circuit 50, is connected with mode control circuit 42 and first switch group 52, in pattern control
Export the electric current of corresponding modes to first switch group 52 under the Schema control of circuit 42 processed.
First switch group 52, is connected with data converting circuit 43, for exporting in data converting circuit 43
Controlling of differential data signals lower receive the electric current of the first circuit 50 output and export to second circuit 53.
Second circuit 53, is connected with first switch group 52 and impedance control circuit 51, for receiving first
The electric current of circuit 50 output, is shunted to the electric current of input with defeated under the control of impedance control circuit 51
Go out corresponding differential signal.
Specifically, second circuit 53 includes the first variable resistance RX1, the second adjustable resistance RX2 and first
Resistance R1, first switch group 52 includes first switch S1 and second switch S2, wherein：
The first end of first resistor R1 is connected with the first end of the first variable resistance RX1, first switch S1
As the negative output terminal of differential signal, the second end of first resistor R1 and the first of the second adjustable resistance RX2
End, second switch S2 connect the positive output end as differential signal, second end of the first variable resistance RX1
All it is connected with source electrode ground power supply with second end of the second adjustable resistance RX2.
Impedance control circuit 51 the 3rd end and the second adjustable resistance RX2 with the first variable resistance RX1 respectively
Three-terminal link, for controlling the resistance size of the first variable resistance RX1 and the second adjustable resistance RX2
Second circuit 53 is made to export corresponding differential signal.
It follows that one kind that Fig. 5 is drive circuit 44 in Fig. 4 realizes structure chart.Switch S1 and S2
The differential signal being inputted controls, and only opens one of them.Rx1 and Rx2 is variable resistance and resistance is in office
When carve and all keep identical, make Rx1=Rx2=Rx, resistance is controlled by impedance control circuit, according to work
Operation mode is determining resistance.Current source Ib is also required to determine current value according to mode of operation.
So that S1 opens as a example it is assumed that the common-mode voltage of output difference signal is as Vcom, the amplitude of oscillation of differential signal
For Vdiff, then be easy to be derived from following result：
Vp+Vn=Rx I=2Vcom
For LVDS mode of operation, in typical case it is desirable to Vcom=1.25v, signal swing is 0.35v,
So draw：
Rx=2050/7 ≈ 293 Ω, I=7/820 ≈ 0.0085A
For DSI mode of operation, in typical case it is desirable to Vcom=0.2v, signal swing is 0.2v, this
Sample draws：
Rx=50 Ω, I=0.008A
Understood by above analysis it is only necessary to select different Rx and Ib values to achieve that LVDS and DSI
Two kinds of mode of operations.And both reference current Ib are very close to only need to being finely adjusted to Ib.Than
As can be adjustable in relative broad range in order to meet output difference signal swing, the adjustable model of Ib can be set
Enclose for 8mA ± 3.5mA, i.e. 4.5mA～11.5mA, with 0.5mA as step-length.
Further, first switch S1 in Fig. 5 and second switch S2 can realize it using transistor
Function, if first switch S1 and second switch S2 are P-type transistor, first switch S1 PM1 table
Show, second switch S2 is represented with PM2, now the structure of drive circuit see shown in Fig. 6, wherein,
The negative output terminal of the differential data signals that the grid of first switch S1 is exported with data converting circuit 43 is connected,
The source electrode of first switch S1 is connected with the outfan of the first circuit 50, first switch S1 drain electrode and the
The first end of one resistance R1 connects, the difference that the grid of second switch S2 is exported with data converting circuit 43
The positive output end of data signal connects, and the source electrode of second switch S2 is connected with the outfan of the first circuit 50,
The drain electrode of described second switch S2 is connected with the second end of described first resistor R1.
The control of the differential data signals that first switch S1 and second switch S2 export in data converting circuit 43
System is lower to open one of them.
Again for example, if first switch S1 in Fig. 5 and second switch S2 are N-type transistor, now,
The differential data signals exporting data converting circuit in Fig. 6 43 only need to be controlled to exchange i.e. and to can achieve identical work(
Can, wherein, differential data signals that the grid of first switch S1 is exported with data converting circuit 43 just defeated
Go out end to connect, the source electrode of first switch S1 is connected with the outfan of the first circuit 50, first switch S1
Drain electrode is connected with the first end of first resistor R1, and the grid of second switch S2 is defeated with data converting circuit 43
The negative output terminal of the differential data signals going out connects, the output of the source electrode of second switch S2 and the first circuit 50
End connects, and the drain electrode of second switch S2 is connected with the second end of described first resistor R1.
The control of the differential data signals that first switch S1 and second switch S2 export in data converting circuit 43
System is lower to open one of them, specifically, first switch and second switch connection diagram see Fig. 7 A and
Shown in Fig. 7 B.
Further, the first variable resistance RX1 in Fig. 5 and the second adjustable resistance RX2 can be by making
Realize its function with the mode that fixed resistance is connected with N-type transistor, now the structure of drive circuit see
Shown in Fig. 6, the first variable resistance RX1 includes second resistance R2 and the first N-type transistor NM1, the
Two variable resistance RX2 include 3rd resistor R3 and the second N-type transistor NM2, wherein second resistance R2
Identical with the resistance size of 3rd resistor R3 and be more than 0, the first end of second resistance R2 and first resistor
The first end of R1 connects, and the source electrode of the first N-type transistor NM1 is connected with the second end of second resistance R2,
The first end of 3rd resistor R3 is connected with the second end of first resistor R1, the second N-type transistor NM2
Source electrode be connected with the second end of 3rd resistor R3, the first N-type transistor NM1 and the second N-type crystal
The drain electrode of pipe NM2 is all connected with source electrode ground power supply, and the first N-type transistor NM1 states the second N-type crystal
The grid of pipe NM2 is all connected with impedance control circuit 51；
Impedance control circuit 51 includes common mode feedback unit 610 and operational amplifier 611, described common-mode feedback
The positive input terminal of unit 610 is connected with the second end of first resistor R1, common mode feedback unit 610 negative defeated
Enter end to be connected with the first end of first resistor R1, the outfan of common mode feedback unit 610 and operational amplifier
611 positive input terminal connects, the negative input end input of operational amplifier 611 for the reference under different mode
Voltage, outfan grid and the 2nd N with the first N-type transistor NM1 respectively of operational amplifier 611
The grid of transistor npn npn NM2 connects, and reference voltage is the standard difference of different mode lower interface circuit output
The common-mode voltage of signal, it is second circuit 53 that common mode feedback unit 610 exports to operational amplifier 611
The common-mode voltage of output.
The differential signal that common mode feedback unit 610 and operational amplifier 611 export to second circuit 53 is carried out
Clamper, and export bias voltage the first N-type transistor NM1 and the second N-type transistor NM2 are carried out
Biasing, to control the resistance size of the first variable resistance RX1 and the second adjustable resistance RX2, makes the second electricity
Road 53 exports corresponding differential signal.
It follows that the physical circuit that Fig. 6 is Fig. 5 realizes example, PM1 and PM2 is two PMOS
Switch, is controlled by the differential signal DIN/DIP of the full amplitude of oscillation respectively, to select the path of electric current, opens wherein
One of；Realize variable resistance Rx1 and Rx2 with the series connection of a fixed resistance and a NMOS；With altogether
Mould feedback unit and operational amplifier (OP) the common-mode voltage of the differential signal of second circuit output is carried out
Clamper, then output bias voltage Vb respectively NM1 and NM2 is biased, with required for obtaining
Impedance Rx, this is a negative feedback process, if the difference common-mode voltage Vcom of second circuit output is more than
Vref, the bias voltage Vb of now operational amplifier output becomes big, so that variable resistance Rx1 and Rx2
Obtain resistance to diminish, so that the difference common-mode voltage Vcom that second circuit exports is diminished, and so on, Zhi Daoyun
Calculate the stable bias voltage Vb of amplifier output, then meet and require.According to the analysis in Fig. 5,
In LVDS mode, selection I_LVDS is 8.5mA, and Vref_LVDS is 1.25v；In DSI pattern
When, selection I_DSI is 8mA, and Vref_DSI is 0.2v.Specifically, when the fixing electricity in variable resistance
When resistance resistance is 0, now variable resistance Rx1 and Rx2 is used alone NMOS and realizes, as shown in Figure 8.
Impedance control circuit 51 in Fig. 6 is to adopt analogue signal to the control of variable resistance Rx1 and Rx2
Realize, impedance control circuit 51 can also adopt the method for digital calibration to realize, as shown in figure 9, resistance
Reactance-controlled circuit 51 includes calibrating current source 90, calibrates variable resistance RX0, comparator 91, adder substracter
92 and controller calibration 93, wherein：
Calibration current source 90 is used for producing calibration electric current Ic, and exports to calibrating variable resistance RX0, wherein
RX0 is identical with the resistance size of RX1 and RX2 in Fig. 5, and implementation is also identical, preferably,
RX0, RX1 can be realized using identical M NMOS tube is in parallel with RX2, and M is according to reality
Situation specifically determines.
The outfan of the positive input terminal of comparator 91 and calibration current source 90, calibration variable resistance RX0
First end connects, the input of the negative input end of comparator 91 for the calibration voltage under different mode, for right
The magnitude of voltage of input carries out size and compares, and exports comparative result to adder substracter 92, and calibration voltage is difference
Pattern index will definitely variable resistive value and the product calibrating current value.
The input of adder substracter 92 is connected with the outfan of comparator 91, for the comparative result according to input
Produce corresponding plus-minus to instruct and export to controller calibration 93.
The input of controller calibration 93 is connected with the outfan of adder substracter 92, controller calibration 93 defeated
Go out end and the 3rd end of standard variable resistance RX0, the 3rd end of the first variable resistance RX1, second variable
The three-terminal link of resistance RX2, for according to input plus-minus instruction control standard variable resistance RX0,
It is poor accordingly that the resistance size of the first variable resistance RX1 and the second adjustable resistance RX2 makes second circuit export
Sub-signal, second end of wherein said standard variable resistance RX0 is connected with source electrode ground power supply.
As shown in Figure 9, Ic is calibration electric current, flows through Rx0 and produces reference voltage V a, Va is with Rx0
Change and change, calibration voltage Vc is selected according to different mode of operations, and is compared with Va, will
Comparative result gives adder substracter 92, and adder substracter 92 produces corresponding plus-minus instruction according to the comparative result of input
And exporting to controller calibration 93, controller calibration 93 produces and exports calibration code Cal_code.Rx0、
Rx1 and Rx2 then using the parallel connection realization of M cell resistance R0, preferably can adopt by cell resistance R0
Realized with NMOS tube, the numerical value of M is controlled by calibration output code Cal_code.Defeated according to comparator 91
Go out result, calibration output code Cal_code is carried out Jia 1 in calibration each rising edge of clock Cal_clock or
The operation that subtracts 1, controller calibration 93 passes through to judge, the final calibration code obtaining closest to target resistance.School
The bit number of quasi- code Cal_code can select according to acceptable calibration accuracy.Such as, work as cell resistance
Number M=31 when, Cal_code can be selected to be 5bit, each bit simultaneously presses 1 respectively:2:4:8:16
Ratio control all resistance units.If Ic=20mA, in DSI pattern, in typical case,
Rx1=Rx2=Rx=50 Ω, now Vc=Rx*Ic=50*20=1000mV, if now Va is more than Vc,
Comparator 91 exports comparative result to adder substracter 92, and comparator 91 is according to the plus-minus of comparative result output+1
Instruction, conversely, the plus-minus of then output -1 instructs, controller calibration 93 instructs+1 according to current plus-minus,
The operation of corresponding calibration code execution+1 to current variable resistance Rx0 resistance, thus change calibrating resistance Rx0
Resistance, so that variable-resistance parallel units number is increased, reduce the resistance of Rx0, make reference voltage V a
Value reduce, and so on, when calibration code Cal_code is frequently beated between two values it is assumed that work as
Cal_code beat back and forth between 10000 and 10,001 2 times when, now select Cal_code be 10001
Calibration code, the Rx0 resistance size now controlling be 16+1=17 cell resistance R0 parallel connection, enter one
The resistance size of determination the first variable resistance RX1 of step and the second adjustable resistance RX2, makes RX0=RX1=
RX2, that is, the first variable resistance RX1 and the second adjustable resistance RX2 all adopt 17 cell resistance R0
Parallel way is realizing.
In sum, the embodiment of the present invention provides a kind of Low Voltage Differential Signal LVDS interface and display difference
DSI interface multiplexing circuit, this circuit includes：Data clock selection circuit, data clock synchronous circuit, mould
Formula control circuit, data converting circuit and drive circuit；Wherein, data clock selection circuit, with pattern control
Circuit data clock synchronization circuit processed is connected, for selecting to work as under the Schema control of mode control circuit
Front interface modes, the data signal of reception outside input and clock signal are simultaneously supplied to the synchronous electricity of data clock
Road；Data clock synchronous circuit, the data that is connected with mode control circuit change-over circuit is connected, and is used for
Under the Schema control of mode control circuit, data signal and clock signal are synchronized, and by after synchronization
Data signal and clock signal are supplied to data converting circuit；Data converting circuit, with mode control circuit and
Drive circuit is connected, under the Schema control of mode control circuit by the data signal after synchronization from simultaneously
Row is converted to serial, and output difference data signal is to drive circuit；Drive circuit, with mode control circuit
It is connected, for utilizing differential data signals to control output signal under the Schema control of mode control circuit
Amplitude range and common mode range, so, both achieved the multiplexing of LVDS interface and DSI interface additionally it is possible to
Reduce the number of packaging pin, reduce packaging cost, thus reduce interface resource wasting.
Those skilled in the art are it should be appreciated that embodiments of the invention can be provided as method, system or meter
Calculation machine program product.Therefore, the present invention can be using complete hardware embodiment, complete software embodiment or knot
Close the form of the embodiment of software and hardware aspect.And, the present invention can adopt and wherein wrap one or more
Computer-usable storage medium containing computer usable program code (including but not limited to disk memory,
CD-ROM, optical memory etc.) the upper computer program implemented form.
The present invention is to produce with reference to method according to embodiments of the present invention, equipment (system) and computer program
The flow chart of product and/or block diagram are describing.It should be understood that can by computer program instructions flowchart and
/ or block diagram in each flow process and/or the flow process in square frame and flow chart and/or block diagram and/
Or the combination of square frame.These computer program instructions can be provided to general purpose computer, special-purpose computer, embed
The processor of formula datatron or other programmable data processing device is to produce a machine so that passing through to calculate
The instruction of the computing device of machine or other programmable data processing device produces for realizing in flow chart one
The device of the function of specifying in individual flow process or multiple flow process and/or one square frame of block diagram or multiple square frame.
These computer program instructions may be alternatively stored in and computer or other programmable datas can be guided to process and set
So that being stored in this computer-readable memory in the standby computer-readable memory working in a specific way
Instruction produce and include the manufacture of command device, the realization of this command device is in one flow process or multiple of flow chart
The function of specifying in flow process and/or one square frame of block diagram or multiple square frame.
These computer program instructions also can be loaded in computer or other programmable data processing device, makes
Obtain and series of operation steps is executed on computer or other programmable devices to produce computer implemented place
Reason, thus the instruction of execution is provided for realizing in flow chart one on computer or other programmable devices
The step of the function of specifying in flow process or multiple flow process and/or one square frame of block diagram or multiple square frame.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know base
This creative concept, then can make other change and modification to these embodiments.So, appended right will
Ask and be intended to be construed to including preferred embodiment and fall into being had altered and changing of the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification and not take off to the embodiment of the present invention
Spirit and scope from the embodiment of the present invention.So, if these modifications of the embodiment of the present invention and modification belong to
Within the scope of the claims in the present invention and its equivalent technologies, then the present invention be also intended to comprise these change and
Including modification.
Claims (9)
1. a kind of Low Voltage Differential Signal LVDS interface and display difference DSI interface multiplexing circuit, its feature
It is, including：Data clock selection circuit, data clock synchronous circuit, mode control circuit, data turn
Change circuit and drive circuit；Wherein,
Described data clock selection circuit, with described mode control circuit and described data clock synchronous circuit phase
Connect, for selecting current interface modes under the Schema control of described mode control circuit, receive outside
The data signal of input and clock signal be supplied to described data clock synchronous circuit；
Described data clock synchronous circuit, is connected with described mode control circuit and described data converting circuit
It is connected, for entering to described data signal and clock signal under the Schema control of described mode control circuit
Row is synchronous, and the data signal after synchronization and clock signal are supplied to described data converting circuit；
Described data converting circuit, is connected with described mode control circuit and described drive circuit, for
Under the Schema control of described mode control circuit by the data signal after synchronization from Parallel transformation be serial, and defeated
Go out differential data signals to described drive circuit；
Described drive circuit, is connected with described mode control circuit, in described mode control circuit
Described differential data signals are utilized to control amplitude range and the common mode range of output signal under Schema control.
2. multiplex circuit as claimed in claim 1 is it is characterised in that described drive circuit includes first
Circuit, impedance control circuit, first switch group and second circuit；
Described first circuit, is connected with described mode control circuit and described first switch group, in institute
State the electric current exporting corresponding modes under the Schema control of mode control circuit to described first switch group；
Described first switch group, is connected with described data converting circuit, in described differential data signals
Control and lower receive the electric current of described first circuit output and export to described second circuit；
Described second circuit, is connected with described first switch group and described impedance control circuit, for receiving
The electric current of described first circuit output, shunts to described electric current under the control of described impedance control circuit
To export corresponding differential signal.
3. multiplex circuit as claimed in claim 2 is it is characterised in that described second circuit includes first
Variable resistance, the second adjustable resistance and first resistor, described first switch group includes first switch and second and opens
Close；
The first end of described first resistor is connected with the described first variable-resistance first end, described first switch
As the negative output terminal of described differential signal, the second end of described first resistor and described the second adjustable resistance
First end, described second switch connect the positive output end as described differential signal, described first variable resistance
The second end and described the second adjustable resistance the second end all with source electrode ground power supply be connected；
Threeth end variable-resistance with described first and described second can power transformation respectively for described impedance control circuit
The three-terminal link of resistance, for controlling the resistance size of described first variable resistance and described the second adjustable resistance
Second circuit is made to export corresponding differential signal.
4. multiplex circuit as claimed in claim 3 is it is characterised in that further include：
The negative output of the differential data signals that the grid of described first switch is exported with described data converting circuit
End connects, and the source electrode of described first switch is connected with the outfan of described first circuit, described first switch
Drain electrode be connected with the first end of described first resistor, the grid of described second switch and described data conversion electricity
Positive output end connection, the source electrode of described second switch and described first circuit of the differential data signals of road output
Outfan connect, the drain electrode of described second switch is connected with the second end of described first resistor；
The differential data signals that described first switch and described second switch export in described data converting circuit
Control under open；
Wherein, described first switch and described second switch are P-type transistor.
5. multiplex circuit as claimed in claim 3 is it is characterised in that further include：
The positive output of the differential data signals that the grid of described first switch is exported with described data converting circuit
End connects, and the source electrode of described first switch is connected with the outfan of described first circuit, described first switch
Drain electrode is connected with the first end of described first resistor, the grid of described second switch and described data converting circuit
The negative output terminal connection of the differential data signals of output, the source electrode of described second switch and described first circuit
Outfan connects, and the drain electrode of described second switch is connected with the second end of described first resistor；
The differential data signals that described first switch and described second switch export in described data converting circuit
Control under open；
Wherein, described first switch and described second switch are N-type transistor.
6. the multiplex circuit as described in claim 3,4 or 5 is it is characterised in that described first can power transformation
Resistance includes second resistance and the first N-type transistor, and described the second adjustable resistance includes 3rd resistor and second
The resistance size of N-type transistor, wherein said second resistance and described 3rd resistor is identical and is more than 0, institute
The first end stating second resistance is connected with the first end of described first resistor, described first N-type transistor
Source electrode is connected with the second end of described second resistance, the first end of described 3rd resistor and described first resistor
Second end connects, and the source electrode of described second N-type transistor is connected with the second end of described 3rd resistor, institute
State the first N-type transistor and the drain electrode of described second N-type transistor is all connected with source electrode ground power supply, described
The grid of the first N-type transistor and described second N-type transistor is all connected with described impedance control circuit；
Described impedance control circuit includes common mode feedback unit and operational amplifier, described common mode feedback unit
Positive input terminal is connected with the second end of described first resistor, the negative input end of described common mode feedback unit with described
The first end of first resistor connects, and the outfan of described common mode feedback unit is just defeated with described operational amplifier
Enter end to connect, the input of the negative input end of described operational amplifier for the reference voltage under different mode, described
The outfan of operational amplifier is connected with the grid of the first N-type transistor grid and the second N-type transistor respectively
Connect, described reference voltage is the common-mode voltage of the standard difference signal of different mode lower interface circuit output；
The differential signal that described common mode feedback unit and described operational amplifier export to described second circuit enters
Row clamper, and export bias voltage described first N-type transistor and described second N-type transistor are carried out
Biasing, to control the resistance size of described first variable resistance and described the second adjustable resistance, makes second circuit
Export corresponding differential signal.
7. the multiplex circuit as described in claim 3,4 or 5 is it is characterised in that described first can power transformation
Hinder for the 3rd N-type transistor, described the second adjustable resistance is the 4th N-type transistor, described 4th N-type
The source electrode of transistor is connected with the first end of described first resistor, the source of described second N-type transistor
Pole is connected with the second end of described first resistor, described first N-type transistor and described second N-type crystal
The drain electrode of pipe is all connected with source electrode ground power supply, described first N-type transistor and described second N-type transistor
Grid be all connected with described impedance control circuit；
Described impedance control circuit includes common mode feedback unit and operational amplifier, described common mode feedback unit
Positive input terminal is connected with the second end of described first resistor, the negative input end of described common mode feedback unit with described
The first end of first resistor connects, and the outfan of described common mode feedback unit is just defeated with described operational amplifier
Enter end to connect, the input of the negative input end of described operational amplifier for the reference voltage under different mode, described
The outfan of operational amplifier is connected with the grid of the first N-type transistor grid and the second N-type transistor respectively
Connect, described reference voltage is the common-mode voltage of the standard difference signal of different mode lower interface circuit output；
The differential signal that described common mode feedback unit and described operational amplifier export to described second circuit enters
Row clamper, and export bias voltage described first N-type transistor and described second N-type transistor are carried out
Biasing, to control the resistance size of described first variable resistance and described the second adjustable resistance, makes second circuit
Export corresponding differential signal.
8. the multiplex circuit as described in claim 3,4 or 5 is it is characterised in that described impedance control is electric
Road include calibrate current source, calibrate variable resistance, comparator, adder substracter and controller calibration,
Described calibration current source, for producing calibration electric current, and exports to calibration variable resistance；
The positive input terminal of described comparator and the described outfan calibrating current source, calibration variable-resistance first
End connects, the input of the negative input end of described comparator for the calibration voltage under different mode, for input
Magnitude of voltage carry out size and compare, and export comparative result to described adder substracter, described calibration voltage is difference
Pattern index will definitely variable resistive value and the product calibrating current value；
The input of described adder substracter is connected with the outfan of described comparator, for the comparison knot according to input
Fruit produces corresponding plus-minus and instructs and export to described controller calibration；
The input of described controller calibration is connected with the outfan of adder substracter, the output of described controller calibration
End with described calibrate variable-resistance 3rd end, the first variable-resistance 3rd end, the second adjustable resistance the
Three-terminal link, for according to input plus-minus instruction control described calibration variable resistance, the first variable resistance and
The resistance size of described the second adjustable resistance makes second circuit export corresponding differential signal, wherein said standard
Variable-resistance second end is connected with source electrode ground power supply.
9. multiplex circuit as claimed in claim 8 is it is characterised in that described calibration variable resistance is M
Individual cell resistance is in parallel, and described cell resistance is the NMOS tube setting resistance, and M is to set positive integer.
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| CN201510466134.7A CN106407138B (en) | 2015-07-30 | 2015-07-30 | A kind of LVDS interface and DSI interface multiplexing circuit |
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| CN201510466134.7A CN106407138B (en) | 2015-07-30 | 2015-07-30 | A kind of LVDS interface and DSI interface multiplexing circuit |
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| CN109683836A (en) * | 2018-12-04 | 2019-04-26 | 珠海妙存科技有限公司 | A kind of driving device being compatible with a variety of display protocol hardware interfaces |
| CN109683836B (en) * | 2018-12-04 | 2022-04-19 | 珠海妙存科技有限公司 | Driving device compatible with hardware interfaces of various display protocols |
| CN116561035A (en) * | 2023-07-07 | 2023-08-08 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
| CN116561035B (en) * | 2023-07-07 | 2023-10-31 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
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