CN106373897B - 将半导体芯片定位在载体上并使其与载体连接的方法 - Google Patents

将半导体芯片定位在载体上并使其与载体连接的方法 Download PDF

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CN106373897B
CN106373897B CN201610391356.1A CN201610391356A CN106373897B CN 106373897 B CN106373897 B CN 106373897B CN 201610391356 A CN201610391356 A CN 201610391356A CN 106373897 B CN106373897 B CN 106373897B
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carrier
semiconductor chip
chip
assembly tool
dielectric layer
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CN106373897A (zh
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N·厄施勒
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明一方面涉及一种用于将半导体芯片(100)定位在载体(3)上的方法。半导体芯片具有半导体本体(1)以及钝化物(4)，所述半导体本体具有底侧(1b)以及与所述底侧相对的上侧(1t)，所述钝化物布置在所述上侧上。在该方法中，半导体芯片被接收并且被放置在载体上。借助于挤压力(F)将半导体芯片压到载体上，以使得挤压力仅仅在一个或多个布置在上侧上的相连的芯片金属化部段(21，23)之上作用于半导体芯片，其中，所述相连的芯片金属化部段中的每一个具有一个环形地闭合的边缘部段(21r，23r)，所述边缘部段在每个垂直于挤压方向(z)的方向(x，y)上具有一个大于零的最小宽度(b)，其中，挤压力不在所述边缘部段之上作用于所述半导体芯片。

Description

将半导体芯片定位在载体上并使其与载体连接的方法
技术领域
本发明涉及一种用于将半导体芯片定位在载体上的方法以及一种用于使半导体芯片与载体进行材料配合地连接的方法。
背景技术
为了将半导体芯片装配在载体上也可以是必要的是，将半导体芯片压到载体上。例如在建立半导体芯片和载体之间扩散焊接的或烧结的连接的情况下，然而也在使用其他连接技术的情况下，当以确定的最小挤压力进行挤压时，则可以建立特别可靠的材料配合的连接。
然而在挤压时存在下述的危险，即装配工具损坏半导体芯片的钝化层，因此，随着时间的推移，湿气会到达半导体芯片的半导体本体上。此外，所述损坏会消极地影响半导体芯片的耐压强度。另一方面期望的是，将半导体芯片的尽可能大的区域压到载体上，以便实现高质量的平面的连接。这例如在制造大功率半导体模块时是有利的，因为在此具有非常大的基面的半导体芯片用作半导体芯片。
发明内容
本发明的目的在于，提供一种用于将半导体芯片定位在载体上的方法，以及一种用于使半导体芯片与载体连接的方法。该目的通过根据权利要求1所述的一种用于将半导体芯片定位在载体上的方法以及通过据权利要求13所述的一种用于使半导体芯片与载体进行材料配合地连接的方法来实现。本发明的构型和进一步方案是从属权利要求的内容。
第一方面涉及一种用于将半导体芯片定位在载体上的方法。半导体芯片具有半导体本体以及钝化物，所述半导体本体具有底侧以及与所述底侧相对的上侧，所述钝化物布置在上侧上。在该方法中，半导体芯片被接收并且被放置在载体上。借助于挤压力将半导体芯片这样压到载体上，以使得挤压力仅仅在一个或多个布置在上侧上的相连的芯片金属化部段之上作用于半导体芯片，其中，所述相连的芯片金属化部段中的每一个具有一个环形地闭合的边缘部段，所述边缘部段在每个垂直于挤压方向的方向上具有一个大于零的最小宽度，其中，挤压力不在所述边缘部段的上部上作用于半导体芯片。
第二方面涉及一种下述的方法，其中使用根据第一方面的方法以使半导体芯片与载体进行材料配合地连接。为此，根据按照第一方面的方法将半导体芯片定位在载体上并且压到载体上。在此，这样实现将半导体芯片放置在载体上，以使得在放置之后并且在挤压期间将一个连接介质层布置在底侧和载体之间。
附图说明
下面根据实施例参考附图说明本发明。在附图中，相同的元件以相同的附图标记标出。附图中的视图不是按照比例的。附图中：
图1A示出半导体芯片的横截面图。
图1B示出在将半导体芯片安置在载体上期间由装配工具保持的根据图1A的半导体芯片。
图1C示出根据图1A和1B的半导体芯片，其中所述半导体芯片通过装配工具压到载体上，以便使所述半导体芯片与载体连接。
图1D示出在抬起装配工具之后与载体连接的半导体芯片。
图2示出在将半导体芯片压到载体上期间根据图1C的布置的放大的部段A。
图3示出芯片金属化部段的俯视图，所述芯片金属化部段被施加到根据图1A的半导体芯片的半导体本体的上侧上。
图4A示出半导体芯片的横截面图，半导体芯片具有带上侧的半导体本体，多个相连的芯片金属化部段被施加到所述上侧上。
图4B示出在将半导体芯片安置在载体上期间由装配工具保持的根据图4A的半导体芯片。
图4C示出根据图4A和4B的半导体芯片，其中所述半导体芯片通过装配工具压到载体上，以便使所述半导体芯片与载体连接。
图4D示出在抬起装配工具之后与载体连接的半导体芯片。
图5示出一个下述的布置，该布置相应于在将半导体芯片压到载体上期间根据图4C的布置，其中，装配工具相对于根据图4C的装配工具被修改。
图6示出一个下述的布置，该布置以如下区别相应于根据图5的装置，即将一个保护层施加到至少一个相连的芯片金属化部段上，所述芯片金属化部段被施加到半导体芯片的上侧上，在所述装配工具将半导体芯片压到载体上期间，装配工具被压到所述保护层上。
图7示出在将半导体芯片压到载体上期间根据图6的布置的放大的部段B。
图8示出根据图4C的半导体芯片的俯视图。
图9示出根据图4C的装配工具的底侧的视图。
具体实施方式
图1A以横截面图示出半导体芯片100。半导体芯片100是任意的半导体元件、例如MOSFET(Metal Oxide Semiconductor Field-Effect Transistor，金属氧化物半导体场效应晶体管)、IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)、JFET(Junction Field-Efffect Transistor，结型场效应晶体管)、HEMT(High ElectorMobility Transistor，高电子迁移率晶体管)、晶闸管或二极管。
半导体芯片100具有半导体本体1，所述半导体本体具有上侧1t和与所述上侧1t相对的底侧1b。将相连的芯片金属化部段21以背向半导体本体1的上侧21t施加到上侧1t上。此外，芯片金属化部段21具有环绕的侧面的边缘21s，所述边缘环绕地完全由介电钝化物4、例如酰亚胺或聚酰亚胺或者其他适用的钝化电介质覆盖。钝化物4例如可以具有至少10μm、例如10μm至100μm范围内的厚度d4。此外，可选地如同所示的那样可以将下部的芯片金属化层22施加到半导体本体1的底侧1b上。
如图1B所示地，根据图1A的半导体芯片100可以借助于装配工具5(例如“拾取和放置工具”)来接收，并且如同结果在图1C中所示的那样放置在载体3上并且通过装配工具5压到载体3上。
载体3理论上可以是任意的载体、例如引线框架(“leadframe”)或电路板。所示的载体3仅仅示意性地构造为陶瓷基底、即具有陶瓷绝缘载体的电路板。然而原则上本发明可以利用其他载体实现。
载体3具有介电绝缘载体30，所述介电绝缘载体在彼此相对的侧上设有上部的金属化层31或下部的金属化层32。介电绝缘载体30由电绝缘陶瓷、例如氧化铝(Al2O3)、氮化铝(AlN)、氧化锆(ZrO2)、氮化硅(Si3N4)。
为了接收半导体芯片100并且至少直至保持在载体3上，装配工具5可以具有一个或多个吸入通道50，所述吸入通道关于包围半导体芯片100和装配工具5的大气的周围环境压力可以被施加负压p50，从而半导体芯片100可以说被吸到装配工具5的底侧5b上。如图1B所示地，以所述的或任意其他的方式由装配工具5保持的半导体芯片100可以放置在载体3上并且借助于挤压力F5压到载体3上。将半导体芯片100压到载体3上可以同样借助于装配工具5实现。挤压力F5可以例如为至少1N或甚至至少5N。
在挤压期间，装配工具5能够可选地直接与芯片金属化部段21接触，也就是说，装配工具5和芯片金属化部段21之间的间距a可以等于零。
将半导体芯片100放置在载体3上可以用于使半导体芯片100与载体3进行材料配合的连接。为此，在将半导体芯片100放置在载体3上之前，在半导体芯片100和载体3之间加入连接介质层70。在将设置有连接介质层70的半导体芯片100放置到载体3上之前，如图1B所示地，例如可以将连接介质层70施加到下部的芯片金属化层22上。替换地，在将半导体芯片100放置到被施加在载体3上的连接介质层70上之前，也可以将连接介质层70施加到载体3上。根据一个另外的构型，在将半导体芯片100以位于其上的一个连接介质层70放置到被施加在载体3上的另一个连接介质层70上之前，可以将一个连接介质层70施加到下部的芯片金属化层22上，并且将另一个连接介质层70施加在载体3上，从而一个连接介质层70和另一个连接介质层70结合成一个唯一的连接介质层。
在将半导体芯片100放置到载体3上之后并且在将半导体芯片100压到载体3上期间，如果应该在半导体芯片100和载体3之间建立材料配合的连接，那么可以在半导体芯片100和载体3之间布置连接介质层70。连接介质层70连续地在半导体芯片100和载体3之间延伸。
连接介质层70可以例如包含焊料、特别是扩散焊料或者由其构成，或者所述连接介质层可以包含干燥的金属粉末、特别是银粉或者由其构成。然而同样可能的是，粘合材料、例如由导电的粘合材料或者电绝缘的粘合材料用作粘合材料层。如果应该在半导体芯片100和载体3之间不仅建立材料配合的连接而且建立导电的连接，那么连接介质层70优选地是导电的。
在建立材料配合的连接期间，连接介质层70转换成一个连接层71，所述连接层使半导体芯片100与载体3材料配合地并且固定地连接，这在图1D中示出。在建立所述连接之后，装配工具5如图1D所示地从与载体3连接的半导体芯片100抬起。为此，负压p50从一个或多个吸入通道50中取消，从而所述吸入通道中产生的负压p50增大到直至大约周围环境压力。
此外由图1B至1D得知，将半导体芯片100压到载体3上可以通过以下方式实现，即将半导体芯片100和载体3以及必要时位于所述半导体芯片和载体之间的连接介质层70压紧在装配工具5和配合保持件6之间，所述配合保持件位于载体3的背向装配工具5的侧上。载体3能够例如以可松动的方式放置在配合保持件6上，或者所述载体能够以任意的方式固定在所述保持件上。
装配工具5和/或配合保持件6能够可选地具有集成的加热装置51或61，借助于所述加热装置可以在挤压期间(图1C)将热量引导到连接介质层70，以便加速接合过程。如果半导体芯片100在未与载体3建立形状配合的连接的情况下放置在所述载体上，那么当然也可以存在加热装置51或61，因为加热装置51或61不必必需激活。
借助于加热装置51和/或61可以将连接介质层70加热到适用于接合过程的过程温度，如果连接介质层70例如具有焊料，那么所述连接介质层在挤压期间被加热到比焊料的熔点高的温度。如果连接介质层70例如具有金属粉末、例如银粉，那么所述连接介质层在挤压期间被加热到比使所述金属粉末(在例如至少100℃下)烧结的温度高的温度。
对于是否激活，在哪个时间激活加热装置51，61(只要存在)并且在此在哪个温度上产生的问题，原则上是任意的。根据一个实例，半导体芯片100如图1B所示地可以在放置在载体3上之前设置有连接介质层70。在此，装配工具5的加热装置51可以不被激活。在设置有连接介质层70的半导体芯片100放置在载体3上之前，载体3可以通过配合保持件6的加热装置61预热。在此，将载体3预热的温度比在放置之前位于半导体芯片100上的连接介质层70上所具有的温度高得多(例如至少为100℃)。因此，连接介质层70从放置的时间点起被显著地加热。为了保持或者增加将热量输入到连接介质层70中，可以从放置的时间点起使加热装置61保持激活或者重复地激活，和/或加热装置51可以被激活。
在所述的实例中，首先从所述放置起对连接介质层70进行加热。因此，例如可以防止的是，在包含在连接介质层70中的待烧结的金属粉末的情况下，烧结过程已经在所述放置之前开始，这对于所建立的接合连接的质量是不利的。然而首先从所述放置起对连接介质层70的加热可以不仅在建立烧结的连接的情况下实现，而且可以在任意的其他连接技术的情况下实现。
如果连接介质层70具有焊料或者由焊料构成，那么在挤压期间通过激活加热装置51和/或61将所述连接介质层加热到比焊料的熔点高的温度。焊料由此熔化。接着，所述温度在保持挤压力的情况又至少下降到下述程度，直到熔化的焊料凝固到下述程度，即存在一个固定的连接层71。在挤压期间所选择的参数：挤压力、连接介质层的温度和挤压持续时间在此可以这样选择，即由连接介质层70不是产生简单的焊接层(这同样是可能的)，而是产生扩散焊接层。
如图1C所示地，挤压力F5在方向z上作用。所述方向在下文也称为“挤压方向”。为了避免在芯片金属化部段21的侧面的边缘21s上放置的钝化物4在挤压期间由装配工具5损坏，装配工具5的底侧5b上的几何形状构造为，即所述装配工具仅仅在芯片金属化部段21的内部区域21i之上(即方向与挤压方向z)压到半导体芯片100上，而不是在环形地闭合的边缘部段21r之上压到半导体芯片上，该边缘部段是芯片金属化部段21的外部的环形地闭合的边缘部段。这在下文参考图2详细地说明，所述图示出根据图1C的布置的放大的部段A。
如图1A-1D和2示意性所示地，所述相连的芯片金属化部段21的、背向半导体本体1的上侧21t不必必需是平坦的，所述芯片金属化部段安置在半导体本体1的上侧1t上。如同特别是在图2中可清楚看到的那样，该上侧例如可以具有一个例如在MOSFET或IGBT或者其他晶体管元件的源极金属化或发射极金属化的情况下的结构，所述晶体管元件具有彼此电并联的晶体管单体的胞状结构。芯片金属化部段21的所述不平坦的上侧21t可以例如由此造成使位于金属化部段21下方的元件结构构造在半导体本体1的上侧1t处。在此指出，所述结构在本附图中未示出。
如图2所示地，芯片金属化部段21具有边缘部段21r。所述边缘部段如同已述地那样环形地闭合。在每个垂直于挤压方向z的方向上、例如在所示的x和y方向上，然而也在每个其他在x-y平面中所示的方向上，边缘部段21r具有大于零的最小宽度b。所述最小宽度可以例如在每个垂直于挤压方向z的方向上等于100μm或者甚至等于200μm。简化地表明，在不在边缘部段21r的位点S上挤压期间，出自装配工具5的挤压力沿着连续的平行于挤压方向z延伸的直的线段传递。
另外表明，对于环形地闭合的边缘部段21r的每个位点S适用的是，在挤压期间，沿着挤压方向z延伸穿过所述位点S的直线g具有线段[P1；P2]，所述线段不延伸穿过固定的本体。通过使线段[P1；P2]不在固定的本体中延伸，不存在沿着挤压方向z直线地传递的作用到所述位点S上的挤压力，也就是说，不存在沿着直线g穿过地在装配工具5和所述位点S之间传递的挤压力。也就是说由此避免了当在边缘部段21r的区域中挤压期间导致不期望地大的力传入到半导体芯片100上。因此特别是防止了钝化物4在其特别敏感的区域在边缘部段21r之上受到压力载荷并且在此例如通过过高的挤压力和/或通过将留存在钝化物4上的污物颗粒压入到钝化物4中而损坏。
如同在图2中可以看到的那样，线段[P1；P2]的起点P1位于那里，平行于挤压方向z延伸穿过所述位点S的直线g在那里与装配工具5的底侧5b相交。线段[P1；P2]的终点P2位于下述的位点上，直线g在所述位点上与芯片金属化部段21的背向半导体本体1的上侧21t相交。
与此相反，在内部的区域21i中能够将挤压力从装配工具5直线地传递到芯片金属化部段21上。所述直线的力传递同样在图2中示出。直线h垂直于挤压方向z延伸穿过一个位点，在所述位点上，装配工具5的底侧5b直接放置在芯片金属化部段21上。在所述位点上，出自装配工具5的在挤压方向z上作用的挤压力直接传递到芯片金属化部段21上。相应地适用于芯片金属化部段21的上侧21t的其他位点，在所述其他位点上，装配工具5的底侧5b贴靠在芯片金属化部段21的上侧21t上。
图3以从上侧21t的视角示出前述的半导体芯片100的芯片金属化部段21的俯视图。半导体芯片100的其他组成部分、特别是钝化物4未示出。在此，虚线示出边缘部段21r的内边界。
图4A示出半导体芯片100的一个另外的实例。所述半导体芯片具有多个相连的芯片金属化部段21，23。一个多个分别相连的芯片金属化部段21(也就是说，附图标记21可以表示两个不同的彼此间隔开的芯片金属化部段21，或者替换地表示相同的芯片金属化部段21)可以例如是一个或多个源极金属化层或者是一个或多个发射极极金属化层。芯片金属化部段23可以例如是栅极金属化层、例如所谓的栅极通路(Gate-Runner)或栅极指叉(Gate-Finger)，或者是用于外置的电触点的栅极焊盘(Gate-Pad)。钝化物4突出于所述相连的芯片金属化部段21或23中的每一个的边缘部段21r，23r。
下面根据图4B至4D说明根据图4A的半导体芯片100与载体3的材料配合的连接的建立。该方法与根据图1B至1D所述的方法的区别在于，即装配工具5在其底侧5b上构造为不同的。也就是说，装配工具5在其底侧5b上具有一个或多个凹进部55，在半导体芯片100由装配工具5保持(图4B)期间并且在半导体芯片100通过装配工具5压到载体3上(图4C)期间，钝化物4的部段啮合到所述凹进部中。凹进部55构造为，出自装配工具5的挤压力沿着平行于挤压方向z延伸的直线的线段仅仅传递到芯片金属化部段21，23的所述区域上，该区域不是边缘部段21r，23r的组成部分。凹进部55可以构造为，装配工具5在解压期间不与钝化物4接触。一个或多个所述凹进部55的(在挤压期间平行于挤压方向z测量的)深度t55可以例如是至少0.3mm。所述深度可以例如处于0.3mm至0.5mm的范围内。
在根据图4B至4D的实例中实现了不仅通过芯片金属化部段21而且通过芯片金属化部段23将挤压力传递到半导体芯片100上。在挤压期间，装配工具5可以与芯片金属化部段21和23直接接触，也就是说，在装配工具5和芯片金属化部段21之间的以及在装配工具5和芯片金属化部段23之间的间距a可以等于零。
图5示出一个另外的替换的构型。该构型相应于根据图4c的布置具有下述的区别之处，即在此不将挤压力通过芯片金属化部段23(例如栅极电路或栅极焊盘)导入。在此，在挤压期间装配工具5和芯片金属化部段21之间的间距可以等于零，而装配工具5在挤压期间与芯片金属化部段23可以间隔开。
图6还示出一个另外的构型，该构型基本上相应于根据图5的构型，然而具有下述的区别，即在芯片金属化部段21或23的背向半导体本体1的上侧21t和/或23t上还施加一个保护层8，所述保护层保护相关的金属化部段21，23例如免受氧化的影响。因此，从装配工具5出发将挤压力F5导入到半导体芯片100上不是直接地在一个或多个上部的芯片金属化部段21，23上实现，而是间接地通过保护层8实现。所述保护层8当然也可以施加到根据图1A的半导体芯片100的芯片金属化部段21的背向半导体本体1的上侧21t上，确切地说，在整个方法期间直至将装配工具5从半导体芯片100抬起(图1D)。用于所述保护层8的材料原则上可以是任意的。所述材料可以是导电的(金属的)或者电介质的。适合的材料例如是氮化硅或氧化铝。
因为保护层8在挤压期间布置在一方面装配工具5和另一方面上部的芯片金属化部段21，23之间，所以装配工具5在挤压期间于一个、多个或所有的上部的芯片金属化部段21，23间隔开并且与其分别具有最大间距a。最大间距a可以例如选择为小于或等于1μm。
图7示出根据图6的布置的放大的部段B。在此从附加的保护层8出发示出同样如同在根据图2的布置的情况下那样的关系。
芯片金属化部段21具有环形地闭合的边缘部段21r。在每个垂直于挤压方向z的方向上、例如在所示的x和y方向上，然而也在每个其他在x-y平面中所示的方向上，边缘部段21r具有大于零的最小宽度b。所述最小宽度可以例如在每个垂直于挤压方向的方向上等于至少100μm或者甚至等于至少200μm。简化地表明，在不在边缘部段21r的位点S上挤压期间，出自装配工具5的挤压力沿着连续的平行于挤压方向z延伸的直的线段传递。简化地表明，为了避免在边缘部段21r上部的区域中损坏钝化物4，在挤压期间不将出自装配工具5的挤压力沿着连续的平行于挤压方向z延伸的直线的线段传递到边缘部段21r的位点上。
另外表明，对于环形地闭合的边缘部段21r的每个位点S适用的是，在挤压期间，沿着挤压方向z延伸穿过所述位点S的直线g具有线段[P1；P2]，所述线段不延伸穿过固定的本体。通过使线段[P1；P2]不在固定的本体中延伸，不存在沿着挤压方向z直线地传递的作用到所述位点S上的挤压力，也就是说，不存在沿着直线g穿过地在装配工具5和所述位点S之间传递的挤压力。也就是说由此避免了当在边缘部段21r的区域中挤压期间导致不期望地大的力传入到半导体芯片100上。因此特别是防止了钝化物4在其特别敏感的区域在边缘部段21r之上受到压力载荷并且在此被损坏。
如同在图7中可以看到的那样，线段[P1；P2]的起点P1位于那里，平行于挤压方向z延伸穿过所述位点S的直线g在那里与装配工具5的底侧5b相交。线段[P1；P2]的终点P2位于下述的位点上，直线g在所述位点上与保护层8的背向半导体本体1的上侧8t相交。
与此相反，如同在没有保护层8的布置的情况(图2)下那样，在内部的区域21i中能够将挤压力从装配工具5直线地传递到芯片金属化部段21上。所述直线的力传递，在图7中示出。直线h垂直于挤压方向z延伸穿过上侧8t的一个下述的位点，在所述位点上，装配工具5的底侧5b直接放置在保护层8上。在所述位点上，出自装配工具5的在挤压方向z上作用的挤压力间接地通过保护层8、确切地说沿着直线的平行于挤压方向z的线段传递到芯片金属化部段21上。相应地适用于其他位点，在所述其他位点上，装配工具5的底侧5b靠置在保护层8的上侧8t上。
图8还示出根据图5的半导体芯片100的俯视图。在所述视图中未示出装配工具、载体3以及配合保持件6。如同可以看到的那样，多个(在此仅仅示例性地为六个)芯片金属化部段21以及一个芯片金属化部段23(例如栅极焊盘)位于半导体芯片100的上侧1t上。所述芯片金属化部段21或23中的每一个分别具有一个环形地闭合的边缘部段21r或23r，所述边缘部段分别由两个虚线示出。所述边缘部段21r或23r的外部边缘(外部边缘分别通过外部的虚线示出)分别完全由钝化物4覆盖。在挤压期间，挤压力分别仅仅位于相关的芯片金属化部段21或23的内部的部段21i或23i上，所述内部的部段位于相关的芯片金属化部段21或23的相应的环形的边缘部段21r或23r的内部上。
图9还示出适用于挤压根据图8的半导体芯片100的装配工具5的底侧5b。在此可以看到，装配工具5可以在其底侧5b上不仅具有一个凹进部，而且具有两个或更多个凹进部55.
在前述的方法中，装配工具5整个或者至少其底侧5b例如由金属构成，或者由塑料构成。通常装配工具5可以构造为，所述装配工具或者至少其底侧5b在最大至少300℃下是耐温度变化的。
上部的芯片金属化部段21，23(只要存在)可以由一个金属层构成，或者由两个或更多个由不同材料构成的金属层构成。芯片金属化部段21，23的背向半导体本体1的上侧可以例如由铝或铝合金构成、由铜或铜合金构成或者由镍或镍合金构成。
在本发明中，装配工具5构造为，挤压力F5基本上仅仅作用到激活的芯片区域上(即到内部的芯片金属化部段21i或23i的下部的区域上)，然而不作用到未激活的芯片区域上。这可以通过如下方式实现，即装配工具5的底侧5b的几何形状大致相应于激活的芯片区域的基面，其中，装配工具5在所有未激活的芯片区域中具有凹进部55，所述凹进部55这样确定尺寸，即装配工具5在挤压期间在凹进部55的区域中不将力传递到半导体芯片100上。装配工具5特别是可以构造为，所述装配工具在挤压期间不会直接地压到钝化物4上。

Claims (17)

1.一种用于将半导体芯片(100)定位在载体(3)上的方法，其中所述半导体芯片(100)具有半导体本体(1)和钝化物(4)，所述半导体本体具有底侧(1b)以及与所述底侧(1b)相对的上侧(1t)，所述钝化物布置在所述上侧(1t)上，其中，所述方法包括：
接收所述半导体芯片(100)并且将所述半导体芯片(100)放置在所述载体(3)上；以及
借助于挤压力(F)将所述半导体芯片(100)压到所述载体(3)上，以使得所述挤压力(F)仅仅在一个或多个布置在所述上侧(1t)上的相连的芯片金属化部段(21，23)之上作用于所述半导体芯片(100)，其中所述相连的芯片金属化部段(21，23)中的每一个具有环形地闭合的边缘部段(21r，23r)，所述边缘部段在每个垂直于挤压方向(z)的方向(x，y)上具有一个大于零的最小宽度(b)，并且其中所述挤压力(F)不在所述边缘部段(21r，23r)之上作用于所述半导体芯片(100)，
其中所述半导体芯片(100)具有介电的保护层(8)，所述保护层被施加在所述芯片金属化部段(21，23)或多个芯片金属化部段(21，23)的背向所述半导体本体(1)的上侧(21t，23t)上。
2.根据权利要求1所述的方法，其中所述钝化物(4)在沿着所述挤压方向(z)挤压期间具有至少10μm的厚度(d4)。
3.根据权利要求1或2所述的方法，其中所述钝化物(4)具有酰亚胺或聚酰亚胺或者由酰亚胺或聚酰亚胺构成。
4.根据权利要求1或2所述的方法，其中所述挤压力(F5)为至少1N或至少5N。
5.根据权利要求1或2所述的方法，其中所述最小宽度(b)等于100μm或者等于200μm。
6.根据权利要求1或2所述的方法，其中连接介质层(70)具有焊料或银粉，在将所述半导体芯片(100)放置在所述载体(3)上之前，将所述连接介质层(70)加入到所述半导体芯片(100)和所述载体(3)之间。
7.根据权利要求1或2所述的方法，其中，接收所述半导体芯片(100)以及将所述半导体芯片(100)放置在所述载体(3)上借助于装配工具(5)进行，其中在将所述半导体芯片(100)放置在所述载体(3)上之后，所述底侧(1b)朝向所述载体(3)，并且所述上侧(1t)朝向所述装配工具(5)。
8.根据权利要求7所述的方法，其中，在挤压期间，对于每个所述边缘部段(21r，23r)的每个位点(S)适用的是，沿着所述挤压方向(z)延伸穿过所述位点(S)的直线(g)具有线段([P1；P2])，所述线段不延伸穿过所述边缘部段(21r，23r)的本体。
9.根据权利要求7所述的方法，其中，所述装配工具(5)具有凹进部(55)，所述钝化物(4)的部段在挤压期间啮合在所述凹进部中。
10.根据权利要求9所述的方法，其中，所述凹进部(55)平行于所述挤压方向(z)具有至少0.3mm的深度(t55)。
11.根据权利要求7所述的方法，其中，所述装配工具(5)在挤压期间与布置在所述上侧(1t)上的相连的芯片金属化部段(21，23)中的每一个芯片金属化部段以不宽于1μm的间距间隔开。
12.根据权利要求7所述的方法，其中，所述装配工具(5)在挤压期间不与所述半导体芯片(100)的电介质接触。
13.一种用于使半导体芯片(100)与载体(3)进行材料配合地连接的方法，所述方法包括：
根据前述权利要求中任一项所述的方法将半导体芯片(100)定位在载体(3)上以及将所述半导体芯片(100)压到载体(3)上，其中实施将所述半导体芯片(100)放置在所述载体(3)上，使得在放置之后并且在挤压期间将连接介质层(70)布置在底侧(1b)和所述载体(3)之间。
14.根据权利要求13所述的方法，其中，所述连接介质层(70)
具有焊料并且在挤压期间被加热到比所述焊料的熔点高的温度；或者
具有金属粉末并且在挤压期间被加热到比使所述金属粉末烧结的温度高的温度。
15.根据权利要求13或14所述的方法，其中，在将所述半导体芯片(100)放置在所述载体(3)上之前，将所述连接介质层(70)施加到所述底侧(1b)上或者施加到所述载体(3)上；或者
在将所述半导体芯片(100)放置在所述载体(3)上之前，将第一连接介质子层施加到所述底侧(1b)上，并且将第二连接介质子层施加到所述载体(3)上，其中，通过将所述半导体芯片(100)放置在所述载体(3)上使所述第一连接介质子层和所述第二连接介质子层结合成所述连接介质层(70)。
16.根据权利要求13或14所述的方法，其中，间接地通过所述连接介质层(70)实施将所述半导体芯片(100)压到所述载体(3)上。
17.根据权利要求13或14所述的方法，其中，在将所述半导体芯片(100)压到所述载体(3)上期间，所述连接介质层(70)连续地从所述底侧(1b)延伸到所述载体(3)上。
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