CN106340277B - Greyscale pixel shake realization device, method and liquid crystal display device based on FPGA - Google Patents
Greyscale pixel shake realization device, method and liquid crystal display device based on FPGA Download PDFInfo
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- CN106340277B CN106340277B CN201610784907.0A CN201610784907A CN106340277B CN 106340277 B CN106340277 B CN 106340277B CN 201610784907 A CN201610784907 A CN 201610784907A CN 106340277 B CN106340277 B CN 106340277B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
Abstract
The present invention relates to a kind of, and the greyscale pixel based on FPGA shakes realization device, including top-level logic encapsulation unit, AXI4Lite Interconnect internal bus interconnection module and control unit；Top-level logic encapsulation unit is for carrying out sub-pixel spatial jitter and the control of frame speed；AXI4Lite Interconnect internal bus interconnection module will be for that will have different clock-domains, the top-level logic encapsulation unit and described control unit of different function interconnect, the present invention applies sub-pixel spatial jitter method and frame speed control method that can reconstruct 6139 grades of grayscale gradation levels simultaneously, its occupied programmable logic resource of IP way of realization is seldom, this controller can be realized up in different FPGA programmable logic platforms, and it is expanded on piece SOC system abundant by the AXI protocol interconnection interface of standard, it is particularly suitable for showing in product in liquid crystal display and promotes the use of.
Description
Technical field
The present invention relates to technical field of liquid crystal display more particularly to a kind of greyscale pixel shake based on FPGA to realize dress
It sets, method and liquid crystal display device.
Background technique
In the display product of single color LCD screen application, single color LCD screen generally also has as color LCD screen
Sub-pixel combinations mode, as shown in Figure 1.With digital visual interface (Digital Visual Interface, DVI) or
In the liquid crystal display of rgb video interface, 24-bit rgb pixel encapsulation format, each sub-pixel colors locating depth are usually all used
For 8-bit.For RGB color degree space, only when R, G, B color component are equal, it can just synthesize and show as grayscale color.So 8-
Bit display system, either colored or single colour liquid crystal display, usually only has 256 grades of grayscale tones.
However in diagnosis medical LCD product, must be requested that the display brightness gradient that medical display is presented
Defer to the GSDF curve of DICOM PART#14 standard.When the display brightness range of a display is in 0~500cd/m2, according to
The GSDF curve standard of DICOM PART#14, at least 705 grades of identifiable brightness degrees of human eye (JND) are referred to defer to.
If JND STEP requirement≤| 1 |, then display at least needs to have 705 grades of display greyscale levels.Therefore, generic liquid crystal is aobvious
Show that 256 grades of grayscale tone characteristics of device are unable to satisfy medical display for display brightness grade quantity and GSDF curve performance
Requirement, and then using general liquid crystal display observation DCM medicine mating plate image when, very multifocal details is possible to present
It does not come out.If doctor diagnoses on such liquid crystal display, it is more likely that cause mistaken diagnosis or fail to pinpoint a disease in diagnosis.
Currently, ability is presented in order to improve the grayscale of liquid crystal display in many Professional display monitor manufacturers, generally use
10-bit single color LCD screen, has become one of standard configuration component of industry medical display.It, can will be grey using 10-bit liquid crystal display
Rank display brightness gradient is promoted to 1024 grades, and for 256 grades of grayscale gradients of more common 8-bit liquid crystal display, grayscale shows bright
Degree gradation levels have larger promotion.By taking the special medical single color LCD screen of certain liquid crystal display panel manufacturers as an example, center is bright
Degree is maximum up to 800cd/m2, contrast 1000, the sub-pixel drive signals of 10-bit coding, therefore can at least be presented 1000
Multistage gray-scale intensity gradient.As shown in Fig. 2, according to the data that liquid crystal display manufacturer provides, 1024 grades of grayscale gradation levels are only accounted for
Can display brightness range high 90% brightness range.Due to the inherent characteristic of TFT-LCD liquid crystal display, 10% or less brightness range
Low-light level is not have contributive to grayscale presentation, therefore 1024 grades of gray-scale intensity gradients will also give a discount, and about 920 ranks are left
It is right.According to the GSDF curve definitions of DICOM PART#14, for 800cd/m3 maximum brightness, there are 766 grades of JND gray-scale intensities
Gradient.Therefore medical display if you need to reach JND Step≤| 1 | or higher precision JND Step≤| 0.5 |, then need more
More gray-scale intensity gradients.
Summary of the invention
Medical display is unable to satisfy for display brightness number of degrees for the grayscale tone characteristic of available liquid crystal display
The defect of the requirement of amount and GSDF curve performance, the present invention propose a kind of greyscale pixel shake realization device based on FPGA,
Including top-level logic encapsulation unit, AXI4Lite Interconnect internal bus interconnection module and control unit；
The top-level logic encapsulation unit is for carrying out sub-pixel spatial jitter and the control of frame speed；
The AXI4Lite Interconnect internal bus interconnection module will be for that will have different clock-domains, different function
The top-level logic encapsulation unit and described control unit of energy interconnect.
Optionally, the top-level logic encapsulation unit includes:
Sub-pixel spatial jitter module, frame speed control module, AXI4Lite bus inferface protocol module and register mould
Block；
The sub-pixel spatial jitter module for realizing sub-pixel sequential combination arrangement mode；
The frame speed control module is used to rebuild grayscale gradient by the refresh rate of control video frame；
The AXI4Lite bus inferface protocol module is used to convert internal deposit for AMBA AXI4Lite standard agreement
Device read-write interface agreement；
The register cell is the register array unit being made of multidigit trigger, for storing preset realization
Pixel space dither method, frame speed control method function control parameter.
Optionally, the top-level logic encapsulation unit further includes the interface interconnected for each intermodule.
Optionally, described device further includes supporting peripheral module/component of AXI4Lite bus inferface protocol.
Optionally, the frame speed control module specifically uses two frame video frame speed control methods, to pass through two frame video frames
Alternately display to rebuild grayscale gradient.
Optionally, described control unit is system on chip SOC.
Optionally, described control unit is processor.
Optionally, described control unit further include:
C function drives library unit, for all control commands to be embodied as to the driving of C function.
On the other hand, the present invention also provides a kind of sides that greyscale pixel shake is realized using any of the above-described kind of described device
Method, comprising:
The mapping on display drive signals is carried out according to lookup table technology；
Corresponding data bit width is configured for the look-up table；
The output end of greyscale pixel shake realization device is connected with corresponding liquid crystal display.
On the other hand, the present invention also provides a kind of liquid crystal display devices, the grayscale including any of the above-described kind based on FPGA
Pixels dithers realization device.
Greyscale pixel based on FPGA of the invention shakes realization device, including top-level logic encapsulation unit, AXI4Lite
Interconnect internal bus interconnection module and control unit；The top-level logic encapsulation unit is for carrying out sub-pixel sky
Jitter and the control of frame speed；The AXI4Lite Interconnect internal bus interconnection module will be for when will have different
Clock domain, the top-level logic encapsulation unit of different function and described control unit interconnect, and the present invention applies sub-pixel empty simultaneously
Jitter method and frame speed control method can reconstruct 6139 grades of grayscale gradation levels, and IP way of realization is occupied to be compiled
Journey logical resource is seldom, can by this controller, (including CPLD) goes to realize on different FPGA programmable logic platforms, and
It is expanded on piece SOC system abundant by the AXI protocol interconnection interface of standard, is particularly suitable for showing product in liquid crystal display
Middle popularization and use.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is color LCD screen in the prior art, single color LCD screen image element composition and structural schematic diagram；
Fig. 2 is the grayscale gradient and brightness degree correspondence diagram of 10-bit liquid crystal display in the prior art；
Fig. 3 is symmetric form sub-pixel structure in the prior art, asymmetric sub-pixel structure schematic diagram；
Fig. 4 is that the realization principle of the sub-pixel spatial dithering technique reconstruction grayscale tone gradient of one embodiment of the invention is shown
It is intended to；
Fig. 5 is that the frame speed control technology of one embodiment of the invention rebuilds the realization principle schematic diagram of grayscale tone gradient；
Fig. 6 is that the greyscale pixel based on FPGA of one embodiment of the invention shakes the structural schematic diagram of realization device；
Fig. 7 is the fusant pixel space dither technique of one embodiment of the invention, frame speed control technology reconstruction grayscale color
Adjust the schematic illustration of gradient.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical solution in the embodiment of the present invention is explicitly described, it is clear that described embodiment is the present invention
A part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not having
Every other embodiment obtained under the premise of creative work is made, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a kind of low cost, it can independently realize, repeat, cross-platform can transplant, IP can be encapsulated
On common liquid crystals screen rebuild greater number grayscale tone technical solution.Generally speaking, the embodiment of the present invention is based on to compile
Cheng Yuyan Verilog executes a logic module on FPGA programmable logic resource platform, which mainly includes sub-pixel
Spatial jitter module, frame speed control module.
As shown in figure 3, the structure of single color LCD screen sub-pixel can classify are as follows: symmetrically type dot structure and non-homogeneous
Symmetric form dot structure.
For non-uniformity type dot structure, since the bore size scale of each sub-pixel is different, so often
Sub-pixel is different to the brightness contribution of whole pixel, and then can produce more sub-pixel permutation and combination codings, can pass through
It rebuilds orderly arrangement of subpixels combination and produces greater number of pixel gray level gradient.
And for symmetrically type dot structure, since the bore size scale of each sub-pixel is identical, so often
A sub-pixel is identical to the brightness contribution of whole pixel, i.e., hypothesis sub-pixel luminence meets bright between normal distribution and sub-pixel
Degree is independent of each other, their arrangement of subpixels assembly coding only has 3 kinds: such as { 0,0,1 }, { 0,1,0 }, { 1,0,0 } three seed picture
Plain arrangement mode, actually these three sub-pixel groups at pixel brightness level be the same.External some medical display systems
The liquid crystal display that quotient mostly uses non-uniformity type pixel interface is made, and then more tendencies select symmetrically type to domestic medical display
The liquid crystal display of pixel interface, because its manufacturing process and color LCD screen are essentially the same, unique difference is that single color LCD screen does not have
There is color filter film.
The sub-pixel spatial jitter implementation method of the embodiment of the present invention is based on the liquid crystal with symmetrically type dot structure
Panel plate, by carrying out reconstruction combination, arrangement, it can be achieved that more show grayscale to three sub-pixels, each liquid crystal pixel
Sub-pixel driving data is rearranged in serial code front end, combines, and it is more to reconstruct a set of gray number more intrinsic than liquid crystal display
Gray-scale intensity gradation levels.As shown in figure 4, the sub-pixel spatial jitter method using the present embodiment can be in 10-bit liquid crystal
Shield and reconstructs 3070 grades of grayscale gradients on the basis of intrinsic pixel gray level characteristic.
Further, display dither technique of the frame speed control method of the present embodiment based on timeline.Display number at present
60Hz is all reached according to the refresh rate of frame, when data frame speed is up to 120Hz, 200Hz, human eye can will not discover flashing completely
Feel, critical flicker frequency (CFF) is greater than 30Hz or so in fact, and human eye also can not experience the feeling of flashing substantially.Therefore exist
It is controlled on the refresh rate basis of 60Hz using frame speed, using the visual response time difference of human eye, data frame can be reconstructed and melted
The effect of conjunction can reconstruct new grayscale gradient.As shown in figure 5, the frame speed control method using the present embodiment can be in 10-
2047 grades of grayscale gradients are reconstructed on the basis of the intrinsic pixel gray level characteristic of bit liquid crystal display.
The present invention is illustrated with a specific embodiment below, but the scope of protection of the present invention is not limited.
Fig. 6 shows the greyscale pixel shake realization device schematic diagram based on FPGA of one embodiment of the invention, such as Fig. 6
Shown, which includes:
It is total to encapsulate sub-pixel spatial jitter module 2, frame speed control module 3, AXI4Lite for top-level logic encapsulation unit 1
The interface inter-link of line interface protocol module 4, register module 5 and intermodule, in which:
Sub-pixel spatial jitter unit 2 realizes the sequential combination arrangement mode of sub-pixel, as shown in figure 4, the first order is sub
Combination of pixels arrangement mode is fairly simple, only includes the 1st grade of 0 grayscale gradient；2nd grade of sub-pixel combinations arrangement mode includes three
Kind, it is made of the 2nd grade of grayscale gradient 1 and the 1st grade of grayscale gradient 0, i.e. Pattern { 0,1,0 }, Pattern { 1,0,1 } with
And Pattern { 1,1,1 }；The 1023rd grade of grayscale gradient, i.e. Pattern of 10-bit liquid crystal display are iterated to according to above-mentioned rule
{1022,1023,1022},Pattern{1023,1022,1023}, Pattern{1023,1023,1023}.By calculating, son
Pixel space dither technique can reconstruct 3070 grades of grayscale gradation levels.
Frame speed control unit 3 achievees the purpose that rebuild grayscale gradient by controlling the refresh rate of video frame.This implementation
2 frame video frame speed control methods are used in example, i.e., grayscale gradient are rebuild by alternately displaying for two frame video frames.
For grayscale gradient 0, frame speed control it is fairly simple, every frame refreshing be all grayscale gradient 0 data；
For grayscale gradient 1, there are two types of data frame refreshing modes, the i.e. data of 1/60 frame refreshing grayscale gradient 1, same with this
When 2/60 frame refreshing grayscale gradient 1 data, other moment all refresh the data of upper level grayscale gradient 0, can thus make
The delayed mixures effect that grayscale gradient 0 and grayscale gradient 1 are experienced in human eye has reconstructed two kinds of new grayscale gradation levels.
The 1023rd grade of grayscale gradient of 10-bit liquid crystal display is iterated to by above-mentioned rule, i.e., also there are two types of data frame refreshings
Mode, the data of 1/60 frame refreshing grayscale 1023 grades of grayscale gradients of gradient, the data of 1/60 frame refreshing grayscale gradient 1023 are simultaneously
The data of 2/60 frame refreshing grayscale gradient 1023, other moment all refresh the data of upper level grayscale gradient 1022, make one in this way
Eye experiences the delayed mixures effect of grayscale gradient 1022 and grayscale gradient 1023, has gone out two kinds of new grayscale gradients etc. again
Grade.
By calculating, 2047 grades of grayscale gradation levels can be reconstructed using the frame speed control technology of the present embodiment.
AXI4Lite bus inferface protocol module 4, for converting internal register for AMBA AXI4Lite standard agreement
Read-write interface agreement；
Wherein, AXI4Lite agreement is that support Burst mode, independent data/address/response channel bus connect
Mouthful, for the Intercommunication between processor and peripheral equipment.
This can be realized that the module of greyscale pixel dither method extends to industry abundant by AXI4Lite interface
Upper system SOC processor platform.
Register cell 5 realizes that sub-pixel is empty for storing for the register array unit being made of multidigit trigger
Jitter method, the function control parameter of frame speed control method；
The control to algorithm function module is realized by the control to register.
It further, further include the peripheral module/component 6 and AXI4Lite for supporting AXI4Lite bus inferface protocol
Interconnect internal bus interconnection module 7；
It can be by different clock-domains, different function by AXI4Lite Interconnect internal bus interconnection module 7
Module and control unit (system on chip SOC or processor) interconnect.
In addition, the device further includes the system on chip SOC or processor unit 8 with control function, as shown in fig. 6, its
In with control function system on chip SOC or processor unit 8 further include:
C function drives library unit 9 to make the register stage of module for all control commands to be embodied as to the driving of C function
Control is converted into the device instance being best understood from, C function operation, and can be applied to support any system on chip of C compiler
SOC or processor platform.
Further, the present embodiment is using the greyscale pixel shake realization device realization based on FPGA based on FPGA grayscale
Pixels dithers implementation method, including following workflow:
1) corresponding lookup table technology is combined to carry out the mapping on display drive signals；
Specifically, it first has to configure suitable look-up table address locating depth.For example, driving signal data bit width is compatible
8-bit, 10-bit display system, look-up table address locating depth can be configured to 8-bit, 10-bit；
2) the suitable data bit width of look-up table is configured, specifically:
When only applying sub-pixel spatial dithering technique, look-up table data bit wide can be configured to 12-bit；
When only applying frame speed control technology, look-up table data bit wide can be configured to 11-bit；
When applying sub-pixel spatial dithering technique and frame speed control technology simultaneously, look-up table data bit wide be can be configured to
13-bit；
3) method for realizing greyscale pixel shake of the present embodiment, is encoded, therefore output end with 10-bit data pixels
It needs to be connected to 10-bit liquid crystal display just and can reach corresponding effect.If system display component is 8-bit liquid crystal display, need to increase
Add corresponding data carry/shortening algorithm elder generation Dither to 8-bit data, reconnects corresponding liquid crystal display.
Greyscale pixel of the present invention based on FPGA shakes realization device, while applying sub-pixel spatial jitter method
6139 grades of grayscale gradation levels can be reconstructed with frame speed control method, as shown in annex Fig. 7；Its IP way of realization is occupied
Programmable logic resource is seldom, can (including CPLD) goes reality on different FPGA programmable logic platforms by this controller
It is existing；It is expanded on piece SOC system abundant by the AXI protocol interconnection interface of standard, is particularly suitable for showing production in liquid crystal display
It is promoted the use of in product.
The above examples are only used to illustrate the technical scheme of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these are modified or replace
It changes, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (9)
1. a kind of greyscale pixel based on FPGA shakes realization device, which is characterized in that including top-level logic encapsulation unit,
AXI4Lite Interconnect internal bus interconnection module and control unit；
The top-level logic encapsulation unit is for carrying out sub-pixel spatial jitter and the control of frame speed；
The AXI4Lite Interconnect internal bus interconnection module is used to have different clock-domains, different function
The top-level logic encapsulation unit and described control unit interconnect；
Wherein, the top-level logic encapsulation unit includes:
Sub-pixel spatial jitter module, frame speed control module, AXI4Lite bus inferface protocol module and register module；
The sub-pixel spatial jitter module for realizing sub-pixel sequential combination arrangement mode；Sub-pixel combinations mode packet
It includes: only including the 1st grade of 0 grayscale gradient for the 1st grade of sub-pixel combinations arrangement mode；When n is greater than 1, picture for n-th grade
Plain assembled arrangement mode includes n-th grade of grayscale gradient and (n-1)th grade of grayscale gradient；
The frame speed control module is used to rebuild grayscale gradient by the refresh rate of control video frame；
The AXI4Lite bus inferface protocol module is used to convert AMBA AXI4Lite standard agreement to internal register and read
Write interface protocol；
The register module is the register array unit being made of multidigit trigger, for storing preset realization sub-pixel
Spatial jitter method, frame speed control method function control parameter；
For grayscale gradient 0, the data of every frame refreshing grayscale gradient 0；When n is greater than 0, for grayscale gradient n, 1/60 frame refreshing
The data of grayscale gradient n, the data of 2/60 frame refreshing grayscale gradient n, other moment all refresh grayscale gradient n-1's at the same time
Data.
2. the apparatus according to claim 1, which is characterized in that the top-level logic encapsulation unit further includes for each module
Between the interface that is interconnected.
3. the apparatus according to claim 1, which is characterized in that described device further includes supporting AXI4Lite bus interface association
Peripheral module/component of view.
4. the apparatus according to claim 1, which is characterized in that the frame speed control module specifically uses two frame video frame speed
Control method, to rebuild grayscale gradient by alternately displaying for two frame video frames.
5. the apparatus according to claim 1, which is characterized in that described control unit is system on chip SOC.
6. the apparatus according to claim 1, which is characterized in that described control unit is processor.
7. device according to claim 5 or 6, which is characterized in that described control unit further include:
C function drives library unit, for all control commands to be embodied as to the driving of C function.
8. a kind of method for realizing greyscale pixel shake using any one of claim 1-7 described device, which is characterized in that packet
It includes:
The mapping on display drive signals is carried out according to lookup table technology；
Corresponding data bit width is configured for the look-up table；
The output end of greyscale pixel shake realization device is connected with corresponding liquid crystal display.
9. a kind of liquid crystal display device, which is characterized in that including the described in any item grayscale pictures based on FPGA of claim 1-7
Element shake realization device.
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| CN203288223U (en) * | 2013-03-04 | 2013-11-13 | 南京巨鲨显示科技有限公司 | Display with gray scale expansion function |
| CN104392424A (en) * | 2014-11-30 | 2015-03-04 | 南京巨鲨显示科技有限公司 | Method and system for contrast adaption of professional gray-scale image |
| CN105513558A (en) * | 2015-09-26 | 2016-04-20 | 南京巨鲨显示科技有限公司 | Superhigh bit width image enhancement display device and method for medical professional display |
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| CN203288223U (en) * | 2013-03-04 | 2013-11-13 | 南京巨鲨显示科技有限公司 | Display with gray scale expansion function |
| CN104392424A (en) * | 2014-11-30 | 2015-03-04 | 南京巨鲨显示科技有限公司 | Method and system for contrast adaption of professional gray-scale image |
| CN105513558A (en) * | 2015-09-26 | 2016-04-20 | 南京巨鲨显示科技有限公司 | Superhigh bit width image enhancement display device and method for medical professional display |
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