CN200947341Y - Display controller for producing multiple light-shade level image - Google Patents
Display controller for producing multiple light-shade level image Download PDFInfo
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- CN200947341Y CN200947341Y CN 200320130438 CN200320130438U CN200947341Y CN 200947341 Y CN200947341 Y CN 200947341Y CN 200320130438 CN200320130438 CN 200320130438 CN 200320130438 U CN200320130438 U CN 200320130438U CN 200947341 Y CN200947341 Y CN 200947341Y
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Abstract
The utility model relates to a displaying controller which through a plurality of continuous frames generates an image which has the multi-ply light-and-shade levels and is displayed on a displaying device which is composed of a plurality of binary image-elements in array. The displaying controller comprises an image memorizer, a light-and-shade level data is provided for each image element. A selective signal of the wave pattern is sent out from a wave pattern selector, and two different groups of wave pattern signals corresponding to any neighboring two sub-image elements are provided by a wave pattern memorizer. The frame speed-rate of the multi continuous-frame is designed to be high enough so as to avoid the vision-interference.
Description
Technical field
The utility model relates to a kind of display controller, relates in particular to a kind of display controller that can produce the multiple shade of grey (Multi-Gradation) image on the display device of being made up of the binary condition pixel.
Prior art
The digital control type display device typically refers to a kind of optoelectronic device of being made up of as the basic luminaire unit a plurality of pixels (Pixel), and wherein each pixel is subjected to digital electronic signal control and switching between binary condition ON and OFF (or claim bright with secretly).Pixel as the basic luminaire unit can be emission-type, transmission-type or reflective.The example of this digital control type display device is liquid crystal indicator, light emitting display device or electric plasma display device or the like.
Since pixel only can represent binary condition ON and OFF one of them, so if will be on the display device of being formed by the binary condition pixel (hereinafter referred binary display device) the multiple shade of grey image of generation, then must utilize or develop special display technique.For example, the analog-modulated technology provides a plurality of pixels with driving voltage of different intermediate level (level) to the binary display device, makes it to be in incomplete ON/OFF state, the demonstration of reaching the multiple shade of grey therefrom.The shortcoming of this analog-modulated technology is to need complicated driver.
Another kind of prior art is a pulse width modulating technology, the low-pass filtering effectiveness that it is controlled the binary condition ON and the working cycle between OFF (Duty Cycle) of pixel and utilizes human eye, the perception of reaching the multiple shade of grey therefrom.The shortcoming of this pulse width modulating technology is to need complicated driver and complicated control algolithm.
Another prior art is the frame rate modulation technique, and its principle is similar to pulse width modulating technology, and difference is to cause by the continuous demonstration of a plurality of frames the perception of the multiple shade of grey.The shortcoming of this frame rate modulation technique is normal perceived in the shown image flicker to be arranged.
Another prior art is shake (Dithering) technology, and it utilizes the flicker in the shown image of dither matrix elimination.Yet this dither technique needs complicated control algolithm and circuit and causes the generation of striped or sacrificed quantity of information.
Summary of the invention
Because foregoing problems, the purpose of this utility model is to provide a kind of display controller, can produce multiple shade of grey image on the display device of being made up of the binary condition pixel.
Via a plurality of successive frames, a display controller produces a width of cloth and has the image of the multiple shade of grey on a display device of being made up of with array way a plurality of binary condition pixels.These a plurality of pixels are distinguished into a plurality of sub-pixel groups with same size.This display controller comprises a video memory, provides a shade of grey data for each pixel.These shade of grey data are in order to indicate the shade of grey color range (level) on the pixel that will result from an expectation.One waveform patterns storer provides many group waveform patterns signals to this display device.Each group in these many group waveform patterns signals have the waveform patterns signal of similar number.Each waveform patterns signal has the position of a predetermined number and produce a different shade of grey color range when being applied to a pixel.Each is to be used in the frame of the correspondence in these a plurality of successive frames to show.One waveform patterns selector switch is exported a waveform patterns and is selected signal, and this waveform patterns storer be you can well imagine for two groups of waveform patterns signals inequality for two adjacent sub-pixel components.These two groups of waveform patterns signals inequality are configured to make these two adjacent sub-pixel groups to be in the state that differs from one another at least one frame of these a plurality of successive frames.This waveform patterns memory response is selected signal and is determined to provide one in these many group waveform patterns signals to select group in waveform patterns, determine to provide one in this selected group waveform patterns signal to select the waveform patterns signal in response to these shade of grey data, and the position of the correspondence of this selected waveform patterns signal is provided in regular turn according to the carrying out of these a plurality of successive frames.The frame rate of these a plurality of successive frames is configured to enough high to avoid vision to disturb.
Preferably, this frame rate is more than or equal to (2
n* 15) Hz.
Preferably, this waveform patterns storer provides two groups of waveform patterns signals to this display device.This waveform patterns selector switch is exported this waveform patterns and is selected signal in response to a least significant bit (LSB) of one of this line number order least significant bit (LSB) and this column number.This waveform patterns memory storage has a group in these two groups of waveform patterns signals, and uses this waveform patterns to select signal to produce another group waveform patterns signal from this group.
Preferably, this display device is a colour display device.
Description of drawings
Fig. 1 shows the synoptic diagram of the binary display device of being made up of the binary condition pel array.
Fig. 2 is presented on the binary display device by 2
nIndividual frame produces a width of cloth and has 2
nThe synoptic diagram of the image of the rank shade of grey.
Each pixel vertical and horizontal ground alternately receives the synoptic diagram of two groups of different waveform patterns signals in Fig. 3 (a) demonstration binary display device.
Fig. 3 (b) shows the synoptic diagram of the some possible space pattern of any 2 * 2 pel array in a frame in the binary display device.
Fig. 4 (a) and the sequential chart of 4 (b) demonstration by an example of foundation two groups of waveform patterns signals that display controller of the present utility model provided.
Fig. 5 (a) and the circuit blocks figure of 5 (b) demonstration according to display controller of the present utility model.
Fig. 6 (a) is to the synoptic diagram of 6 (c) display application colour display device of the present utility model.
Embodiment
As previously mentioned, prior art all has various shortcomings for produce multiple shade of grey image on the binary display device.Yet, except producing multiple shade of grey image effectively on the binary display device, also provide following advantage according to display controller of the present utility model: control algolithm, (3) vision that implement easily (1) simple circuit configurations, (2) disturbed the lifting of making full use of of the avoiding of (for example flicker or striped), (4) quantity of information and (5) digital image signal process aiming speed.Thereby, control the binary display device according to the control algolithm that display controller utilization of the present utility model is implemented easily, under the situation of loss of information amount not, reach the even and estriate multiple shade of grey, and directly avoided the phenomenon of flicker according to the characteristic of human eye perception.
Explanation hereinafter and accompanying drawing will make aforementioned and other purpose of the present utility model, feature, more obvious with advantage.Here describe in detail according to preferred embodiment of the present utility model with reference to the accompanying drawings.
With reference to Fig. 1, a binary display device 10 is made up of 240 * 160 binary condition pixels, and these pixels are arranged in has 240 row and 160 arrays that are listed as.Be of a size of 240 * 160 though note that binary display device 10 shown in Figure 1, the utility model is not limited thereto example, but can be applicable to have the binary display device of arbitrary dimension.In order on binary display device 10, to produce multiple shade of grey image, the image segmentation that one width of cloth can be had the multiple shade of grey becomes a plurality of frames (Frame) that equally spaced show in time, and wherein the demonstration of each frame can be set a plurality of pixels in the binary display device respectively one of in binary condition ON/OFF and realize according to specific space pattern.As a result, under time/spatial integration (integration) effect effect of human eye vision, can perceive multiple shade of grey image from the binary display device effectively.
Suppose that on binary display device 10 operation shows a series ofly have 2
nThe image of the rank shade of grey (n is a positive integer).As shown in Figure 2, each 2
nRank shade of grey image is by 2
nIndividual frame is formed, wherein between consecutive frame across a fixing frame period.Constituting last 2
nThe 2nd of rank shade of grey image
nThrough this fixing frame period, next was 2 years old after frame showed
nThe 1st frame of rank shade of grey image promptly demonstrates.In other words, be manipulated on the binary display device 10 with a fixing frame rate display frame, wherein per 2
nThe combination of individual frame can make human eye perceive a width of cloth to have 2
nThe image of the rank shade of grey.Particularly, for the time of utilizing human eye vision is integrated effect, frame rate must have a sizable value.In principle, the big frame rate that heals, the time that more is of value to human eye vision is integrated the utilization of effect, and then produces high-quality multiple shade of grey image.The frame rate that prior art adopted is approximately 50 to 120Hz, perhaps still can demonstrate good 2 when n≤2 under the situation that does not cause flicker
nRank shade of grey image.Yet when n 〉=3, prior art must adopt complicated control algolithm or dither matrix remedying the low excessively defective of frame rate, otherwise can't avoid flicker.
In a foundation preferred embodiment of the present utility model, frame rate is set for more than or equal to (2
n* 15) Hz.With this understanding, because each 2
nRank shade of grey image has 2
nSo individual frame is adjacent two 2
nThe demonstration speed of wantonly two frames with same number of frames sequence number in the shade of grey image of rank is more than or equal to 15Hz (that is per 2
nThe individual frame period occurs once).In foundation other embodiment of the present utility model, preferable frame rate also can and be determined via Computer Simulation or actual test, can avoid human eye to perceive scintillation as long as frame rate is enough high.
In order to utilize the spatial integration effect of human eye vision, provide two groups of different waveform patterns signals for the mode that each pixel of binary display device 10 all replaces with vertical and horizontal according to display controller of the present utility model.Particularly, shown in Fig. 3 (a), one 2 * 2 basic pixel cells 30 comprise four pixels, and two pixels that wherein are positioned on the diagonal line are positioned at two pixels on another diagonal line then in order to receive second group of waveform patterns signal WP2 in order to receive first group of waveform patterns signal WP1.In the utility model, second group of waveform patterns signal WP2 is designed to be different from first group of waveform patterns signal WP1, will describe in detail subsequently.Refer back to Fig. 1, binary display device 10 can be considered by 2 * 2 basic pixel cells 30 shown in a plurality of Fig. 3 (a) to be formed.As a result, the pixel that is marked with symbol I is being represented in order to receive the pixel of first group of waveform patterns signal WP1, and unmarked blank pixel is then being represented in order to receive the pixel of second group of waveform patterns signal WP2.Therefore, two the adjacent pixels on the binary display device 10 no matter be vertical adjacent or level is adjacent, are receiving two groups of waveform patterns signal WP1 inequality and WP2.
Fig. 3 (b) shows the synoptic diagram of the some possible space pattern A to H of any 2 * 2 pel array in a frame in the binary display device 10.In Fig. 3 (b), on behalf of it, the pixel that is marked with empty circles be in ON state (or claiming bright state) in the binary condition, and on behalf of it, the pixel that is marked with solid circles then be in OFF state (or claiming dark state) in the binary condition.In the utility model, provide respectively to the two groups of waveform patterns signal WP1 inequality and the WP2 of two adjacent pixels of binary display device 10 to be configured to make these two adjacent pixels 2
nBe in the mode of operation that differs from one another at least one frame of individual frame, for example space pattern A or the B among Fig. 3 (b).In other words, staggered effect spatially takes place in the mode of operation of two adjacent pixels.As a result, the switching rate that can perceive the binary condition pixel under the spatial integration effect of human eye vision has increased by one times.By this mode, be configured to more than or equal to (2 in aforementioned frame rate
n* 15) in the preferred embodiment of Hz, even have a pixel in the binary display device 10 2
nOnly switch once in the individual frame, the switching rate that human eye perceived is still more than or equal to 30Hz.Therefore according to display controller of the present utility model more positively avoid glimmering generation with striped.
Fig. 4 (a) and 4 (b) show by the sequential chart according to the example of display controller of the present utility model provided two groups of waveform patterns signal WP1 and WP2.Two groups of waveform patterns signal WP1 that Fig. 4 (a) and 4 (b) are provided have all extended 32 frames with WP2, therefore can be used to demonstration and have 2
5The image of (=32) rank shade of grey.In Fig. 4 (a) and 4 (b), m rank waveform patterns signal is designed to have pulse in m the frame in 32 frames and does not have pulse in all the other (32-m) individual frame.With regard to the waveform patterns signal of corresponding m rank, though first and second group waveform patterns signal WP1 and WP2 have m pulse all respectively, both differences are the distribution of pulse in whole 32 frame periods.As previously mentioned, waveform patterns signal WP1 and WP2 are configured to make two adjacent pixels 2
nBe in the mode of operation that differs from one another at least one frame of individual frame.By the design of this different distribution of pulses, can utilize human eye vision time/spatial integration effect and reaching makes the perceived effect of pixel switching rate multiplication.Fig. 4 (a) also must be considered to a digit order number sequence (digital bit sequence) with the waveform patterns signal WP1 shown in 4 (b) and each signal among the WP2 or be implemented by it.For example, the 22nd rank signal of first group of waveform patterns signal is [11111001111001111100111100111100], and its meta 1 representative has pulse position 0 then to represent no pulse.Each is to be used in the frame of the correspondence in these a plurality of successive frames to show.Because each has binary condition, so quite be fit to be used for controlling the operation of binary condition pixel.
Please note, in Fig. 4 (a) and 4 (b), only show the 16th rank to the 32 rank signals among first and second group waveform patterns signal WP1 and the WP2, because the 1st to 15 rank signal is designed to the complement code (complement) or the inversion signal of the 31st to 17 rank signal in this embodiment, it is graphic so omit.According among another embodiment of the present utility model, the 1st rank signal also can be designed to neitherly in whole 32 frame periods have a pulse.
Though two groups of waveform patterns signal WP1 shown in Fig. 4 (a) and 4 (b) and WP2 are in order to show 32 rank shade of grey images in the aforementioned embodiment, but being not limited thereto example, the utility model can be applicable to from each group of two groups of waveform patterns signal WP1 and WP2, select corresponding 16 waveform patterns signals respectively, in order to show 16 rank shade of grey images.In like manner, the utility model also can be applicable to select corresponding 8 waveform patterns signals respectively from each group of two groups of waveform patterns signal WP1 and WP2, in order to show 8 rank shade of grey images.
Here with reference to Fig. 5 (a) and 5 (b) circuit configurations and the operation thereof that produces the foundation display controller 51 of the present utility model of multiple shade of grey image on display device 50 is described.With reference to Fig. 5 (a), display controller 51 of the present invention includes pixel counter 53, sweep trace counter 54, video memory 52, waveform patterns selector switch 57 and waveform patterns storer 56.Wherein the output terminal of pixel counter 53 and sweep trace counter 54 all is connected to the input end of video memory 52 and waveform patterns selector switch 57; The output terminal of waveform patterns selector switch 57 and video memory 52 all is connected to the input end of waveform patterns storer 56; The output terminal of waveform patterns storer 56 is connected to the input end of display device 50.Video memory 52 stores shade of grey data, the shade of grey color range of each pixel in the binary pixel array of this shade of grey data indication formation display device 50.The line number order signal CN that video memory 52 is exported by pixel counter 53 and make the address of desiring access by the column number signal RN that sweep trace counter 54 is exported.Pixel counter 53 uses pixel clock PCK and sweep trace clock SLCK as clock signal respectively with sweep trace counter 54.In response to line number order signal CN and column number signal RN, video memory 52 outputs will be shown in by the shade of grey data GD on the pixel of line number order signal CN and the addressing of column number signal RN institute.Though shade of grey data GD can directly import waveform pattern memory 56, in a foundation preferred embodiment of the present utility model, shade of grey data GD imports waveform pattern memory 56 via look-up table (Look Up Table) 55.The function of look-up table 55 generally includes the bits number that increases shade of grey data GD, shade of grey data GD is carried out gamma (Gamma) revises or other similar calculation, so as to strengthening the quality of the image that will show.Conversion back shade of grey data GD ' inputs to waveform patterns storer 56 from look-up table 55.Waveform patterns storer 56 stores the digit order number sequence of predetermined number, and it is corresponding to foundation waveform patterns signal of the present utility model, for example the waveform patterns signal shown in Fig. 4 (a) and 4 (b).
On the other hand, waveform patterns selector switch 57 is based on line number order signal CN and the column number signal RN in order to the definite pixel address that are received, according to the output waveform pattern selects signal WS to waveform patterns storer 56 according to the waveform patterns system for delivering shown in Fig. 3 of the present utility model (a), in order to determine to use first group or second group of waveform patterns signal.Simultaneously, frame counter 58 under the operation of frame clock FCK output frame number signal FN to waveform patterns storer 56.Select signal WS and frame number signal FN in response to conversion back shade of grey data GD ', waveform patterns, waveform patterns storer 56 with one time one mode in regular turn output waveform pattern signal bits WPB to binary display device 50, so as to producing multiple shade of grey image.In one embodiment, waveform patterns storer 56 can store two groups of waveform patterns signals, and selects signal WS to determine to use which group waveform patterns signal based on waveform patterns.In another embodiment, waveform patterns storer 56 can only store single group of waveform patterns signal, and selects definite directly this group waveform patterns signal of use of signal WS or derive another group waveform patterns signal from this group waveform patterns signal based on waveform patterns.For example, another group waveform patterns signal can be derived from this stored group waveform patterns signal by the mode of utilizing phase deviation.In the broadest sense, in foundation display controller of the present utility model, waveform patterns storer 56 can or be simplified the information of required storage by various rational techniques or compression algorithm, as long as it can be effectively selects signal WS and frame number signal FN and correctly export desired waveform patterns signal bits WPB based on conversion back shade of grey data GD ', waveform patterns.
The partial circuit figure of Fig. 5 (b) displayed map 5 (a) is in order to the example of explanation according to waveform patterns selector switch 57 of the present utility model.With reference to Fig. 5 (b), because in the utility model, only use two groups of waveform patterns signals and carry out the distribution of waveform patterns signal space, so waveform patterns selector switch 57 can only be implemented by an exclusive OR (Exclusive-OR) logical circuit quite simply according to 2 * 2 basic pixel cells shown in Fig. 3 (a).Particularly, mutual exclusion-or logical circuit receives the least significant bit (LSB) CNLSB of the line number order signal CN that is exported from pixel counter 53 and the least significant bit (LSB) RNLSB of the column number signal RN that exported from sweep trace counter 54.With reference to the truth table of exor computing as can be known, when two input logic values were identical, the output logic value was 0, and when two input logic values not simultaneously, the output logic value is 1.Therefore, the exor circuit can be distinguished two pairs of pixels that lay respectively in 2 * 2 basic pixel cells shown in Fig. 3 (a) on two diagonal line effectively.
In sum, only use two groups of waveform patterns signals on the binary display device, to produce according to display controller of the present utility model and have 2
nThe image of the shade of grey.Compared to the various prior aries of using very many group phase-shift signals and well-designed spatial distributed pattern or use complexity and large-sized dither matrix, can reduce the memory capacity of waveform patterns storer 56 widely and use simply constructed waveform patterns selector switch 57 to replace the spatial distributed pattern storer or the dither matrix buffer of prior art according to display controller of the present utility model, and then promote digital image signal process aiming speed greatly.
Here illustrate that to 6 (c) foundation display controller of the present utility model is applied to the example on the colour display device 60 with reference to Fig. 6 (a).With reference to Fig. 6 (a), colour display device 60 is formed by the array that a plurality of pixel constituted, wherein each pixel respectively in order to show redness (R), green (G), with blue three primary colors such as (B) in of the same colour.In colour display device 60, typically, with a red pixel (R for example
11), green pixel (G for example
11), with blue pixel (B for example
11) be arranged in and form a colour element group 61 together, in order to be combined into desired color.Though Fig. 6 (a) only shows a kind of three primary colors pixel arrangement mode of colour display device, the utility model is not limited thereto example and the colour display device that may be used on being made up of three primary colors pixel color arrangement mode miscellaneous.
Fig. 6 (b) shows that foundation display controller of the present utility model distributes first mode of two groups of waveform patterns signals to colour display device 60.In first mode, each pixel of colour display device 60 all is regarded as smallest allocation unit, no matter its color why.Therefore, the pixel of colour display device 60 is distinguished according to 2 * 2 basic pixel cells 30 of Fig. 3 (a), mat and vertical go up and level on all alternately receive two groups of waveform patterns signal WP1 and WP2.
Fig. 6 (c) shows that foundation display controller of the present utility model distributes second mode of two groups of waveform patterns signals to colour display device 60.In second mode, the colour element group 61 that is constituted by red pixel, green pixel, with blue pixel of colour display device 60 is regarded as smallest allocation unit.If four pixels in 2 * 2 basic pixel cells 30 of Fig. 3 (a) are extended to four colour element groups 61 as smallest allocation unit, just can determine according to 2 * 2 basic pixel cells 30 of Fig. 3 (a) which group waveform patterns signal is each pixel of colour display device 60 should receive easily.In the case, the colour element group 61 of colour display device 60 vertically upward and on the level all alternately receives two groups of waveform patterns signal WP1 and WP2.
Though the utility model is illustrated as illustration by preferred embodiment, will be appreciated that: the utility model is not limited to this embodiment that is disclosed.On the contrary, to be intended to contain be tangible various modification and similar configuration to the utility model for a person skilled in the art.Therefore, the scope of claim should be according to the widest annotation, and this type of is revised and similar configuration to contain all.
Claims (5)
1. display controller, has the image of the multiple shade of grey on a display device of being formed with array way by a plurality of binary condition pixels in order to produce a width of cloth via a plurality of successive frames, these a plurality of pixels are distinguished into a plurality of sub-pixel groups with same size, and this display controller comprises:
One pixel counter is in order to specify the line number order of a pixel of expecting;
The one scan thread count is in order to the column number of the pixel of specifying this expectation;
One video memory provides a shade of grey data in response to this line number order of the pixel of this expectation and this column number, and these shade of grey data will result from the shade of grey color range on the pixel of this expectation in order to indication;
One waveform patterns storer, in order to provide many group waveform patterns signals to this display device, each group in these many group waveform patterns signals have the waveform patterns signal of similar number, wherein each waveform patterns signal has the position of a predetermined number and produce a different shade of grey color range when being applied to a pixel, and wherein each is to be used in the frame of the correspondence in these a plurality of successive frames to show; And
One waveform patterns selector switch, export a waveform patterns and select signal in response to this line number order of the pixel of this expectation and this column number, make this waveform patterns storer provide in these many group waveform patterns signals two groups inequality respectively for two adjacent sub-pixel groups, wherein:
This waveform patterns memory response is selected signal and is determined to provide one in these many group waveform patterns signals to select group in waveform patterns, determine to provide one in this selected group waveform patterns signal to select the waveform patterns signal in response to these shade of grey data, and the position of the correspondence of this selected waveform patterns signal is provided in regular turn according to the carrying out of these a plurality of successive frames;
Provide respectively to these two adjacent sub-pixel groups should many group waveform patterns signals in these inequality two groups be configured to make these two adjacent sub-pixel groups at least one frame of these a plurality of successive frames, to be in the state that differs from one another; And
The frame rate of these a plurality of successive frames is configured to enough high to avoid vision to disturb.
2. display controller as claimed in claim 1, wherein:
This frame rate is more than or equal to (2
n* 15) Hz.
3. as the display controller of claim 1, wherein:
It is that a binary is selected signal that this waveform patterns is selected signal.
4. display controller as claimed in claim 1, wherein:
This waveform patterns selector switch is an exor circuit.
5. display controller as claimed in claim 1, wherein:
This display device is a colour display device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200320130438 CN200947341Y (en) | 2003-12-22 | 2003-12-22 | Display controller for producing multiple light-shade level image |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200320130438 CN200947341Y (en) | 2003-12-22 | 2003-12-22 | Display controller for producing multiple light-shade level image |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8970637B2 (en) | 2008-12-01 | 2015-03-03 | Lg Display Co., Ltd. | Unit and method of controlling frame rate and liquid crystal display device using the same |
| CN101751845B (en) * | 2008-12-01 | 2016-12-14 | 乐金显示有限公司 | Control the unit of frame per second and method and with this unit and the liquid crystal display of method |
-
2003
- 2003-12-22 CN CN 200320130438 patent/CN200947341Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8970637B2 (en) | 2008-12-01 | 2015-03-03 | Lg Display Co., Ltd. | Unit and method of controlling frame rate and liquid crystal display device using the same |
| CN101751845B (en) * | 2008-12-01 | 2016-12-14 | 乐金显示有限公司 | Control the unit of frame per second and method and with this unit and the liquid crystal display of method |
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