CN106339338B - A kind of data transmission method and device that system performance can be improved - Google Patents
A kind of data transmission method and device that system performance can be improved Download PDFInfo
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- CN106339338B CN106339338B CN201610780787.7A CN201610780787A CN106339338B CN 106339338 B CN106339338 B CN 106339338B CN 201610780787 A CN201610780787 A CN 201610780787A CN 106339338 B CN106339338 B CN 106339338B
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000006073 displacement reaction Methods 0.000 claims description 6
- 230000014509 gene expression Effects 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 4
- 238000012546 transfer Methods 0.000 abstract description 4
- 230000006870 function Effects 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/287—Multiplexed DMA
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/355—Indexed addressing
Abstract
The present invention provides a kind of data transmission methods that system performance can be improved, when starting point dma module has data to transmission, the application for completing memory headroom is interacted with memory headroom management module, starting point DMA will be after data-moving to the corresponding space of memory, the information of this data-moving is uploaded into CPU, data are moved by CPU notice terminal DMA, terminal DMA is after moving corresponding data in memory, correspondence memory space is discharged by memory headroom management module, a partial data is completed to move, during this period, CPU is only responsible for the processing of the data transfer direction of most critical, greatly alleviate CPU burden, improve running efficiency of system.
Description
Technical field
The invention belongs to data paths in SOC piece to exchange transmission field, and system performance can be improved more particularly, to a kind of
Data transmission method and device.
Background technique
According to the statement of Moore's Law, with the development of deep-submicron manufacturing technology, integrated circuit has goed deep into system on chip
Epoch.In the system on chip epoch, the function that a chips are realized becomes increasingly complex, and data exchange is also more and more.At the beginning, piece
Interior data exchange needs CPU to complete, and during this period, CPU cannot respond to other tasks, this certainly will largely occupy cpu resource simultaneously
Reduce system performance.
With the development of technology, DMA technology occurs.At this point, port data, which can use dma module, directly moves memory
In keep in, and moved from memory to other ports using dma module.During this period, CPU only need be responsible for memory address maintenance and
The work such as interrupt response, remaining time can execute other tasks, be released cpu resource.
Although DMA technology greatly releases cpu resource, vast resources can be still occupied, how utmostly to be subtracted
Few CPU bears the direction developed at DMA technology.Such as, from Block DMA to SGDMA (scatter-gather DMA) hair
Exhibition greatly reduces the number for interrupting CPU, discharges a large amount of cpu resources.And the application proposes a kind of system performance of can be improved
Data transmission method can undertake memory address maintenance work, be particularly suitable for the big data quantity exchange scene for having data packet format,
CPU burden is reduced, and then improves system performance.
Summary of the invention
In view of this, the present invention is directed to propose a kind of data transmission method that system performance can be improved, is born with reducing CPU
And improve system performance.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
A kind of data transmission method that system performance can be improved, specifically comprises the following steps:
(1) starting point dma module is to one memory headroom address of memory space management module application；
(2) memory headroom management module pops up an indicator index after receiving application from pointer storehouse, and is converted into interior
Space pointer is deposited, by memory headroom pointer return to origin DMA；
(3) starting point DMA moves data packet in corresponding memory headroom according to memory headroom pointer；
(4) after starting point DMA completes data transmission, starting point DMA will interrupt CPU and the information for transmitting this data uploads
CPU；
(5) CPU responds the interruption of starting point DMA and collects data transmission information, analyzes information and determines terminal DMA, must
The information wanted is sent to terminal DMA；
(6) terminal DMA moves data packet according to memory headroom pointer from corresponding memory headroom；
(7) after terminal DMA completes data transmission, memory headroom pointer is write back into memory headroom management module, memory
Memory headroom pointer is converted into indicator index by space management module, and indicator index is pushed back in pointer storehouse.
Further, the memory headroom pointer be by indicator index after displacement plus shape by way of base address
At the size of the single pointer of how much expressions of displacement.
It further, further include being hit by a bullet after memory headroom management module receives application from pointer storehouse in the step (2)
An indicator index out, if the number of indicator index is less than lower limit value, memory headroom management module returns to 0 value, and interrupts
CPU informs that pointer is used up.
Further, after the success of memory headroom application IP addresses, copy count parameter can be set for it, when same pointer
When data content is needed by n terminal DMA, it is that n is returned after each terminal DMA has moved pointer data that copy parameter, which can be set,
Go back to memory headroom address, copy parameter subtracts one, until all terminal DMA all complete data-moving and return memory headroom address it
Afterwards, copy parameter is zeroed, and copy operation terminates.
Further, after the success of memory headroom application IP addresses, sitation index parameter can be set for it, this parameter is main
Link operation to be completed, two indicator index can be operated by link, link becomes a big indicator index, especially by
Link source and link destination register is arranged to complete, source memory headroom address write-in link source is posted
Storage, and purpose memory headroom address write-in link destination register is completed into link operation；If it is to be understood that certain
Whether a memory headroom address includes link operation, is needed by reading link operation, especially by setting read link
Source and read link destination register is completed, and read link is written in target memory space address
Source register learns whether target memory space address has by reading read link destination register
The memory headroom address of link.
Compared with the existing technology, a kind of data transmission method that system performance can be improved of the present invention has following excellent
Gesture: method of the present invention using starting point DMA by after data-moving to the corresponding space of memory, by the letter of this data-moving
Breath uploads CPU, data is moved by CPU notice terminal DMA, terminal DMA is after moving corresponding data in memory, by interior
Space management module release correspondence memory space is deposited, a partial data is completed and moves, during this period, CPU is only responsible for most critical
Data transfer direction processing, greatly alleviate CPU burden, improve running efficiency of system.
It is negative to reduce CPU another object of the present invention is to propose a kind of data transmission device that system performance can be improved
It carries on a shoulder pole and improves system performance.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
A kind of data transmission device that system performance can be improved, including starting point dma module, terminal dma module, memory headroom
Management module, SDRAM and CPU,
Starting point DMA is used for memory space management module application memory headroom address, moving data；
Terminal DMA is used for moving data, returns to memory headroom pointer and gives memory headroom management module；
Memory headroom management module is used to respond the request of starting point DMA and terminal DMA, and maintenance and management memory headroom refers to
Needle；
SDRAM is for storing data；
It is mainly used for the management of data transfer direction during CPU.
A kind of data transmission device that system performance can be improved and a kind of above-mentioned data that system performance can be improved
Transmission method has the advantage that identical compared with the existing technology, and details are not described herein.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is a kind of transmission structure signal for the data transmission method that system performance can be improved described in the embodiment of the present invention
Figure；
Fig. 2 is a kind of frame of reference frame for the data transmission structure that system performance can be improved described in the embodiment of the present invention
Structure；
Fig. 3 is a kind of frame of reference frame for the data transmission structure that system performance can be improved described in the embodiment of the present invention
Structure.
Specific embodiment
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", "upper", "lower",
The orientation or positional relationship of the instructions such as "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of description of the present invention and simplification of the description, rather than instruction or dark
Show that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as pair
Limitation of the invention.In addition, term " first ", " second " etc. are used for description purposes only, it is not understood to indicate or imply phase
To importance or implicitly indicate the quantity of indicated technical characteristic.The feature for defining " first ", " second " etc. as a result, can
To explicitly or implicitly include one or more of the features.In the description of the present invention, unless otherwise indicated, " multiple "
It is meant that two or more.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood by concrete condition
Concrete meaning in the present invention.
The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
As illustrated in the accompanying drawings from 1 to 3, a kind of data transmission structure that system performance can be improved includes dma module and a memory
Space management module completes memory headroom to the interaction of memory space management module when starting point dma module has data to transmission
The information of this data-moving is uploaded CPU, is led to by CPU by application, starting point DMA by after data-moving to the corresponding space of memory
Know that terminal DMA moves data, terminal DMA is released after corresponding data are moved in memory by memory headroom management module
Correspondence memory space is put, a partial data is completed and moves, during this period, CPU is only responsible for the data transfer direction of most critical
Processing greatly alleviates CPU burden, improves running efficiency of system.As figure label step is described as follows:
1, when starting point DMA, which receives a data packet needs from A port, moves into memory temporary, starting point DMA starts number
It is operated according to transmission；
2, starting point DMA is to memory space management module one piece of memory headroom pointer of application；
3, after memory headroom management module receives the request of starting point DMA, from pointer storehouse (buffer index stack)
One indicator index (buffer index) of middle pop-up is simultaneously converted into memory headroom pointer, by memory headroom pointer return to origin
DMA；
4, starting point DMA moves data packet in corresponding memory headroom according to memory headroom pointer；
5, after starting point DMA completes data transmission, the information that starting point DMA will interrupt CPU and transmit this data, including
The upload CPU such as memory headroom pointer and packet are long；
6, CPU responds the interruption of starting point DMA and collects data transmission information, analyzes information and determines terminal DMA, then will
Necessary information, as memory headroom pointer is sent to terminal DMA；
7, terminal DMA is moved data packet from corresponding memory headroom to port B according to memory headroom pointer；
After terminal DMA completes data transmission, memory headroom pointer is write back into memory headroom management module, memory headroom
Memory headroom pointer is converted back indicator index (buffer index) by management module, and memory headroom management module checks this pointer
Link and copy etc. the parameter for indexing (buffer index), after meeting the requirements, memory headroom management module is by pointer rope
Draw (buffer index) to push back in pointer storehouse (buffer index stack).
Wherein, the specific component representation of transmission structure are as follows:
(1) memory headroom management module: this module is responsible for safeguarding memory headroom address information, and responding DMA module is interior
Space application release request is deposited, memory headroom allocation unit for unit, supports link and copy with buffer (size is configurable)
Operation.
Memory headroom management module includes two main submodules, is pointer storehouse (buffer index stack) and letter
It ceases table (buffer table), pointer storehouse saves indicator index (buffer index), and memory headroom address is by indicator index
(buffer index) is deformed, in each indicator index (buffer index) corresponding informance table (buffer table)
One group information, information include the information such as copy number, link index, application DMA.
Memory headroom address (buffer memory unit pointer) is logical by indicator index (buffer index)
The mode after displacement plus base address is crossed to be formed, displacement number mean that the size of single buffer.Memory headroom pipe
Reason module specific operation process is expressed as follows:
Firstly, initiating the starting point DMA of data transmission to one memory headroom address of memory space management module application, memory
Space management module pops up an indicator index (buffer after receiving application from pointer storehouse (buffer index stack)
Index), if the number of indicator index (buffer index) is less than lower limit value, memory headroom management module returns to 0 value,
And it interrupts CPU and informs that pointer is used up.
After the success of memory headroom application IP addresses, copy count parameter (saving in buffer table) is set for it.This
Function is described as, and when same buffer data content is needed by n terminal DMA, it is n that copy parameter, which can be set, each
After terminal DMA has moved buffer data, memory headroom address is returned to, copy parameter subtracts one, until all terminal DMA are completed
Data-moving and after returning to memory headroom address, copy parameter zero, copy operation terminates.
After the success of memory headroom application IP addresses, link index parameter (saving in buffer table) is set for it.This
A parameter mainly completes link operation, this operation is described as, and two indicator index (buffer index) can be passed through link
Operation, link become a big indicator index (buffer index), especially by setting link source and link
Destination register is completed, and link source register is written in source memory headroom address, and by purpose memory headroom
Address is written link destination register and completes link operation.
It is above-mentioned for complete link operation, if it is to be understood that some memory headroom address whether include link operation, need to lead to
Reading link operation is crossed, is completed especially by setting read link source and read link destination register, it will
Read link source register is written in target memory space address, by reading read link destination deposit
Device learns whether target memory space address has the memory headroom address of link.
After terminal DMA completes the operation for moving out data from memory, need to discharge memory headroom address.In operation
It is terminal DMA by memory headroom write back address memory headroom management module, memory headroom management module turns memory headroom address
It changes indicator index (buffer index) into and indicator index (buffer index) is pushed back pointer storehouse (buffer index
stack)。
CPU, which possesses highest permission, convenient for generating mistake, to interrupt CPU with direct read/write information table (buffer table)
When, CPU does timely processing.
DMA component: it completes basic DMA data and moves function；With completing memory headroom in conjunction with memory headroom management module
The operation such as the application of location, release, copy, link；After completing data-moving, interrupts CPU and upload this data-moving
Relevant information.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (5)
1. a kind of data transmission method that system performance can be improved, it is characterised in that: specifically comprise the following steps:
(1) starting point dma module is to one memory headroom address of memory space management module application；
(2) memory headroom management module pops up an indicator index after receiving application from pointer storehouse, and is converted into memory sky
Between pointer, by memory headroom pointer return to origin DMA；
(3) starting point DMA moves data packet in corresponding memory headroom according to memory headroom pointer；
(4) after starting point DMA completes data transmission, starting point DMA will interrupt CPU and the information for transmitting this data uploads CPU；
(5) CPU responds the interruption of starting point DMA and collects data transmission information, analyzes information and determines terminal DMA, will be necessary
Information is sent to terminal DMA；
(6) terminal DMA moves data packet according to memory headroom pointer from corresponding memory headroom；
(7) after terminal DMA completes data transmission, memory headroom pointer is write back into memory headroom management module, memory headroom
Memory headroom pointer is converted into indicator index by management module, and indicator index is pushed back in pointer storehouse.
2. a kind of data transmission method that system performance can be improved according to claim 1, it is characterised in that: the memory
Space pointer is formed by way of adding base address after displacement by indicator index, the single pointer of how much expressions of displacement
Size.
3. a kind of data transmission method that system performance can be improved according to claim 1, it is characterised in that: the step
It (2) further include that an indicator index is popped up from pointer storehouse after memory headroom management module receives application in, if pointer rope
When the number drawn is less than lower limit value, memory headroom management module returns to 0 value, and interrupts CPU and inform that pointer is used up.
4. a kind of data transmission method that system performance can be improved according to claim 1, it is characterised in that: memory headroom
After application IP addresses success, copy count parameter is set for it, when same pointer data content is needed by n terminal DMA, if
Setting copy parameter is n, after each terminal DMA has moved pointer data, returns to memory headroom address, and copy parameter subtracts one, until
After all terminal DMA complete data-moving and return to memory headroom address, copy parameter zero, copy operation terminates.
5. a kind of data transmission method that system performance can be improved according to claim 1, it is characterised in that: memory headroom
After application IP addresses success, sitation index parameter is set for it, this parameter mainly completes link operation, two indicator index are led to
Link operation is crossed, link becomes a big indicator index, especially by setting link source and link destination
Register is completed, and link source register is written in source memory headroom address, and link is written in purpose memory headroom address
Destination register completes link operation；If needed it is to be understood that whether some memory headroom address includes link operation
It is operated by reading link, is completed especially by setting read link source and read link destination register,
Read link source register is written into target memory space address, is posted by reading read link destination
Storage learns whether target memory space address has the memory headroom address of link.
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| CN110515872B (en) * | 2018-05-21 | 2020-07-31 | 阿里巴巴集团控股有限公司 | Direct memory access method, device, special computing chip and heterogeneous computing system |
| CN111615692A (en) * | 2019-05-23 | 2020-09-01 | 深圳市大疆创新科技有限公司 | Data transfer method, calculation processing device, and storage medium |
| CN113127391B (en) * | 2021-05-13 | 2023-03-14 | 西安微电子技术研究所 | Design method of DMA data transmission engine compatible with multiple devices |
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| CN1797379A (en) * | 2004-12-24 | 2006-07-05 | 华为技术有限公司 | Method of data transmission by using mode of direct memory access |
| CN101421791A (en) * | 2005-02-03 | 2009-04-29 | Level5网络有限公司 | Queue depth management for communication between host and peripheral device |
| CN103262021A (en) * | 2010-12-21 | 2013-08-21 | 国际商业机器公司 | Buffer management scheme for network processor |
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