CN106330378B - A kind of method for synchronizing time of intelligent substation frequency domain time delay optimization - Google Patents
A kind of method for synchronizing time of intelligent substation frequency domain time delay optimization Download PDFInfo
- Publication number
- CN106330378B CN106330378B CN201610801280.5A CN201610801280A CN106330378B CN 106330378 B CN106330378 B CN 106330378B CN 201610801280 A CN201610801280 A CN 201610801280A CN 106330378 B CN106330378 B CN 106330378B
- Authority
- CN
- China
- Prior art keywords
- time
- delay
- time delay
- value
- synchronizing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The present invention provides a kind of method for synchronizing time of intelligent substation frequency domain time delay optimization, fail to fully consider that the intelligent substation environment lower path delay of time fluctuates caused timing tracking accuracy and reduces problem for current time synchronization policy, fully consider the dynamic characteristic of electric power signal, on the basis of IEC61588 time synchronization protocol frame, optimization is synchronized according to Domain Dynamic filter correction model.Low-pass filter is constructed first, and low-pass filtering then is carried out to initial data and obtains smoothed data, master-salve clock time delay best estimate is obtained by smoothed out data, reaches synchronous error effect of optimization.It overcomes conventional method and does not consider timing tracking accuracy decline problem caused by time delay fluctuation, improve synchronization accuracy.
Description
Technical field
The invention belongs to intelligent substation Time synchronization technique field more particularly to a kind of intelligent substation frequency domain time delay are excellent
The method for synchronizing time of change.
Background technique
Intelligent substation is the important foundation for constructing smart grid as smart grid important component and key link
And support.With the fast development of electric system, requirement of each smart machine of intelligent substation to time synchronization is increasingly urgent to.Intelligence
Energy substation mostly uses IEC61588 time synchronization protocol (hereinafter referred to as IEC61588 agreement) to realize interior synchronised clock control of standing.
Clock system is the measurement and control for realizing intelligent substation, and the important foundation and support of protection, precision is by direct shadow
Ring the control precision and performance of intelligent substation.
In existing time synchronization strategy, fail caused by fully considering the fluctuation of the intelligent substation environment lower path delay of time
The problem of timing tracking accuracy reduces.Therefore it is likely to occur the fluctuation of master-salve clock time delay during practical transformer substation synchronous and draws
The synchronous error problem risen.Synchronization accuracy is caused to decline problem for time delay fluctuation, the present invention is fluctuated by Domain Dynamic time delay
Low-pass filtering correction model carries out low-pass filtering amendment to time delay undulating value, obtains master-salve clock time delay best estimate, realizes same
Walk the effect of error optimization.
Summary of the invention
The purpose of the present invention is to provide a kind of method for synchronizing time of intelligent substation frequency domain time delay optimization, this method packets
Include following steps:
S1. it obtains master-salve clock time delay value in intelligent substation and constructs master-salve clock decay time sequence.
If being currently No.k synchronizing cycle, to unite containing the preceding n synchronizing cycle including current No.k synchronizing cycle as time delay
Cycle T is counted, wherein the value of n is 3 ~ 5.Carry out m time delay system each synchronizing cycle between master-salve clock according to constant duration
Meter operation, wherein the value of m is 6 ~ 12.Each delay statistics operation is that master clock first to from clock sends " synchronization delayed time
Req " message, from clock receive message after to master clock return " synchronization delayed time ACK " message, thus master clock acquisition come from
From the master-salve clock time delay value of clock；If i is delay statistics moment serial number, No.i statistics moment master-salve clock time delay value is recorded
For d (i), the master-salve clock time delay value recorded is constituted into master-salve clock decay time sequence { d (i) } (i=1 ..., m*n).
S2. dynamic delay low-pass filtering correction model is constructed.
In a delay statistics cycle T in initial data, selection is without the preceding n-1 including current No.k synchronizing cycle
Time delay value construction dynamic delay filter correction model time domain sequences { fd (j) } (j=1 ..., m* (n-1)) in a synchronizing cycle；It is right
The time domain sequences carry out Fourier transformation and obtain dynamic delay filter correction model frequency domain sequence envelope waveform FD (f), and wherein f is
Frequency variable；Taking the frequency-portions among the first zero crossing of frequency domain sequence envelope waveform FD (f) is the passband of time delay correction model
Band range, the low-pass filter that construction passband amplitude is 1 correct mould as the time delay low-pass filtering of current No.k synchronizing cycle
Type.
S3. the data smoothing of exceptional value is realized using time delay Estimation Optimization low-pass filtering.
In a delay statistics cycle T in initial data, select time delay value construction in current No.k synchronizing cycle new
Sequence nd (p) (p=1 ..., m), mean value ave=E [nd (p)] of sequence of calculation nd (p), given threshold α；If confidence interval is
[ave- α, ave+ α], is selected as sequence variation value for the value nd (p) outside confidence interval；The sequence is low by dynamic delay
Pass filter correction model carries out low-pass filtering, obtains filtered sequence { yd (p) } (p=1 ..., m)；After filtering, if abnormal value sequence
It number is i, then with the value of the value of yd (p=i) replacement nd (p=i), non-abnormal value is remained unchanged, realize the data smoothing of exceptional value,
Time-delay series { ad (q) } (q=1 ..., m) after obtaining data smoothing.
S4. the master-salve clock time delay best estimate of data smoothing sequence.
In current No.k synchronizing cycle, to the time-delay series { ad (q) } (q=1 ..., m) of data smoothing, according to following public affairs
Formula seeks the optimum delay estimated value of sequence:, wherein q is delay statistics moment serial number, that is, is worked as
Preceding No.k synchronizing cycle, the best estimate of master-salve clock time delay are optAd (k).
S5. it is corrected with time delay best estimate from clock and realizes time synchronization optimization.
In current No.k synchronizing cycle, using the best estimate optAd (k) of master-salve clock time delay, according to IEC61588
Agreement synchronizes correction formula from clock:, the time deviation between master-salve clock is calculated,
Wherein,For master clock to from clock send message at the time of,At the time of to receive the message that master clock is sent from clock；
Then according to adjustment from the time value of clock, then realize that the slave clock of No.k synchronizing cycle is synchronous with master clock.
The method for synchronizing time of the intelligent substation frequency domain time delay optimization is directed to same using the IEC61588 time
Walk the intelligent substation that agreement carries out time synchronization.
Compared with general technology, the method for synchronizing time of intelligent substation frequency domain time delay optimization of the present invention, for it is existing when
Between synchronization policy fail to fully consider that timing tracking accuracy reduces problem caused by the intelligent substation environment lower path delay of time is fluctuated,
The dynamic characteristic for fully considering electric power signal is filtered on the basis of IEC61588 time synchronization protocol frame according to Domain Dynamic
Wave correction model synchronizes optimization, reaches synchronous error effect of optimization.Conventional method is overcome not consider time delay fluctuation and draw
The timing tracking accuracy risen declines problem, improves synchronization accuracy.
Detailed description of the invention
Fig. 1 is the method for the present invention overall flow figure.
Fig. 2 is principal and subordinate's clock delay value synchronizing process schematic diagram.
Fig. 3 is principal and subordinate's clock delay time series schematic diagram.
Fig. 4 is dynamic delay low-pass filtering correction model schematic diagram.
Fig. 5 is data smoothing process schematic.
Specific embodiment
As shown in Figure 1 be flow chart of the method for the present invention, below in conjunction with specific embodiment to method of the invention carry out into
One step explanation:
The method for synchronizing time of this intelligent substation frequency domain time delay optimization provided by the invention, is directed to use
IEC61588 time synchronization protocol carries out the intelligent substation of principal and subordinate's time synchronization, includes the following steps:
S1. it obtains master-salve clock time delay value in intelligent substation and constructs master-salve clock decay time sequence.
If being currently No.k synchronizing cycle, to unite containing the preceding n synchronizing cycle including current No.k synchronizing cycle as time delay
Count cycle T.Carry out the subsynchronous delay statistics operation of m each synchronizing cycle between master-salve clock according to constant duration；When each
Prolonging statistical operation is master clock first to sending " synchronization delayed time Req " message from clock, from clock receive message after to it is main when
Clock returns to " synchronization delayed time ACK " message, and thus master clock obtains the master-salve clock time delay value come since clock；If i is time delay system
Serial number is carved in timing, then recording No.i statistics moment master-salve clock time delay value is d (i), the master-salve clock time delay value structure that will be recorded
At master-salve clock decay time sequence { d (i) } (i=1 ..., m*n).
Such as Fig. 2 in example, if being currently No.k synchronizing cycle, with same containing preceding n=3 including current No.k synchronizing cycle
Step period is delay statistics cycle T.Each synchronizing cycle carries out the subsynchronous time delay in m=8 according to constant duration between master-salve clock
Statistical operation；Each delay statistics operation is that master clock connects to " synchronization delayed time Req " message is sent from clock from clock first
It receives and returns to " synchronization delayed time ACK " message to master clock after message, thus master clock, which obtains, comes when the master-salve clock of clock
Prolong value；If i is delay statistics moment serial number, recording No.i statistics moment master-salve clock time delay value is d (i), by what is recorded
Master-salve clock time delay value constitutes master-salve clock decay time sequence { d (i) } (i=1 ..., m*n), and as a result signal is as shown in Figure 3.
S2. dynamic delay low-pass filtering correction model is constructed.
In a delay statistics cycle T in initial data, selection is without the preceding n-1 including current No.k synchronizing cycle
Time delay value construction dynamic delay filter correction model time domain sequences { fd (j) } (j=1 ..., m* (n-1)) in a synchronizing cycle；It is right
The time domain sequences carry out Fourier transformation and obtain dynamic delay filter correction model frequency domain sequence envelope waveform FD (f), and wherein f is
Frequency variable；Taking the frequency-portions among the first zero crossing of frequency domain sequence envelope waveform FD (f) is the passband of time delay correction model
Band range, the low-pass filter that construction passband amplitude is 1 correct mould as the time delay low-pass filtering of current No.k synchronizing cycle
Type.
Such as Fig. 4 in example, in a delay statistics cycle T in initial data, n=3 are taken, selection is free of current No.k
Time delay value construction dynamic delay filter correction model time domain sequences { fd (j) } in preceding n-1 synchronizing cycle including synchronizing cycle
(j=1,…,8*(n-1))；Fourier transformation is carried out to the time domain sequences and obtains dynamic delay filter correction model frequency domain sequence packet
Network waveform FD (f), wherein f is frequency variable；The frequency-portions among the first zero crossing of frequency domain sequence envelope waveform FD (f) are taken to be
The pass band of time delay correction model, the low-pass filter that construction passband amplitude is 1 is as current No.k synchronizing cycle
Time delay low-pass filtering correction model.
S3. the data smoothing of exceptional value is realized using time delay Estimation Optimization low-pass filtering.
In a delay statistics cycle T in initial data, select time delay value construction in current No.k synchronizing cycle new
Sequence { nd (p) } (p=1 ..., m), mean value ave=E [nd (p)] of sequence of calculation nd (p), given threshold α；If confidence interval
For [ave- α, ave+ α], the value nd (p) outside confidence interval is selected as sequence variation value；The sequence is passed through into dynamic delay
Low-pass filtering correction model carries out low-pass filtering, obtains filtered sequence { yd (p) } (p=1 ..., m)；After filtering, if exceptional value sequence
Row number is i, then the value of nd (p=i) is replaced with the value of yd (p=i), and non-abnormal value remains unchanged, and realizes that the data of exceptional value are flat
Sliding, after obtaining data smoothing time-delay series { ad (q) } (q=1 ..., m).
Such as Fig. 5 in example, in a delay statistics cycle T in initial data, m=8 are taken, select current No.k synchronous
Time delay value constructs new sequence nd (p) (p=1 ..., m) in period, mean value ave=E [nd (p)] of sequence of calculation nd (p), setting
Threshold alpha=0.1；If confidence interval is [ave- α, ave+ α], the value nd (p) outside confidence interval is selected as sequence variation value；
By the sequence by dynamic delay low-pass filtering correction model, carry out low-pass filtering, obtain filtered sequence { yd (p) } (p=1 ...,
m)；After filtering, if exceptional value Serial No. i, then the value of nd (p=i) is replaced with the value of yd (p=i), non-abnormal value is kept not
Become, realizes the data smoothing of exceptional value, the time-delay series { ad (q) } (q=1 ..., m) after obtaining data smoothing.
S4. the master-salve clock time delay best estimate of data smoothing sequence.
In current No.k synchronizing cycle, to the time-delay series { ad (q) } (q=1 ..., m) of data smoothing, according to following public affairs
Formula seeks the optimum delay estimated value of sequence:, wherein q is delay statistics moment serial number, that is, is worked as
Preceding No.k synchronizing cycle, the best estimate of master-salve clock time delay are optAd (k).
As shown in figure 5, taking m=8 in current No.k synchronizing cycle in example, to the time-delay series { ad of data smoothing
(q) } (q=1 ..., m) seeks the optimum delay estimated value of sequence according to following formula:, wherein
M=8, q are delay statistics moment serial number, i.e., current No.k synchronizing cycle, the best estimate of master-salve clock time delay is optAd
(k)。
S5. it is corrected with time delay best estimate from clock and realizes time synchronization optimization.
In current No.k synchronizing cycle, using the best estimate optAd (k) of master-salve clock time delay, according to IEC61588
Agreement synchronizes correction formula from clock:, the time deviation between master-salve clock is calculated,
Wherein,For master clock to from clock send message at the time of,At the time of to receive the message that master clock is sent from clock；
Then then realize that the slave clock of current No.k synchronizing cycle is synchronous with master clock from the time value of clock according to adjustment.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of protection of the claims
Subject to.
Claims (6)
1. a kind of method for synchronizing time of intelligent substation frequency domain time delay optimization, comprising the following steps:
S1. it obtains master-salve clock time delay value in intelligent substation and constructs master-salve clock decay time sequence；
S2. dynamic delay low-pass filtering correction model is constructed；
S3. the data smoothing of exceptional value is realized using time delay Estimation Optimization low-pass filtering；
S4. the master-salve clock time delay best estimate of data smoothing sequence；
S5. it is corrected with time delay best estimate from clock and realizes time synchronization optimization.
2. the method for synchronizing time of intelligent substation frequency domain time delay optimization according to claim 1, it is characterised in that described
Synchronous method be directed to using IEC61588 time synchronization protocol carry out time synchronization intelligent substation.
3. the method for synchronizing time of intelligent substation frequency domain time delay optimization according to claim 1, which is characterized in that described
In step S1, if being currently No.k synchronizing cycle, to unite containing the preceding n synchronizing cycle including current No.k synchronizing cycle as time delay
Cycle T is counted, wherein the value of n is 3~5, and each synchronizing cycle carries out m time delay according to constant duration between master-salve clock
Statistical operation, wherein the value of m is 6~12.
4. the method for synchronizing time of intelligent substation frequency domain time delay optimization according to claim 1, which is characterized in that described
In step S2, in a delay statistics cycle T in initial data, selection is without the preceding n- including current No.k synchronizing cycle
Time delay value construction dynamic delay filter correction model time domain sequences { fd (j) } (j=1 ..., m* (n-1)) in 1 synchronizing cycle；
Fourier transformation is carried out to the time domain sequences and obtains dynamic delay filter correction model frequency domain sequence envelope waveform FD (f), wherein f
For frequency variable；Taking the frequency-portions among the first zero crossing of frequency domain sequence envelope waveform FD (f) is the logical of time delay correction model
Frequency range, the low-pass filter that construction passband amplitude is 1 are corrected as the time delay low-pass filtering of current No.k synchronizing cycle
Model.
5. the method for synchronizing time of intelligent substation frequency domain time delay optimization according to claim 1, which is characterized in that described
In step S3, in a delay statistics cycle T in initial data, select time delay value construction in current No.k synchronizing cycle new
Sequence nd (p) (p=1 ..., m), the mean value ave=E [nd (p)] of sequence of calculation nd (p), given threshold α；If confidence interval
For [ave- α, ave+ α], the value nd (p) outside confidence interval is selected as sequence variation value；The sequence is passed through into dynamic delay
Low-pass filtering correction model carries out low-pass filtering, obtains filtered sequence { yd (p) }；After filtering, if exceptional value Serial No. i, then
With the value of value replacement nd (p=i) of yd (p=i), non-abnormal value is remained unchanged, and realizes the data smoothing of exceptional value, obtains number
According to smoothed out time-delay series { ad (q) } (q=1 ..., m).
6. the method for synchronizing time of intelligent substation frequency domain time delay optimization according to claim 1, which is characterized in that described
In step S4, in current No.k synchronizing cycle, to the time-delay series { ad (q) } of data smoothing, sequence is sought according to following formula
Optimum delay estimated value:Wherein q is delay statistics moment serial number, i.e., current No.k synchronizes week
Phase, the best estimate of master-salve clock time delay are optAd (k).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610801280.5A CN106330378B (en) | 2016-09-05 | 2016-09-05 | A kind of method for synchronizing time of intelligent substation frequency domain time delay optimization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610801280.5A CN106330378B (en) | 2016-09-05 | 2016-09-05 | A kind of method for synchronizing time of intelligent substation frequency domain time delay optimization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106330378A CN106330378A (en) | 2017-01-11 |
| CN106330378B true CN106330378B (en) | 2019-03-29 |
Family
ID=57787389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610801280.5A Expired - Fee Related CN106330378B (en) | 2016-09-05 | 2016-09-05 | A kind of method for synchronizing time of intelligent substation frequency domain time delay optimization |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106330378B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022235245A1 (en) * | 2021-05-06 | 2022-11-10 | Roketsan Roket Sanayi̇i̇ Ti̇caret A.Ş. | Inter-component time shift estimation and signal alignment method for hardware and software integrated simulations |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227246A (en) * | 2008-01-28 | 2008-07-23 | 中兴通讯股份有限公司 | Method and apparatus for master-salve clock synchronization |
| CN105721095A (en) * | 2016-02-26 | 2016-06-29 | 江苏省电力公司检修分公司 | Substation device clock synchronization improving method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8959381B2 (en) * | 2012-09-05 | 2015-02-17 | Khalifa University of Science, Technology, and Research | Method and system for clock offset and skew estimation |
-
2016
- 2016-09-05 CN CN201610801280.5A patent/CN106330378B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227246A (en) * | 2008-01-28 | 2008-07-23 | 中兴通讯股份有限公司 | Method and apparatus for master-salve clock synchronization |
| CN105721095A (en) * | 2016-02-26 | 2016-06-29 | 江苏省电力公司检修分公司 | Substation device clock synchronization improving method |
Non-Patent Citations (1)
| Title |
|---|
| IEEE1588标准下准确时间值的获取方法;张涛等;《化工自动化及仪表》;20141010;全文 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106330378A (en) | 2017-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103763055B (en) | The method of precise synchronization time a kind of | |
| CN101252429B (en) | Method for enhancing clock synchronization accuracy in distributed network system | |
| CN102332973B (en) | Real-time communication and clock synchronization method of chain network | |
| CN106603183B (en) | A kind of timestamp filter method and device | |
| Kim et al. | Energy-efficient time synchronization based on asynchronous source clock frequency recovery and reverse two-way message exchanges in wireless sensor networks | |
| US20090135677A1 (en) | System and method for application layer time synchronization without creating a time discrepancy or gap in time | |
| JP2013106329A (en) | Communication apparatus | |
| CN103702409B (en) | Synchronous detection method for TD-LTE (time division long term evolution) network optimized equipment | |
| CN104053223A (en) | Low-power wireless sensor network time synchronization method | |
| CN104918319A (en) | Clock synchronization simplified information exchange method applied to wireless sensor network | |
| BR112014015407B1 (en) | METHOD AND APPLIANCE BASED ON CIRCUITS TO RECEIVE DATA COMMUNICATION THROUGH POWER DISTRIBUTION LINES AND DEVICE | |
| CN107959969A (en) | A kind of method for synchronizing time applied to transient state recording type fault detector | |
| CN104579623A (en) | Network time-setting system and method for secondary equipment of electric power system | |
| CN106656397B (en) | Clock synchronizing method and device | |
| CN202353572U (en) | Institute of Electrical and Electronic Engineers (IEEE) 1588 time synchronization system for electronic type mutual inductor merging units | |
| CN109548135A (en) | A kind of wireless network time synchronous method of optimization | |
| CN102769504A (en) | 1588 system and method thereof for achieving synchronization | |
| CN105376043A (en) | Dual-board system time synchronization method | |
| CN106100781A (en) | Clock tracking method and system based on E1 channel | |
| CN106330378B (en) | A kind of method for synchronizing time of intelligent substation frequency domain time delay optimization | |
| CN106162858B (en) | Directintermination time synchronization method and device | |
| CN108632989A (en) | A kind of wireless sensor network consistency Distributed Time synchronous method | |
| CN103684358B (en) | Sampling pulse generates method and apparatus | |
| CN102412954A (en) | Clock frequency synchronization method in packet based network | |
| CN103957591A (en) | Node pair based wireless sensor network time synchronization method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190329 Termination date: 20200905 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |