CN106330340A - Light receiving circuit and method for preventing logical abnormalities - Google Patents
Light receiving circuit and method for preventing logical abnormalities Download PDFInfo
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- CN106330340A CN106330340A CN201610847410.9A CN201610847410A CN106330340A CN 106330340 A CN106330340 A CN 106330340A CN 201610847410 A CN201610847410 A CN 201610847410A CN 106330340 A CN106330340 A CN 106330340A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/697—Arrangements for reducing noise and distortion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
- H04B10/0799—Monitoring line transmitter or line receiver equipment
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
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Abstract
The invention provides a light receiving circuit. The light receiving circuit includes a light signal receiving module, a one-stage amplifying circuit, a two-stage amplifying circuit and a comparison output circuit which are connected with one another sequentially; the two-stage amplifying circuit comprises two input ends and two output ends; and one of the input ends of the two-stage amplifying circuit is connected with a constant current bias circuit, so that the voltage difference of the two output ends of the two-stage amplifying circuit is always greater than a preset value. The present invention also provides a method for preventing the logic abnormalities of a circuit. According to the light receiving circuit and the method for preventing the logical abnormalities provided by the embodiments of the present invention, one of the input ends of the two-stage amplifying circuit is connected with the constant current bias circuit, so that the voltage difference of two input ends of the comparison output circuit, namely, the voltage difference of the two output ends of the two-stage amplifying circuit, is always greater than the preset value, and the comparison output circuit can always confirm and identify the voltage difference of the two input ends of the comparison output circuit, and therefore, it can be ensured that the comparison output circuit can always output correct digital logic signals.
Description
Technical field
The present embodiments relate to optical communication technique, refer more particularly in a kind of optical receiving circuit and a kind of optical receiving circuit
Prevent the method that logic is abnormal.
Background technology
The signal transmission system that IGBT driving chip is made up of light emitting diode and photodiode.In general, luminous
Together with diode is encapsulated in the reception circuit of integrated photodiode.The optical signal received due to integrated photodiode
The faintest, therefore, in existing optical signal reception technique, optical signal receiving circuit usually occurs that logic is judged by accident, and causes
Distorted signals.
Summary of the invention
The purpose of the embodiment of the present invention is, it is provided that a kind of optical receiving circuit and a kind of side preventing circuit logic abnormal
Method, with the problem solving to cause distorted signals because of circuit logic erroneous judgement in traditional optical signal receiving circuit.
On the one hand, the invention provides a kind of optical receiving circuit, including:
Optical signal receiving module；
One-level amplifying circuit, the input of this one-level amplifying circuit is connected to described optical signal receiving module, for by institute
State current signal produced by optical signal receiving module and be converted to the first voltage signal；
Second amplifying circuit, the input of this second amplifying circuit is connected to the outfan of described one-level amplifying circuit, uses
In producing the second voltage signal and reference voltage signal according to described first voltage signal；And
Relatively output circuit, this input comparing output circuit is connected to described second amplifying circuit to outfan, use
In exporting corresponding digital logic signal according to described second voltage signal and described reference voltage signal；
Wherein, described second amplifying circuit includes two inputs and two outfans, and one of them input connects to be had
Constant current bias circuit, so that the voltage difference perseverance of the two of described second amplifying circuit outfans is more than a preset value.
On the one hand, the invention provides a kind of method preventing logic abnormal, be applied in optical receiving circuit, the method bag
Include following steps:
Optical signal receiving step, receives optical signal and the optical signal of reception is converted to current signal；
Current-voltage switch process, amplifies current signal and is converted to the first voltage signal；
Voltage amplification step, produces the second voltage signal and reference voltage signal according to described first voltage signal；And
Relatively output step, relatively described second voltage signal and described reference voltage signal, export according to comparative result
Corresponding digital logic signal；
Wherein, described voltage amplification step is realized by a second amplifying circuit, and this second amplifying circuit includes one
Second amplifier, this second amplifier includes two inputs and two outfans, and one of them input connects a perseverance
Stream biasing circuit, this constant current bias circuit makes the voltage difference perseverance of described second voltage signal and reference voltage signal more than one
Preset value.
The optical receiving circuit of the embodiment of the present invention and prevent the method that circuit logic is abnormal, it is by second amplifying circuit
One of them input connect a constant current bias circuit so that the voltage difference of two outfans of second amplifying circuit (can
It is equal to or convertible in the voltage difference of two inputs comparing output circuit) permanent more than a preset value so that the most defeated
Go out circuit to be confirmed all the time the voltage difference between two input to identify, thus ensure that to compare output circuit the most defeated
Go out correct digital logic signal.
In order to be able to be further understood that inventive feature and technology contents, refer to below in connection with the present invention is detailed
Illustrate and accompanying drawing, but accompanying drawing only provides reference and explanation use, be not used for the present invention is any limitation as.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of the optical receiving circuit of the embodiment of the present invention.
Fig. 2 is the circuit diagram of the optical receiving circuit of the embodiment of the present invention.
Fig. 3 be in the optical receiving circuit shown in Fig. 2 key node waveform diagram.
Fig. 4 be the embodiment of the present invention optical receiving circuit in the schematic equivalent circuit of photodiode.
Fig. 5 is the circuit diagram of the optical receiving circuit of another embodiment of the present invention.
Fig. 6 is the signal processing flow figure preventing circuit logic exception of the embodiment of the present invention.
Main element symbol description
Optical receiving circuit 100
Optical signal receiving module 10
One-level amplifying circuit 20
Second amplifying circuit 30
Relatively output circuit 40
Photodiode D1
First amplifier OP1
Second amplifier OP2
Comparator CMP
First resistance R1
Second resistance R2_1
3rd resistance R2_2
4th resistance R3_1
5th resistance R3_2
6th resistance R4_1
7th resistance R4_2
Constant current bias circuit IB
Specific embodiment
By further illustrating the technological means and effect, being preferable to carry out below in conjunction with the present invention that the present invention taked
Example and accompanying drawing thereof are described in detail.
Refer to Fig. 1,2, in the present embodiment, optical receiving circuit 100 includes the optical signal receiving module connected in order
10, one-level amplifying circuit 20, second amplifying circuit 30 and compare output circuit 40.
Optical signal receiving module 10 is for receiving the optical signal of external light source, and by this optical signal and be converted to electric current letter
Number, with output to one-level amplifying circuit 20.This optical signal receiving module 10 can include photodiode D1 or other photosensitive units
Part.
In the present embodiment, optical signal receiving module 10 is the photodiode D1 being operated under reverse-biased, this photoelectricity
Diode D1 is not when having illumination or faint light photograph, and the electric current of output is the faintest, is equivalent to be in cut-off state；Should
Photodiode D1 is when relatively intense light irradiation, and directional current increases rapidly, is equivalent to be in conducting state.
It should be noted that this current signal needs to be detected by subsequent conditioning circuit, this subsequent conditioning circuit can be according to electric current
Size exports corresponding digital logic signal, it is provided that rear class reading circuit processes.
One-level amplifying circuit 20, the input of this one-level amplifying circuit 20 is connected to described optical signal receiving module 10, uses
In current signal produced by described optical signal receiving module 10 is converted to the first voltage signal.
In the present embodiment, one-level amplifying circuit 20 includes the first amplifier OP1, the first resistance R1, the second resistance R2_1
And the 3rd resistance R2_2, wherein: the first amplifier OP1 includes that first input end, the second input, the first outfan and second are defeated
Going out end, the first input end of the first amplifier OP1 is connected to one end of optical signal receiving module 10 by the first resistance R1 and leads to
Crossing the second resistance R2_1 and be connected to first outfan of the first amplifier OP1, second input of the first amplifier OP1 is by the
Three resistance R2_2 are connected to second outfan of the first amplifier OP1, first outfan of the first amplifier OP1 and the second output
The outfan as one-level amplifying circuit 20 is held to be connected to second amplifying circuit 30.
In the present embodiment, photodiode D1 belongs to a submodule of integrated circuit, is not to separately exist in collection
Become outside circuit.Different technique, the key parameter of photodiode D1 is the most different, such as optical signal transmission ratio, parasitic knot
Electric capacity etc., can these parameters all can have influence on reception circuit below and normally work.
First resistance R1, as input resistance, can be used to the problem eliminating photodiode D1 with process deviation, typically
It is arranged on hundreds of ohm to about one kilohm.All kinds of technological requirement can be met.
First amplifier OP1 can be trans-impedance amplifier (Trans-impedance Amplifier, TIA), this TIA it
In-phase input end be the first input end of the first amplifier OP1, inverting input be the first amplifier OP1 the second input,
Reversed-phase output be first outfan of the first amplifier OP1, in-phase output end be second outfan of the first amplifier OP1.
Certainly, the first amplifier OP1 can also use other amplifier elements.
Second amplifying circuit 30, the input of this second amplifying circuit 30 is connected to the output of described one-level amplifying circuit 20
End, for producing the second voltage signal and reference voltage signal according to described first voltage signal.Wherein, second amplifying circuit 30
Including two inputs and two outfans, one of them input connects constant current bias circuit IB, so that two grades are amplified electricity
The voltage difference perseverance of two outfans on road 30 is more than a preset value.
In the present embodiment, second amplifying circuit 30 includes the second amplifier OP2, the 4th resistance R3_1, the 5th resistance R3_
2, the 6th resistance R4_1, the 7th resistance R4_2 and described constant current bias circuit IB, wherein: the second amplifier OP2 includes that first is defeated
Entering end, the second input, the first outfan and the second outfan, it is inclined that the first input end of the second amplifier OP2 is connected to constant current
Circuits IB, it is connected to first outfan and by the 6th resistance R4_1 even of the first amplifier OP1 by the 4th resistance R3_1
Being connected to first outfan of the second amplifier OP2, second input of the second amplifier OP2 is by described 5th resistance R3_2 even
It is connected to second outfan of the first amplifier OP1 and is connected to second output of the second amplifier OP2 by the 7th resistance R4_2
End, first outfan of the second amplifier OP2 and the second outfan are connected to compare as the outfan of second amplifying circuit 30
Output circuit 40.
First amplifier OP1 can be anti-phase ratio-voltage amplifier, the homophase input of this anti-phase ratio-voltage amplifier
End be the first input end of the second amplifier OP2, inverting input be second input of the second amplifier OP2, anti-phase output
End be first outfan of the second amplifier OP2, in-phase output end be second outfan of the second amplifier OP2.Certainly, second
Amplifier OP2 can also use other amplifier elements.
Relatively output circuit 40, this input comparing output circuit 40 is connected to the output of described second amplifying circuit 30
End, for exporting corresponding digital logic signal according to described second voltage signal and described reference voltage signal.
Relatively output circuit 40 includes at least one comparator CMP, wherein: comparator CMP include first input end, second
Input, the first outfan and the second outfan, the first input end of comparator CMP is connected to the first of the second amplifier OP2
Outfan, comparator CMP is connected to second outfan of the second amplifier OP2, first outfan of comparator CMP and second defeated
Go out the end outfan as optical receiving circuit 100, be used for exporting corresponding digital logic signal, it is provided that rear class reading circuit is carried out
Process.In the present embodiment, the voltage difference of 30 two outfans of second amplifying circuit and compare 40 two inputs of output circuit
Voltage difference identical.In the present embodiment, comparator CMP can be high-speed comparator.
In a preferred embodiment, constant current bias circuit IB needs to meet following condition:
R2_1*IS*(R4_1/R3_1)≥M*IB*R3_2；
Wherein, R2_1 be described second resistance, R3_1 be described 4th resistance, R3_2 be that described 5th resistance, R4_1 are
Described 6th resistance, ISFor the electric current of optical signal receiving module 10 generation, IBFor the electric current of described constant current bias circuit IB offer, M
For the real number more than or equal to 2.The preferred embodiment has ensured the voltage comparing two inputs of output circuit CMP further
Difference, thus avoid the logic of comparator CMP to judge by accident.
In a preferred embodiment, when optical signal receiving module 10 uses photodiode D1, refer to Fig. 4, it is
The equivalent circuit diagram of photodiode D1.Is is equivalent current, and Rs is equivalent series resistance, by contact resistance, non-depletion layer material
The bulk resistor of material is formed.Cd is junction capacity.The size of Rs, Cd is relevant with bias with size, the structure of photodiode.Bias
The biggest, Rs, Cd are the least.Rd is the parallel resistance of silicon photoelectric diode, by silicon photoelectric diode depletion layer resistance and ohmic leakage institute
Constitute, relevant with pipe sizing.Junction area is the least, and Rd is the least.
Due to an external RC (Resistance-Capacitance) series connection of the normal job demand of one-level amplifying circuit 20
Compensate network and stablize its duty, but extra RC circuit needs to account for chip area.For solving this problem, this is the most real
Executing the example plus earth by photodiode D1, negative electrode is connected to first input of the first amplifier OP1 by the first resistance R1
End, forms a RC series circuit by parasitic junction capacitance Cd and the first resistance R1 of photodiode D1 optocoupler, it is provided that one
Zero point carrys out compensation loop stability.
In a preferred embodiment, one or more for variable resistance in the first resistance to the 7th resistance.
So that the embodiment of the present invention becomes apparent from understanding, with Fig. 2 as reference, concrete to the embodiment of the present invention below
Circuit operation principle carries out labor.In analysis, involved component includes photodiode D1, the first amplifier
OP1, the second amplifier OP2, comparator CMP, the first resistance to the 7th resistance (R1, R2_1, R2_2, R3_1, R3_3, R4_1,
R4_2), constant current bias circuit IB.Wherein, R2_2, R3_1=R3_3, R4_1=R4_2.IPD is that photodiode D1 produces
Current signal (photoelectric current).
Work as IPD=0, bias current IBWhen=0, then: VINP1=VINN1, VPD=VR1, VINP1 are approximately equal to photoelectricity two
The reversed bias voltage of pole pipe D1, it is assumed that the DC offset voltage of VPD=VR1 is Va；VPD_A=VR2, it is assumed that VPD_A=VR2's is straight
Stream bias voltage is Vb.
As IPD=Is (Is is photodiode maximum photoelectric current), VINP1=VINN1, the second resistance R2_1 can be flowed through and arrive
Ground, therefore: VPD=Va+R2_1*Is.
Refer to Fig. 3, IPD is the trip current signal from 0 to Is, and VPD changes between Va and Va+R2_1*Is.Tr table
Showing the rising delay of photoelectric current, tf represents the fall delay of photoelectric current, therefore draws:
VPD_A=Vb-[Va+R2_1*Is* (R4_1/R3_1)]；
VR2=Vb-[Va+R2_2*0* (R4_2/R3_2)]=Vb；
As Is=0, VPD_A=VR2=Vb；
When Is does not waits zero, VPD_A-VR2=-R2_1*Is* (R4_1/R3_1).
For comparator CMP, as Is=0, it cannot judge correct logic state.Because during Is=0, than
Equal compared with the voltage of the two of device CMP inputs, comparator CMP cannot normally work.In order to solve this problem, put second
The inverting input of big device OP2 accesses a constant current bias circuit IB, it is ensured that the voltage difference of two inputs of comparator CMP.
After adding this constant current bias circuit IB:
As Is=0, VR2 can than VPD_A a low IB* the magnitude of voltage of R3_2: VPD_A=Vb, VR2=Vb-IB*R3_
2.Understand, between two inputs of comparator CMP, there is IB* the voltage difference of R3_2, this voltage difference is generally located on 50mV
Left and right, and I can be adjusted according to practical situationBSize or the size of the 5th resistance R3_2.The pressure reduction of this rank, one
As comparator can normally identify, it is easy to transplant.
When Is is not equal to zero, have:
VPD_A=Vb-[Va+R2_1*Is* (R4_1/R3_1)]；
VR2=Vb-IB*R3_2-[Va+R2_2*0*(R4_2/R3_2)]；
VPD_A-VR2=IB*R3_2-R2_1*Is*(R4_1/R3_1)；
Understanding, the voltage difference between two inputs of comparator CMP still has certain probability to be zero, causes comparator
The logic erroneous judgement of CMP, to this end, the electric current I of constant current bias circuit IB outputBAlso need to meet following condition:
R2_1*Is*(R4_1/R3_1)≥M*IB*R3_2；
Is is photodiode photo stream, IBFor the current signal of constant-current source bias circuit I B offer, M is real number, this reality
Execute the preferred M=2 of example, to realize optimal performance.
To sum up, the embodiment of the present invention is it can be avoided that the logic easily occurred in traditional circuit is judged by accident, and the present invention implements
In example, all of resistance and constant current bias circuit all can be adjusted by the way of different, such as fuse regulation, and numeral is compiled
Journey regulation etc., is used for meeting polytechnic different demand, and transplantability is the highest.
In another embodiment, as it is shown in figure 5, be with the circuit difference of Fig. 2, constant current bias circuit IB uses
The mode of one end ground connection.
The signal processing flow figure preventing circuit logic exception of Fig. 6 position embodiment of the present invention.
Optical signal receiving step S10, receives optical signal and the optical signal of reception is converted to current signal.
Current-voltage switch process S20, amplifies current signal and is converted to the first voltage signal.Step S10 passes through one
Individual photodiode realizes, and step S20 is realized by an one-level amplifying circuit, the plus earth of this photodiode, negative electrode
Described one-level amplifying circuit is connected, in order to the parasitic junction capacitance of described photodiode and described resistance are formed by a resistance
One RC circuit.
Voltage amplification step S30, produces the second voltage signal and reference voltage signal according to described first voltage signal.Step
Rapid S30 is realized by a second amplifying circuit, and this second amplifying circuit includes second amplifier, this second amplifier bag
Including two inputs and two outfans, one of them input connects a constant current bias circuit, this constant current bias circuit
Make the voltage difference perseverance of described second voltage signal and reference voltage signal more than a preset value.
Relatively output step S40, relatively described second voltage signal and described reference voltage signal, defeated according to comparative result
Go out corresponding digital logic signal.
The above, for the person of ordinary skill of the art, can be according to technical scheme and technology
Other various corresponding changes and deformation are made in design, and all these change and deformation all should belong to the claims in the present invention
Protection domain.
Claims (10)
1. an optical receiving circuit, it is characterised in that including:
Optical signal receiving module；
One-level amplifying circuit, the input of this one-level amplifying circuit is connected to described optical signal receiving module, for by described light
Current signal produced by signal receiving module is converted to the first voltage signal；
Second amplifying circuit, the input of this second amplifying circuit is connected to the outfan of described one-level amplifying circuit, is used for depending on
The second voltage signal and reference voltage signal is produced according to described first voltage signal；And
Relatively output circuit, this input comparing output circuit is connected to the outfan of described second amplifying circuit, is used for depending on
Corresponding digital logic signal is exported according to described second voltage signal and described reference voltage signal；
Wherein, described second amplifying circuit includes two inputs and two outfans, and one of them input connects constant current
Biasing circuit, so that the voltage difference perseverance of the two of described second amplifying circuit outfans is more than a preset value.
2. optical receiving circuit as claimed in claim 1, it is characterised in that described one-level amplifying circuit include the first amplifier,
First resistance, the second resistance and the 3rd resistance, wherein:
Described first amplifier includes first input end, the second input, the first outfan and the second outfan, and described first puts
The first input end of big device is connected to one end of described optical signal receiving module and by described second by described first resistance
Resistance is connected to the first outfan of described first amplifier, and the second input of described first amplifier is by described 3rd electricity
Resistance is connected to the second outfan of described first amplifier, the first outfan of described first amplifier and the second outfan conduct
The outfan of described one-level amplifying circuit is connected to described second amplifying circuit.
3. optical receiving circuit as claimed in claim 2, it is characterised in that described second amplifying circuit include the second amplifier,
4th resistance, the 5th resistance, the 6th resistance, the 7th resistance and described constant current bias circuit, wherein: described second amplifier includes
First input end, the second input, the first outfan and the second outfan, the first input end of described second amplifier is connected to
Described constant current bias circuit, it is connected to the first outfan of described first amplifier by described 4th resistance and by described the
Six resistance are connected to the first outfan of described second amplifier, and the second input of described second amplifier passes through the described 5th
Resistance be connected to described first amplifier the second outfan and by described 7th resistance be connected to described second amplifier it
Second outfan, the first outfan of described second amplifier and the second outfan are as the outfan of described second amplifying circuit
It is connected to described compare output circuit.
4. optical receiving circuit as claimed in claim 3, it is characterised in that described constant current bias circuit meets following relation:
R2_1*IS*(R4_1/R3_1)≥M*IB*R3_2；
Wherein, R2_1 be described second resistance, R3_1 be described 4th resistance, R3_2 be described 5th resistance, R4_1 be described
6th resistance, IS is the electric current of described optical signal receiving module generation, and IB for the electric current of described constant current bias circuit offer, M is
Real number more than or equal to 2.
5. optical receiving circuit as claimed in claim 4, it is characterised in that the described output circuit that compares includes that at least one compares
Device, wherein:
Described comparator includes first input end, the second input, the first outfan and the second outfan, the of described comparator
One input is connected to the first outfan of described second amplifier, and the second input of described comparator is connected to described second
Second outfan of amplifier, the first outfan of described comparator and the second outfan are as the output of described optical receiving circuit
End.
6. the optical receiving circuit as described in claim 1-5 any one, it is characterised in that described optical signal receiving module includes
Photodiode, the plus earth of this photodiode, negative electrode is connected to described first amplifying circuit by described first resistance
Input.
7. the optical receiving circuit as described in claim 2-5 any one, it is characterised in that described first amplifier is for put across resistance
Big device.
8. the optical receiving circuit as described in claim 3-5 any one, it is characterised in that described first resistance is to the 7th resistance
In one or more for variable resistance.
9. prevent the method that logic is abnormal, be applied in optical receiving circuit, it is characterised in that the method includes following step
Rapid:
Optical signal receiving step, receives optical signal and the optical signal of reception is converted to current signal；
Current-voltage switch process, amplifies current signal and is converted to the first voltage signal；
Voltage amplification step, produces the second voltage signal and reference voltage signal according to described first voltage signal；And it is the most defeated
Go out step, relatively described second voltage signal and described reference voltage signal, export corresponding Digital Logic according to comparative result
Signal；
Wherein, described voltage amplification step is realized by a second amplifying circuit, and this second amplifying circuit includes one second
Amplifier, this second amplifier includes two inputs and two outfans, and one of them input connects has a constant current inclined
Circuits, this constant current bias circuit makes the voltage difference perseverance of described second voltage signal and reference voltage signal preset more than one
Value.
10. optical receiving circuit as claimed in claim 9, it is characterised in that described optical signal receiving step passes through a photoelectricity
Diode realizes, and described current-voltage switch process is realized by an one-level amplifying circuit, and the anode of this photodiode connects
Ground, negative electrode connect described one-level amplifying circuit by resistance, in order to the parasitic junction capacitance of described photodiode and described
Resistance forms a RC circuit.
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| CN201610847410.9A CN106330340B (en) | 2016-09-23 | 2016-09-23 | Optical receiving circuit and the method for preventing logic exception |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610847410.9A CN106330340B (en) | 2016-09-23 | 2016-09-23 | Optical receiving circuit and the method for preventing logic exception |
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| CN106330340B CN106330340B (en) | 2019-07-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109560879A (en) * | 2017-09-27 | 2019-04-02 | 敦宏科技股份有限公司 | The optics for having dark current correcting function receives circuit and its dark current correction method |
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| CN204517817U (en) * | 2015-03-20 | 2015-07-29 | 深圳光启创新技术有限公司 | Photoelectric switching circuit and optical signal receiver |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560879A (en) * | 2017-09-27 | 2019-04-02 | 敦宏科技股份有限公司 | The optics for having dark current correcting function receives circuit and its dark current correction method |
| CN109560879B (en) * | 2017-09-27 | 2021-06-22 | 敦宏科技股份有限公司 | Optical receiving circuit with dark current correction function and dark current correction method thereof |
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| CN106330340B (en) | 2019-07-26 |
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