CN106328699B - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN106328699B
CN106328699B CN201510386621.2A CN201510386621A CN106328699B CN 106328699 B CN106328699 B CN 106328699B CN 201510386621 A CN201510386621 A CN 201510386621A CN 106328699 B CN106328699 B CN 106328699B
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gate
layer
semiconductor device
field plate
metal layer
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CN106328699A (en
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廖文甲
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Anchorage Semiconductor Co ltd
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Delta Electronics Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a semiconductor device which comprises a substrate, an active layer, a source electrode, a drain electrode, a grid electrode, a field plate, a first protective layer and a metal layer. The active layer is disposed on the substrate. The source and the drain are respectively electrically connected with the active layer. The grid electrode is arranged between the source electrode and the drain electrode and is arranged above the active layer. The field plate is arranged above the active layer and between the grid electrode and the drain electrode. The first protection layer covers the gate and the field plate. The metal layer is arranged on the first protective layer, arranged above the grid and the field plate and electrically connected with the source electrode. The semiconductor device of the present invention adjusts the gate-source capacitance (Cgs) through the metal layer.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device.
Background
A High Electron Mobility Transistor (HEMT) is a type of Field Effect Transistor (FET) and is widely used because it has high electron mobility and low resistance. The important component of the high electron mobility transistor is a heterostructure layer, which is composed of two materials with different energy gaps to replace the PN interface of the traditional field effect transistor. A commonly utilized combination of materials is aluminum gallium nitride (AlGaN) and gallium nitride (GaN). Due to the conduction band of the heterostructure layer composed of gan and gan forming the quantum well on the gan side, a two-dimensional electron gas (2DEG) is generated at the interface between gan and gan.
Disclosure of Invention
One aspect of the present invention provides a semiconductor device including a substrate, an active layer, a source electrode, a drain electrode, a gate electrode, a field plate, a first protection layer and a metal layer. The active layer is disposed on the substrate. The source and the drain are respectively electrically connected with the active layer. The grid electrode is arranged between the source electrode and the drain electrode and is arranged above the active layer. The field plate is arranged above the active layer and between the grid electrode and the drain electrode. The first protection layer covers the gate and the field plate. The metal layer is arranged on the first protective layer, arranged above the grid and the field plate and electrically connected with the source electrode.
In one or more embodiments, the gate has a first distance from the active layer, and the field plate has a second distance from the active layer, the second distance being less than the first distance.
In one or more embodiments, a portion of the first passivation layer disposed between the gate and the metal layer has a thickness less than 500 nm.
In one or more embodiments, a gap is formed between the gate and the field plate, and the metal layer covers the gap entirely.
In one or more embodiments, a side of the metal layer facing the source is located above the gate.
In one or more embodiments, a side of the metal layer facing the drain electrode is located above the field plate.
In one or more embodiments, the first distance is about 20 nm to 200 nm.
In one or more embodiments, the second distance is about 50 nanometers to 300 nanometers.
In one or more embodiments, the field plate is electrically connected to the source electrode.
In one or more embodiments, the field plate is electrically connected to the gate.
In one or more embodiments, the semiconductor device further includes a second protective layer disposed between the field plate and the active layer.
In one or more embodiments, the metal layer completely covers the gate.
In one or more embodiments, the horizontal distance between the metal layer and the drain is less than the horizontal distance between the field plate and the drain.
The semiconductor device of the above embodiment adjusts the gate-source capacitance (Cgs) by the metal layer.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
Wherein the reference numerals are as follows:
102: insulating region
105: buffer layer
110: substrate
120: active layer
122: channel layer
124: barrier layer
126: two-dimensional electron gas
130: source electrode
140: drain electrode
150: grid electrode
160: a field plate
170: first protective layer
175: second protective layer
180: metal layer
182. 184: side edge
190: p-type doped layer
D1, D2, D3, D4: horizontal distance
d 1: first distance
d 2: second distance
G: gap
T: thickness of
Detailed Description
In the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the various embodiments of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.
Fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor device includes a substrate 110, an active layer 120, a source electrode 130, a drain electrode 140, a gate electrode 150, a field plate 160, a first protection layer 170, and a metal layer 180. The active layer 120 is disposed on the substrate 110. The source 130 and the drain 140 are electrically connected to the active layer 120, respectively. For example, in fig. 1, the source 130 and the drain 140 are partially disposed in the active layer 120, but in other embodiments, the source 130 and the drain 140 may be disposed on the active layer 120. The gate 150 is disposed between the source 130 and the drain 140 and above the active layer 120. The gate 150 has a first distance d1 from the active layer 120. The field plate 160 is disposed over the active layer 120 and between the gate 150 and the drain 140. The field plate 160 and the active layer 120 have a second distance d2 therebetween, and the second distance d2 is smaller than the first distance d 1. The first protection layer 170 covers the gate 150 and the field plate 160. The metal layer 180 is disposed on the first passivation layer 170, disposed above the gate 150 and the field plate 160, and electrically connected to the source electrode 130.
In the semiconductor device of the present embodiment, the gate-source capacitance (Cgs) is adjusted by the metal layer 180, and the second distance d2 is smaller than the first distance d1, so that the breakdown voltage of the semiconductor device can be increased. In detail, in the present embodiment, a portion of the metal layer 180 is disposed above the gate 150, that is, a portion of the metal layer 180 overlaps the gate 150. Since the metal layer 180 is electrically connected to the source 130, a gate-source capacitance (Cgs) is formed between the metal layer and the gate 150. Such an arrangement increases the gate-source capacitance of the semiconductor device, and thus the Miller Ratio (which is inversely proportional to the gate-source capacitance) of the semiconductor device may be relatively reduced. The lower the miller ratio, the better the operating state of the semiconductor device, the easier it is to achieve high frequency operation, and the breakdown current value(s) can be minimized. On the other hand, a high electric field exists between the gate 150 and the active layer 120. As long as a source-drain voltage is applied to the semiconductor device, the electric field may rapidly increase to reach the breakdown voltage of the semiconductor device. However, in the present embodiment, since the field plate 160 is disposed between the gate 150 and the drain 140, and the second distance d2 is smaller than the first distance d1, i.e., the field plate 160 is lower than the gate 150, when the device is applied with a high source-drain voltage, a portion of the electric field can be effectively moved to the vicinity of the field plate 160, so that the electric field increase at the side of the gate 150 close to the drain 140 can be reduced, and thus the breakdown voltage of the semiconductor device can be raised.
In one embodiment, when metal layer 180 is present, the gate-source charge (qgs (th)) is about 1.1(nC/m) and the miller ratio is about 2.4. Also, when no metal layer 180 is present, the gate-source charge (qgs (th)) is about 1.8(nC/m) and the miller ratio is about 1.2.
In the present embodiment, the portion of the first passivation layer 170 disposed between the gate 150 and the metal layer 180 has a thickness T, and the thickness T is less than 500 nm. In other embodiments, the thickness T is less than 300 nanometers. In other embodiments, the thickness T is less than 100 nanometers. By adjusting the thickness T, the gate-source capacitance between the gate 150 and the metal layer 180 can be adjusted. In addition, when the coverage area between the gate 150 and the metal layer 180 is different, the gate-source capacitance between the gate 150 and the metal layer 180 may also be changed accordingly, so that a person skilled in the art may determine the coverage area between the gate 150 and the metal layer 180 according to actual situations.
In this embodiment, a gap G is formed between the gate 150 and the field plate 160, and the metal layer 180 covers the gap G completely. In other words, the metal layer 180 overlaps both the gate 150 and the field plate 160, and the edge of the metal layer 180 is not located in the gap G. Since the electric field is easily concentrated at the edge of the metal layer 180 (referred to as fringe field), in the present embodiment, since the metal layer 180 completely covers the gap G, i.e. the sides 182, 184 of the metal layer 180 are not located in the gap G, the metal layer 180 is prevented from generating a fringe field at the gap G to disturb the electric field distribution above the active layer 120, which may change the breakdown voltage of the semiconductor device.
In this embodiment, a side 182 of the metal layer 180 facing the source 130 is located above the gate 150. In other words, the horizontal distance D1 between the metal layer 180 and the source 130 is farther than the horizontal distance D2 between the gate 150 and the source 130. In the present embodiment, the metal layer 180 is not overlapped with the gate 150 and does not protrude from the side of the gate 150 facing the source 130, but the invention is not limited thereto. Fig. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the invention. In the present embodiment, the metal layer 180 completely covers the gate 150, i.e., the horizontal distance D1 may be equal to or less than the horizontal distance D2. Other details of the present embodiment are the same as those of fig. 1, and therefore, are not described again.
Referring back to fig. 1, in the present embodiment, a side 184 of the metal layer 180 facing the drain electrode 140 is located above the field plate 160. In other words, the horizontal distance D3 between the metal layer 180 and the drain 140 is farther than the horizontal distance D4 between the field plate 160 and the drain 140. In this embodiment, the metal layer 180 not only overlaps the field plate 160, but does not protrude from the side of the field plate 160 facing the drain electrode 140. This configuration allows the side 184 of the metal layer 180 to be separated from the active layer 120 by the field plate 160, so that the side 182 of the metal layer 180 does not generate a fringe electric field near the active layer 120, and thus does not disturb the electric field distribution near the active layer 120.
In the present embodiment, the field plate 160 is electrically connected to the source electrode 130, in other words, the field plate 160 and the metal layer 180 are both electrically connected to the source electrode 130, so that no additional capacitance is generated between the field plate 160 and the metal layer 180, and the field plate 160 is disposed between the gate 150 and the drain electrode 140, which also reduces the possible electrical influence between the gate 150 and the drain electrode 140. In some embodiments, the field plate 160 can be electrically connected to the source electrode 130 and/or the metal layer 180 by an external line or an interlayer penetrating structure, which is not limited in the present invention.
However, in other embodiments, the field plate 160 may be electrically connected to the gate 150, and thus another gate-source capacitance may be formed between the field plate 160 and the metal layer 180. The gate-source capacitance between the field plate 160 and the metal layer 180 can be changed by different thickness T of the first protection layer 170 and/or different coverage area between the field plate 160 and the metal layer 180. In some embodiments, the field plate 160 can be electrically connected to the gate 150 by an external line or an interlayer through structure, which is not limited by the invention.
In one or more embodiments, the active layer 120 includes a plurality of different nitride-based semiconductor layers to generate a two-dimensional electron gas (2DEG)126 at a heterojunction (heterojunction) as a conductive channel. For example, a via layer 122 and a barrier layer 124 can be used that are stacked on top of each other, wherein the barrier layer 124 is disposed on the via layer 122. With this structure, a two-dimensional electron gas 126 may exist at the interface between the channel layer 122 and the barrier layer 124. Thus, when the semiconductor device is in an on state, an on current between the source 130 and the drain 140 can flow along the interface between the channel layer 122 and the barrier layer 124. In some embodiments, the channel layer 122 may be a gallium nitride (GaN) layer, and the barrier layer 124 may be an aluminum gallium nitride (AlGaN) layer. On the other hand, the material of the substrate 110 is, for example, a silicon (silicon) substrate or a sapphire (sapphire) substrate, which is not limited by the invention. In this embodiment, the semiconductor device may further include a buffer layer 105 disposed between the active layer 120 and the substrate 110. In addition, the semiconductor device may further include an insulating region 102 surrounding the active layer 120. The insulating region 102 can prevent the generation of leakage current and increase the breakdown voltage.
In this embodiment, the semiconductor device further includes a P-type doped layer 190 disposed between the gate 150 and the active layer 120. The P-type doped layer 190 may be a layer for suppressing the two-dimensional electron gas 126 of the active layer 120 under the gate electrode 150, and thus the two-dimensional electron gas 126 under the P-type doped layer 190 is intercepted, which effect is present even in the absence of an applied voltage. Therefore, the semiconductor device of this embodiment mode is a normally-off (enhancement mode) device.
In this embodiment, the semiconductor device further includes a second protection layer 175 disposed between the field plate 160 and the active layer 120, i.e., the field plate 160 is disposed on the second protection layer 175. By varying the thickness of the second protection layer 175, the second distance d2 between the field plate 160 and the active layer 120 can be varied. In some embodiments, the first passivation layer 170 and the second passivation layer 175 may be aluminum oxide (Al)2O3) Aluminum nitride (AlN), silicon nitride (Si)3N4) Silicon dioxide (SiO)2) Hafnium oxide (HfO)2) Or any combination of the above.
In some embodiments, the first distance d1 may be about 20 nm to 200 nm, and the second distance d2 is about 50 nm to 300 nm, but the invention is not limited thereto. Basically, it is within the scope of the present invention to disperse the electric field of the gate 150 as long as the first distance d1 is greater than the second distance d2, i.e., the field plate 160 is lower than the gate 150.
The semiconductor device of the above embodiment adjusts the gate-source capacitance (Cgs) through the metal layer, and the breakdown voltage of the semiconductor device can be increased because the second distance is smaller than the first distance.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (13)

1. A semiconductor device, comprising:
a substrate;
an active layer disposed on the substrate;
a source and a drain electrically connected to the active layer respectively;
a grid electrode arranged between the source electrode and the drain electrode and above the active layer;
a field plate disposed above the active layer and between the gate and the drain;
a first protection layer covering the gate and the field plate; and
and a metal layer disposed on the first protective layer, disposed above the gate and the field plate, and electrically connected to the source electrode, wherein a horizontal distance between the metal layer and the source electrode is greater than a horizontal distance between the gate and the source electrode.
2. The semiconductor device of claim 1, wherein said gate has a first distance from said active layer and said field plate has a second distance from said active layer, said second distance being less than said first distance.
3. The semiconductor device of claim 1, wherein a portion of said first protective layer disposed between said gate and said metal layer has a thickness less than 500 nm.
4. The semiconductor device of claim 1, wherein said gate has a gap with said field plate, said metal layer completely covering said gap.
5. The semiconductor device of claim 1, wherein a side of said metal layer facing said source is located above said gate.
6. The semiconductor device of claim 1, wherein a side of said metal layer facing said drain electrode is located above said field plate.
7. The semiconductor device of claim 2, wherein said first distance is between 20 nm and 200 nm.
8. The semiconductor device of claim 2, wherein said second distance is between 50 nm and 300 nm.
9. The semiconductor device of claim 1, wherein said field plate is electrically connected to said source electrode.
10. The semiconductor device of claim 1, wherein said field plate is electrically connected to said gate.
11. The semiconductor device according to claim 1, further comprising: a second passivation layer disposed between the field plate and the active layer.
12. The semiconductor device of claim 1, wherein said metal layer completely covers said gate.
13. The semiconductor device of claim 1, wherein a horizontal distance between said metal layer and said drain is less than a horizontal distance between said field plate and said drain.
CN201510386621.2A 2015-07-03 2015-07-03 Semiconductor device with a plurality of semiconductor chips Active CN106328699B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227198A (en) * 2012-01-27 2013-07-31 富士通半导体股份有限公司 Compound semiconductor device and method of manufacturing the same
CN103456781A (en) * 2012-06-04 2013-12-18 英飞凌科技奥地利有限公司 Compound semiconductor transistor with self aligned gate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7573078B2 (en) * 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227198A (en) * 2012-01-27 2013-07-31 富士通半导体股份有限公司 Compound semiconductor device and method of manufacturing the same
CN103456781A (en) * 2012-06-04 2013-12-18 英飞凌科技奥地利有限公司 Compound semiconductor transistor with self aligned gate

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Effective date of registration: 20221107

Address after: No. 252, Shanying Road, Guishan District, Taoyuan City, Taiwan, China, China (6/F)

Patentee after: Anchorage Semiconductor Co.,Ltd.

Address before: Taoyuan County, Taiwan, China

Patentee before: DELTA ELECTRONICS, Inc.

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