CN106328542A - 薄膜晶体管的制备方法 - Google Patents

薄膜晶体管的制备方法 Download PDF

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CN106328542A
CN106328542A CN201611031040.8A CN201611031040A CN106328542A CN 106328542 A CN106328542 A CN 106328542A CN 201611031040 A CN201611031040 A CN 201611031040A CN 106328542 A CN106328542 A CN 106328542A
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thin film
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ito glass
film transistor
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林慧
匡鹏
叶旭
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

薄膜晶体管的制备方法,属于半导体显示技术领域,本发明包括下述步骤:1)ITO玻璃衬底基片清洗;2)制备Al2O3:PVP绝缘层:ITO玻璃衬底上旋涂Al2O3:PVP前驱体溶液,然后在200℃~250℃条件下退火,然后重复旋涂——退火至少一次,得到Al2O3:PVP绝缘层;3)制备有缘层:在气压低于3×10‑4Pa的环境中,对步骤2)处理后的ITO玻璃衬底基片进行蒸镀,蒸镀材料为Pentacene材料,得到有缘层薄膜;4)制备源极和漏极:以Au作为源极和漏极的电极材料,在步骤3)处理后的基片的有缘层薄膜上蒸镀制备源电极和漏电极,蒸镀的气压低于3×10‑4Pa。本发明采用燃烧法只需要较低的引导温度,自产生的高能量可实现在低温下将前驱体转化成相应的氧化物。

Description

薄膜晶体管的制备方法
技术领域
本发明属于半导体显示技术领域,涉及一种基于Al2O3:PVP绝缘层的薄膜晶体管的制备方法。
背景技术
薄膜晶体管(Thin Film Transistor,TFT)作为20世纪最伟大的发明之一,被广泛应用于诸多领域,在过去的十几年里已经成为电子平板显示行业的核心部件,其在射频电子标签、电子电路和传感器等方面的应用价值也备受关注。为满足电子产业的发展和商业化的需求,薄膜晶体管器件在尺寸上也不断追求微型化,在器件不断微型化的过程中,既要考虑短沟道效应,又要在较低的电压下尽量使沟道里富集较多的电荷,从而获得较高的输出电流。在薄膜晶体管中,高介电常数的绝缘层在增加电流密度的同时,保证了优异的绝缘性能。选择合适的介电材料,控制适当的膜厚以减少漏电流,则可以达到最优的器件性能。
金属氧化物作为高介电常数材料成为了研究热点,传统氧化物薄膜制备方法有化学气相沉积、原子力沉积和磁控溅射等,都需要昂贵的设备和维护费用。为实现低成本制备方式,溶液法被应用于薄膜晶体管制备。溶液法制备薄膜晶体管,相比于常规晶体管制备的优势在于,它可以在基底上实现薄膜的低温、均一、快速制备。溶液法操作简单,不仅能用于单个器件的制备,还可以用于制备大面积薄膜,一次性制备大量器件,有利于降低整个电路的造价。溶液法制备金属氧化物薄膜实现工艺和设备简单、成本低等有利条件,同时因金属氧化物较高的介电常数可实现器件在低电压下正常工作。然而,溶液法制备金属氧化物薄膜通常需要高于350℃的温度来使薄膜致密、纯净等,过高的退火温度导致其不能在大多数柔性基底制备。为实现在金属氧化物薄膜的低温、均一、快速制备,燃烧法成为了研究热点。燃烧法通过在金属盐中加入“燃料”(乙酰丙酮或尿素),加热分解过程发生化学放热反应,自产生的热提供了一个局部能量供给,消除对外部施加高温度的必要性。
绝缘层质量是影响薄膜晶体管性能的主要因素之一,材料的选择、制备方式对绝缘层质量有着至关重要的影响。Al2O3材料因具有绝缘性好、禁带宽度大、高介电常数、成本低、化学性能稳定、可溶液法制备薄膜等优点而被认为是良好的绝缘层材料,同时,掺入适量的PVP可以有效的降低薄膜表面极性和陷阱密度,使器件性能最优化。
发明内容
本发明所要解决的技术问题是,提供一种利用燃烧法实现在低温条件下制备高性能薄膜晶体管的方法。
本发明解决所述技术问题采用的技术方案是,薄膜晶体管的制备方法,其特征在于,包括下述步骤:
1)ITO玻璃衬底基片清洗;
2)制备Al2O3:PVP绝缘层:ITO玻璃衬底上旋涂Al2O3:PVP前驱体溶液,然后在200℃~250℃条件下退火,然后重复旋涂——退火至少一次,得到Al2O3:PVP绝缘层;
3)制备有缘层:在气压低于3×10-4Pa的环境中,对步骤2)处理后的ITO玻璃衬底基片进行蒸镀,蒸镀材料为Pentacene材料,得到厚度为50nm左右的有缘层薄膜;
4)制备源极和漏极:以Au作为源极和漏极的电极材料,在步骤3)处理后的基片的有缘层薄膜上蒸镀制备源电极和漏电极,蒸镀的气压低于3×10-4Pa。
进一步的,所述步骤1)包括:
(1.1)设置好超声仪参数:温度30℃,时间15min,功率70w;
(1.2)用无尘布沾上丙酮擦拭ITO玻璃衬底表面,直至肉眼观察无颗粒杂质;
(1.3)将擦洗干净的ITO玻璃衬底放入装有丙酮的烧杯中进行第一步超声清洗;
(1.4)用乙醇冲洗后再放入装有乙醇的烧杯中进行第二步清洗;
(1.5)用去离子水对ITO玻璃衬底进行第三步超声清洗;
(1.6)用氮气将ITO玻璃衬底吹干。
所述步骤2)中,200℃条件下退火40分钟。
所述步骤3)中,Pentacene材料加热升温至180℃,蒸镀速率为
所述步骤4)中,以的蒸镀速率,待厚度达到10nm之后,调整蒸镀速率至直到蒸镀结束。
本发明与现有技术相比,采用燃烧法只需要较低的引导温度,自产生的高能量可实现在低温下将前驱体转化成相应的氧化物。使用Al2O3:PVP绝缘层,高介电常数材料Al2O3可以增加载流子密度,减小漏电流,同时,掺入适量的PVP可以降低薄膜表面极性和陷阱密度,使器件性能最优化。
附图说明
图1为Si基板的薄膜晶体管的器件结构示意图。
图2为ITO玻璃基板的薄膜晶体管的器件结构示意图。
图3为器件结构:ITO/Al2O3:PVP/Pentacene/Au的转移特性曲线图。
图4为器件结构:Si/Al2O3:PVP/Pentacene/Au的转移特性曲线图。
具体实施方式
本发明提供了一种基于Al2O3:PVP绝缘层的薄膜晶体管的制备方法,包括以下步骤:
1)基片清洗:
(1.1)设置好超声仪参数:温度30℃,时间15min,功率70w;
(1.2)用无尘布沾上丙酮擦拭衬底表面,直到肉眼观察到无颗粒杂质为止。所述衬底为Si衬底或者ITO玻璃衬底;
(1.3)将擦洗干净的Si衬底或者ITO玻璃衬底放置在聚四氟乙烯基片架上,再放入装有丙酮的烧杯中进行第一步超声清洗;
(1.4)取出基片架,用乙醇冲洗后再放入装有乙醇的烧杯中进行第二步清洗;
(1.5)用去离子水对Si衬底或者ITO玻璃衬底进行第三步超声清洗。(6)用氮气将Si衬底或者ITO玻璃衬底吹干。
2)制备Al2O3:PVP绝缘层:将Al2O3:PVP前驱体溶液均匀滴注在Si衬底或者ITO玻璃衬底上,以2500rpm的转速旋涂30s,然后在200℃条件下退火40min。上述过程在相同条件下重复2次,得到所需的Al2O3:PVP绝缘层。
3)制备有缘层:采用真空蒸镀的方法制备,以Pentacene作为有缘层材料。首先将基片放入真空腔里,待蒸镀室气压低于3×10-4Pa以下,开始对Pentacene材料加热升温至180℃左右,以大约的蒸镀速率得到厚度为50nm的有缘层薄膜。
4)制备源极和漏极:以Au作为源极和漏极的电极材料,同样采用真空蒸镀的方法制备。将基片放入真空腔里,待蒸镀室气压低于3×10-4Pa以下,以的蒸镀速率,待厚度达到10nm之后,调整蒸镀速率至直到蒸镀结束。
步骤2)中Al2O3:PVP前驱体溶液的配制:
首先用电子天平称量225.1mg Al(NO3)3·9H2O装入玻璃瓶中,再用移液器抽取2ml二甲氧基乙醇溶剂移入装有Al(NO3)3·9H2O的玻璃瓶中,再加入120μl乙酰丙酮(C5H8O2)作为燃料和66μl氨水(NH4OH)用于平衡酸碱度,最后加入磁力搅拌子并放置在磁力搅拌台上搅拌12h,使溶液混合均匀。
步骤3)中Pentacene材料的特性:
Pentacene为p型有机小分子场效应材料,Pentacene是线形稠环芳香烃的典型代表,也是有机半导体材料中的佼佼者。其分子式为C22H14,最高占据轨道(HOMO)能级为-5.14eV,能级带隙(Eg)为1.77eV。
从图3和图4的转移特性曲线中可以看出,本发明利用燃烧法制备的基于Al2O3:PVP绝缘层的薄膜晶体管展现出了相当低的漏电流密度,开关比达到105,意味着器件具有更好的稳定性、抗干扰能力和更大的负载驱动能力。同时,较低的阈值电压可以更好的实现在低电压下工作。

Claims (5)

1.薄膜晶体管的制备方法,其特征在于,包括下述步骤:
1)ITO玻璃衬底基片清洗;
2)制备Al2O3:PVP绝缘层:ITO玻璃衬底上旋涂Al2O3:PVP前驱体溶液,然后在200℃~250℃条件下退火,然后重复旋涂——退火至少一次,得到Al2O3:PVP绝缘层;
3)制备有缘层:在气压低于3×10-4Pa的环境中,对步骤2)处理后的ITO玻璃衬底基片进行蒸镀,蒸镀材料为Pentacene材料,得到有缘层薄膜;
4)制备源极和漏极:以Au作为源极和漏极的电极材料,在步骤3)处理后的基片的有缘层薄膜上蒸镀制备源电极和漏电极,蒸镀的气压低于3×10-4Pa。
2.如权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述步骤1)包括:
(1.1)设置好超声仪参数:温度30℃,时间15min,功率70w;
(1.2)用无尘布沾上丙酮擦拭ITO玻璃衬底表面,直至肉眼观察无颗粒杂质;
(1.3)将擦洗干净的ITO玻璃衬底放入装有丙酮的烧杯中进行第一步超声清洗;
(1.4)用乙醇冲洗后再放入装有乙醇的烧杯中进行第二步清洗;
(1.5)用去离子水对ITO玻璃衬底进行第三步超声清洗;
(1.6)用氮气将ITO玻璃衬底吹干。
3.如权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述步骤2)中,200℃条件下退火40分钟。
4.如权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述步骤3)中,Pentacene材料加热升温至180℃,蒸镀速率为
5.如权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述步骤4)中,以的蒸镀速率,待厚度达到10nm之后,调整蒸镀速率至直到蒸镀结束。
CN201611031040.8A 2016-11-16 2016-11-16 薄膜晶体管的制备方法 Pending CN106328542A (zh)

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CN105408245A (zh) * 2013-07-25 2016-03-16 东丽株式会社 碳纳米管复合体、半导体元件和使用其的传感器
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