CN106328534A - Mos transistor and forming method thereof - Google Patents
Mos transistor and forming method thereof Download PDFInfo
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- CN106328534A CN106328534A CN201510387736.3A CN201510387736A CN106328534A CN 106328534 A CN106328534 A CN 106328534A CN 201510387736 A CN201510387736 A CN 201510387736A CN 106328534 A CN106328534 A CN 106328534A
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- 230000004888 barrier function Effects 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 28
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 176
- 238000002955 isolation Methods 0.000 claims description 83
- 239000000463 material Substances 0.000 claims description 68
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- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
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- 241000208340 Araliaceae Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
An MOS transistor and a forming method thereof are disclosed. The forming method of the MOS transistor comprises the following steps: providing a semiconductor base, wherein the semiconductor base includes a first semiconductor base and a second semiconductor base which is arranged on the surface of the first semiconductor base and protrudes from the first semiconductor base, and the top surface of the second semiconductor base is provided with a gate structure; forming a protective layer on the top surface and sidewall surface of the gate structure and on the sidewall surface of the second semiconductor base; etching the first semiconductor base with the protective layer as a mask to form a first trench; performing first ion implantation on the surface of the first semiconductor base at the bottom of the first trench to form a barrier layer; oxidizing the first semiconductor base at the bottom of the second semiconductor base and at the sides of the first trench with the barrier layer as a cover to form an isolating base; removing the barrier layer and the protective layer; and forming a source region and a drain region, wherein the source region and the drain region are respectively disposed in the first trench at the two sides of the gate structure. Through the MOS transistor forming method, the performance of the MOS transistor is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of MOS transistor and forming method thereof.
Background technology
MOS (Metal-oxide-semicondutor) transistor, be in modern integrated circuits most important element it
One, the basic structure of MOS transistor includes: Semiconductor substrate；It is positioned at the grid of semiconductor substrate surface
Structure, described grid structure includes: is positioned at the gate dielectric layer of semiconductor substrate surface and is positioned at gate medium
The gate electrode layer on layer surface；It is positioned at the source region of grid structure side and is positioned at the drain region of grid structure opposite side.
Doped with ion in described source region and drain region.
Along with the development of semiconductor technology, in integrated circuit, the size of device is more and more less, highly dense for realizing
Degree, high performance MOS transistor, the anti-break-through isolation between source region and drain region is more and more important, generally
The Semiconductor substrate of grid structure bottom section is injected contrary with source region, drain region dopant ion type
Ion, carries out anti-break-through isolation to the source region of grid structure side and the drain region of grid structure opposite side.
But the poor-performing of the MOS transistor formed in prior art.
Summary of the invention
The problem that the present invention solves is to provide a kind of MOS transistor and forming method thereof, improves MOS crystal
The performance of pipe.
For solving the problems referred to above, the present invention provides the forming method of a kind of MOS transistor, including: including:
Thering is provided quasiconductor pedestal, described quasiconductor pedestal includes the first quasiconductor pedestal and is positioned at the first quasiconductor lining
Bottom susceptor surface and protrude from the second quasiconductor pedestal of the first quasiconductor pedestal；Described second semiconductor-based
Seat top surface has grid structure；In grid structure top surface and sidewall surfaces, second semiconductor-based
Seat sidewall surfaces forms protective layer, and described protective layer exposes grid structure both sides the first quasiconductor pedestal
Surface；With described protective layer as mask, etch the first quasiconductor pedestal, form the first groove, described
One groove exposes the lower surface of part the second quasiconductor pedestal；Formation is positioned at the first trench bottom surfaces
Barrier layer, described barrier layer exposes the sidewall of the first groove；With barrier layer as overcover, to second
Quasiconductor base bottom, the first quasiconductor pedestal of the first groove sidepiece carry out oxidation processes, form isolation
Pedestal；Remove barrier layer and protective layer；After removing barrier layer and protective layer, form source region and drain region, institute
State source region and drain region lays respectively in the first groove of grid structure both sides.
Optionally, the method forming described first groove is wet-etching technology, and concrete technological parameter is:
The etching solution used is tetramethyl ammonium hydroxide solution, the percent by volume of tetramethyl ammonium hydroxide solution
Concentration is 10%～30%, and etching temperature is 50 degrees Celsius～90 degrees Celsius.
Optionally, the step forming described barrier layer is: the first quasiconductor pedestal to the first channel bottom
Surface carries out the first ion implanting；After first ion implanting, the first quasiconductor pedestal is carried out annealing treatment
Reason.
Optionally, the technological parameter of described first ion implanting is: the ion of employing is Nitrogen ion, injects
Ion energy is 2KeV～10KeV, and injection ion dose is 1E15atom/cm2～1E16atom/cm2, note
Entering angle is 5 degree～15 degree.
Optionally, described annealing is spike annealing, and the gas of employing is N2, temperature is 950 degrees Celsius
～1050 degrees Celsius.
Optionally, the material on described barrier layer is silicon nitride.
Optionally, the thickness on described barrier layer is 5nm～15nm.
Optionally, the method for described oxidation processes is dry oxidation technique, and concrete technological parameter is: adopt
Gas be O2, temperature is 500 degrees Celsius～800 degrees Celsius, and oxidization time is 20 minutes～60 minutes.
Optionally, the material of described isolation pedestal is silicon oxide.
Optionally, described isolation pedestal includes the first isolation pedestal and is positioned at the of the first isolation pedestal top
Two isolation pedestals, described first isolation pedestal is positioned in the first quasiconductor pedestal of the first groove sidepiece, institute
State the second isolation pedestal be positioned at the second quasiconductor base bottom and protrude to raceway groove.
Optionally, wet-etching technology etching is used to remove described barrier layer and described protective layer, concrete
Technological parameter is: the etching solution of employing is phosphoric acid solution, and the concentration of volume percent of phosphoric acid solution is
70%～90%, etching temperature is 120 degrees Celsius～200 degrees Celsius.
Optionally, described protective layer includes the first protective layer and the second protective layer, described first protective layer position
In grid structure top surface, described second protective layer is positioned at gate structure sidewall surface and the second quasiconductor
Base side wall surface.
Optionally, the material of described protective layer is silicon nitride.
Optionally, the step forming described source region and drain region is: in the first groove of grid structure both sides
Form source-drain area material layer；Adulterate the second ion to source-drain area material layer.
Optionally, epitaxial growth technology is used to form described source-drain area material layer.
Optionally, when MOS transistor to be formed is nmos pass transistor, described source-drain area material layer
Material be carborundum；When MOS transistor to be formed is PMOS transistor, described source-drain area material
The material of layer is SiGe.
Optionally, when MOS transistor to be formed is nmos pass transistor, described second ion is N
Type ion；When MOS transistor to be formed is PMOS transistor, described second ion is p-type ion.
Present invention also offers a kind of MOS transistor, it is characterised in that including: semiconductor substrate structure；
It is positioned at the grid structure on semiconductor substrate structure surface；Lay respectively at grid structure semiconductor substrates on two sides knot
Source region in structure and drain region；It is positioned at the raceway groove in grid structure base semiconductor substrate structure；It is positioned at raceway groove
Bottom and the isolation pedestal protruded to raceway groove, described isolation pedestal is between described source region and drain region.
Optionally, the material of described isolation pedestal is silicon oxide.
Compared with prior art, technical scheme has the advantage that
The forming method of the MOS transistor that the present invention provides, owing to defining isolation in quasiconductor pedestal
Pedestal, on the one hand, enhance anti-break-through between the source region and the drain region that lay respectively at grid structure both sides every
From performance, effectively prevent described source region and drain region from break-through occurring；On the other hand, isolation pedestal is to raceway groove
Produce stress, improve the mobility of carrier in raceway groove.
The MOS transistor that the present invention provides, described MOS transistor includes laying respectively at grid structure two
The source region of side and drain region；It is positioned at trench bottom and the isolation pedestal protruded to raceway groove, described isolation pedestal position
Between described source region and drain region, on the one hand, enhance source region and the leakage laying respectively at grid structure both sides
Anti-break-through isolation performance between district, effectively prevents described source region and drain region from break-through occurring；On the other hand,
Isolation pedestal protrudes to raceway groove, it is possible to raceway groove is produced stress, improves the mobility of carrier in raceway groove.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of MOS transistor in one embodiment of the invention.
Fig. 2 to Figure 15 is that in another embodiment of the present invention, the cross-section structure of MOS transistor forming process shows
It is intended to.
Figure 16 is the cross-sectional view of MOS transistor in further embodiment of this invention.
Detailed description of the invention
As described in background, the poor-performing of the MOS transistor that prior art is formed.
One embodiment of the invention provides a kind of method forming MOS transistor, including: quasiconductor is provided
Substrate；Semiconductor substrate is carried out anti-break-through ion implanting, forms anti-punch through region in the semiconductor substrate；
Forming grid structure at semiconductor substrate surface, grid structure is positioned at above anti-punch through region；Form source region
And drain region, described source region and drain region lay respectively in the Semiconductor substrate of grid structure both sides.
Described anti-punch through region is positioned at the bottom of raceway groove.
Acting as of described anti-punch through region: prevent described source region and drain region from break-through occurring.
Research finds, the Performance And Reliability of the MOS transistor formed in above-described embodiment is poor.Fig. 1 is
The structural representation of the MOS transistor that said method is formed.With reference to Fig. 1, MOS transistor includes: half
Conductor substrate 100；It is positioned at the grid structure 120 on Semiconductor substrate 100 surface；It is positioned at grid structure 120
The source region 130 of side and the drain region 131 being positioned at grid structure 120 opposite side；It is positioned at grid structure 120 end
Anti-punch through region 110 in portion's Semiconductor substrate 100.When MOS transistor is nmos pass transistor,
Doped with N-type ion in source region 130 and drain region 131, doped with p-type ion in anti-punch through region 110；
When MOS transistor is PMOS transistor, doped with p-type ion in source region 130 and drain region 131,
Doped with N-type ion in anti-punch through region 110.Along with the integrated level of semiconductor technology increases further,
Grid structure 120 density increases, and the channel length bottom grid structure 120 becomes more and more less, described
Distance between source region 130 and drain region 131 reduces so that described source region 130 and drain region 131 are easily sent out
Raw break-through, so that the degradation of MOS transistor.
Another embodiment of the present invention provides the forming method of a kind of MOS transistor, including: provide and partly lead
Susceptor body, described quasiconductor pedestal includes the first quasiconductor pedestal and is positioned at the first Semiconductor substrate pedestal table
Face and protrude from the second quasiconductor pedestal of the first quasiconductor pedestal；Described second quasiconductor pedestal top table
Mask has grid structure；At grid structure top surface and sidewall surfaces, the second quasiconductor pedestal sidewall table
Face forms protective layer, and described protective layer exposes the surface of grid structure both sides the first quasiconductor pedestal；With
Described protective layer is mask, etches the first quasiconductor pedestal, forms the first groove, and described first groove is sudden and violent
The lower surface of exposed portion the second quasiconductor pedestal；Form the barrier layer being positioned at the first trench bottom surfaces,
Described barrier layer exposes the sidewall of the first groove；With barrier layer as overcover, to the second quasiconductor pedestal
Bottom, the first quasiconductor pedestal of the first groove sidepiece carry out oxidation processes, form isolation pedestal；Remove
Barrier layer and protective layer；After removing barrier layer and protective layer, form source region and drain region, described source region and leakage
District lays respectively in the first groove of grid structure both sides.
Owing to defining isolation pedestal in quasiconductor pedestal, on the one hand, enhance and lay respectively at grid knot
Anti-break-through isolation performance between source region and the drain region of structure both sides, effectively prevents described source region and drain region from sending out
Raw break-through；On the other hand, isolation pedestal produces stress to raceway groove, improves the migration of carrier in raceway groove
Rate.Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
With reference to Fig. 2, it is provided that Semiconductor substrate 200, form grid structure 220 on Semiconductor substrate 200 surface,
Grid structure 220 top surface has the first protective layer 230.
Described Semiconductor substrate 200 provides technique platform for being subsequently formed MOS transistor.
Described Semiconductor substrate 200 can be monocrystal silicon, polysilicon or non-crystalline silicon；Semiconductor substrate 200
Can also be the semi-conducting materials such as silicon, germanium, SiGe, GaAs；Described Semiconductor substrate 200 is permissible
It is body material, it is also possible to be composite construction, such as silicon-on-insulator；Described Semiconductor substrate 200 is all right
It is other semi-conducting material, illustrates the most one by one.In the present embodiment, described Semiconductor substrate 200
Material be silicon.In the present embodiment, also include: in Semiconductor substrate 200, form shallow trench isolation junction
Structure (not shown), the active area that the isolation of described fleet plough groove isolation structure is adjacent.
Grid structure 220 includes gate dielectric layer (not shown) and the position being positioned at Semiconductor substrate 200 surface
Gate electrode layer (not shown) in gate dielectric layer.
In embodiments of the invention, the material of described gate dielectric layer is silicon oxide, the material of described gate electrode layer
Material is polysilicon.
In other embodiments, it is also possible to be: the material of described gate dielectric layer is high K dielectric material, institute
The material stating gate electrode layer is metal.Described gate dielectric layer and described gate electrode layer constitute metal gate structure.
After described metal gate structure uses, grid technique is formed, and the concrete step forming metal gate structure is:
It is initially formed dummy gate structure, follow-up removal dummy gate structure, forms grid in original dummy gate structure position
Dielectric layer and the gate electrode layer being positioned at gate dielectric layer surface.
Acting as of described first protective layer 230: during subsequent etching Semiconductor substrate 200 and
Follow-up carry out the first ion implanting during, protect grid structure 220.
The material of described first protective layer 230 is silicon nitride, silicon oxynitride or silicon oxide.In the present embodiment,
The material of described first protective layer 230 is silicon nitride.
First protective layer 230 is positioned at the top surface of grid structure 220.
The method forming grid structure 220 and the first protective layer 230 is: on Semiconductor substrate 200 surface
Deposition gate structure material layer；The first protection material layer (not shown) is formed on gate structure material layer surface；
Patterned photoresist, described patterned photoresist definition grid is formed in the first protection material surface
Structure 220 and the position of the first protective layer 230；The photoresist graphically changed is grid described in mask etching
Structural material and the first protection material layer, form grid structure 220 and the first protective layer 230.
After forming grid structure 220 and the first protective layer 230, dry method degumming process or wet method is used to remove photoresist
Technique removes the photoresist of the first protective layer 230 surface graphics.
In the present embodiment, dry method degumming process is used to remove described patterned photoresist.
With reference to Fig. 3, etching removes the Semiconductor substrate 200 (reference of grid structure 220 two side portions thickness
Fig. 2), quasiconductor pedestal is formed.
With grid structure 220 and the first protective layer 230 as mask, use anisotropic plasma etch
The Semiconductor substrate 200 of technique etching grid structure 220 two side portions thickness, forms quasiconductor pedestal, tool
The technological parameter of body is: etching gas includes NF3, HBr and N2, NF3Flow be
The flow of 10sccm～100sccm, HBr is 100sccm～500sccm, N2Flow be
5sccm～200sccm, etching cavity pressure is 2mtoor～50mtorr, and source radio-frequency power is 100 watts～1000
Watt, biasing radio-frequency power is 100 watts～500 watts.
Described quasiconductor pedestal includes the first quasiconductor pedestal 201 and is positioned at the first quasiconductor pedestal 201 table
Face and protrude from the second quasiconductor pedestal 202 of the first quasiconductor pedestal 201.
In the present embodiment, described first quasiconductor pedestal 201 and the second quasiconductor pedestal 202 are by partly leading
Obtain after body substrate 200 etching, here for being easy to subsequent descriptions and understanding, by the quasiconductor after etching
Substrate 200 is divided into two parts (first quasiconductor pedestal 201 and the second quasiconductor pedestal 202) to be described by.
After forming the first quasiconductor pedestal 201 and the second quasiconductor pedestal 202, described grid structure 220 is positioned at
The top surface of the second quasiconductor pedestal 202.
With reference to Fig. 4, formed in grid structure 220 sidewall surfaces and the second quasiconductor pedestal 202 sidewall surfaces
Second protective layer 231, the second protective layer 231 exposes grid structure 220 both sides the first quasiconductor pedestal
The surface of 201.
Acting as of described second protective layer 231: in the process of subsequent etching the first semiconductor base 201
In and follow-up carry out the first ion implanting during, protect grid structure 220.
The material of described second protective layer 231 can be silicon nitride, silicon oxynitride or silicon oxide.This enforcement
In example, the material of described second protective layer 231 is silicon nitride.
The step forming the second protective layer 231 is: is formed and covers the first protective layer 230 surface, grid knot
The of structure 220 sidewall, the second quasiconductor pedestal 202 sidewall surfaces and the first quasiconductor pedestal 201 surface
Two protections material layer (not shown)；Use anisotropic dry etch process etching the second protection material layer,
Until exposing the first protective layer 230 and surface of the first quasiconductor pedestal 201.Above-mentioned steps completes it
After, form the second protective layer 231, described second protective layer 231 be positioned at grid structure 220 sidewall surfaces and
Second quasiconductor pedestal 202 sidewall surfaces.
In embodiments of the invention, described first protective layer 230 and the second protective layer 231 collectively form guarantor
Sheath, described protective layer is positioned at grid structure 220 top surface and sidewall surfaces, the second quasiconductor pedestal
202 sidewall surfaces, in order to protect grid structure not to be damaged in subsequent technique.
With reference to Fig. 5, with the first protective layer 230 and the second protective layer 231 as mask, etch the first quasiconductor
Pedestal 201, forms the first groove 240, and described first groove 240 exposes part the second quasiconductor pedestal
The lower surface of 202.
The method forming described first groove 240 is wet-etching technology, or first carries out dry etching then
Carry out wet-etching technology.
In the present embodiment, using wet-etching technology to form the first groove 240, concrete technological parameter is:
The etching solution used is tetramethyl ammonium hydroxide solution, the percent by volume of tetramethyl ammonium hydroxide solution
Concentration is 10%～30%, and etching temperature is 50 degrees Celsius～90 degrees Celsius.
Wet-etching technology is used to form the first groove 240, it is possible to Simplified flowsheet step.
With reference to Fig. 6 and Fig. 7, form the barrier layer 250 being positioned at the first groove 240 lower surface, described resistance
Barrier 250 exposes the first groove 240 sidewall.
Acting as of described barrier layer 250: follow-up the first quasiconductor pedestal to the first groove 240 sidepiece
During 201 carry out oxidation processes, prevent from the first quasiconductor pedestal 201 below barrier layer 250 is entered
Row oxidation, behind follow-up removal barrier layer 250, can use epitaxial growth technology at the first quasiconductor pedestal
201 surfaces form source region or drain region.
Factor of both the selection consideration on described barrier layer 250: the process on follow-up removal barrier layer 250
In, do not remove the isolation pedestal of the first groove 240 sidewall；During carrying out described oxidation processes,
Prevent from the first quasiconductor pedestal 201 below barrier layer 250 is aoxidized.Therefore the material on barrier layer 250
Material needs different with the material of the isolation pedestal being subsequently formed.The material on described barrier layer 250 can be nitrogen
SiClx or silicon oxynitride.
In the present embodiment, the material on described barrier layer 250 is silicon nitride.
The thickness on described barrier layer 250 is 5nm～15nm.
In the present embodiment, the thickness on described barrier layer 250 is 5nm, 10nm or 15nm.
The method forming described barrier layer 250 is: to the first quasiconductor pedestal bottom the first groove 240
201 surfaces carry out the first ion implanting；After first ion implanting, the first quasiconductor pedestal is annealed
Process.
Wherein, the technological parameter of described first ion implanting is: the injection ion of employing is Nitrogen ion, note
Entering energy is 2KeV～10KeV, and implantation dosage is 1E15atom/cm2～1E16atom/cm2, implant angle
It it is 5 degree～15 degree.Described implant angle is the angle between Semiconductor substrate 200 normal.
It should be noted that in actual process, the implant angle selected about the first ion implanting is permissible
Actual size according to the first quasiconductor pedestal 201 and the second quasiconductor pedestal 202 determines, is not limited to
Above-mentioned scope.
Described annealing is spike annealing, and its technological parameter is: the gas of employing is N2, temperature is 950
Degree Celsius～1050 degrees Celsius.
In one embodiment, with reference to Fig. 6, to the first quasiconductor pedestal 201 bottom the first groove 240
Whole surface carries out the first ion implanting, forms barrier layer 250.
In another embodiment, with reference to Fig. 7, semiconductor-based to the part first bottom the first groove 240
Seat 201 surfaces carry out the first ion implanting, form barrier layer 250.
It should be noted that the first quasiconductor pedestal 201 part surface bottom the first groove 240 is entered
Row the first ion implanting, can reduce the difficulty that technique realizes.
It should be noted that in other embodiments, other method can be used to form barrier layer 250.
With reference to Fig. 8 and Fig. 9, wherein, Fig. 8 is the schematic diagram formed on the basis of Fig. 6, and Fig. 9 is at figure
On the basis of 7 formed schematic diagram, with barrier layer 250 as overcover, to bottom the second quasiconductor pedestal 202,
First quasiconductor pedestal 201 of the first groove 240 sidepiece carries out oxidation processes, forms isolation pedestal 260.
The position on the barrier layer 250 owing to being formed in abovementioned steps is different, aoxidizes the isolation base of formation herein
The position of seat 260 is also slightly different.Concrete, if described barrier layer 250 was positioned at for first groove 240 end
The first whole surface of quasiconductor pedestal 201 (with reference to Fig. 6) in portion, refer to Fig. 8, carries out described oxidation
The first quasiconductor pedestal 201 surface bottom the first groove 240 will not be carried out oxygen during process
Changing, the isolation pedestal 260 of formation is positioned at bottom the second quasiconductor pedestal 202 and the first groove 240 side
In the first quasiconductor pedestal 201 in portion；If described barrier layer 250 is positioned at bottom the first groove 240
The part surface (with reference to Fig. 7) of semiconductor pedestal 201, refer to Fig. 9, carries out described oxidation processes
During, at unsheltered first quasiconductor pedestal 201 table of the first groove 240 bottom barrier 250
Face also can be oxidized, and the isolation base part of formation is positioned at bottom the second quasiconductor pedestal 202 and first
In first quasiconductor pedestal 201 of groove 240 sidepiece, part is positioned at the first groove 240 bottom barrier
250 unsheltered first quasiconductor pedestal 201 surfaces.
The material of described isolation pedestal 260 is silicon oxide.
It is wet process oxidation technology or dry oxidation work that described oxidation processes forms the technique of isolation pedestal 260
Skill.
In the present embodiment, use dry oxidation to the first quasiconductor pedestal 201 of the first groove 240 sidepiece,
Carry out oxidation processes bottom second quasiconductor pedestal 202, form isolation pedestal 260, concrete technological parameter
For: the gas of employing is O2, temperature is 500 degrees Celsius～800 degrees Celsius, and oxidization time is 20 minutes
～60 minutes.
First quasiconductor pedestal 201 of the first groove 240 sidepiece is carried out oxidation processes, formed first every
From pedestal, described first isolation pedestal is positioned in the first quasiconductor pedestal 201 of the first groove 240 sidepiece；
To carrying out oxidation processes bottom the second quasiconductor pedestal 202, formed second isolation pedestal, described second every
The bottom of the first quasiconductor pedestal 202 it is positioned at from structure.
Described first isolation pedestal and described second isolation pedestal constitute isolation pedestal 260.Wherein, first every
Acting as from pedestal: isolate the source region laying respectively at grid structure 220 both sides and drain region being subsequently formed,
Increase the anti-break-through isolation performance in described source region and drain region, prevent from laying respectively at grid structure 220 both sides
Break-through is there is between source region and drain region.And for the effect of the second isolation pedestal, due to described second isolation
Pedestal is for obtaining after carrying out oxidation processes bottom the second quasiconductor pedestal 202, and the second of formation isolates base
Seat protrudes to grid structure 220 so that the second isolation pedestal forms stress to the second quasiconductor pedestal 202,
Follow-up in the first groove 240, form source region or drain region after, part the second quasiconductor pedestal 202 constitutes MOS
The raceway groove of transistor, the second isolation pedestal produces stress, improves carrier in channel region channel region
Mobility, thus improve the performance of MOS transistor.
In sum, acting as of pedestal 260 is isolated: what isolation was subsequently formed lays respectively at grid structure
The source region of 220 both sides and drain region, prevent from occurring between described source region and drain region break-through；Channel region is produced
Stress, improves the mobility of carrier in raceway groove.
It should be noted that to bottom the second quasiconductor pedestal 202, the first of the first groove 240 sidepiece
After quasiconductor pedestal 201 carries out oxidation processes, the isolation pedestal 260 of Fig. 8 and Fig. 9 signal is for be all subject to
Isolation pedestal 260 to oxidation.
In other embodiments, isolation pedestal 260 can be the isolation pedestal 260 that part is aoxidized, ginseng
Examining Figure 10 and Figure 11, wherein, Figure 10 is the schematic diagram formed on the basis of Fig. 6, and Figure 11 is at Fig. 7
On the basis of formed schematic diagram, Figure 10 and Figure 11 signal isolation pedestal 260 part aoxidized, every
Not oxidized from the central area of pedestal 260, owing to the central area of isolation pedestal 260 is not oxidized,
During MOS transistor work, can form substrate current, described substrate current is by isolation pedestal 260
Heart region and flow to the first quasiconductor pedestal 201, described substrate current can take away partial heat so that
MOS transistor temperature operationally reduces, thus improves the stability of MOS transistor performance.
With reference to Figure 12 and Figure 13, wherein, Figure 12 is the schematic diagram formed on the basis of Fig. 8, and Figure 13 is figure
The schematic diagram formed on the basis of 9, removes barrier layer 250 (with reference to Fig. 8 and Fig. 9) and described protective layer.
Remove acting as of barrier layer 250: expose the first quasiconductor pedestal 201 below barrier layer 250,
Follow-up the first quasiconductor pedestal 201 surface epitaxial growth source-drain area material layer bottom the first groove 240.
Remove acting as of described protective layer 250: remove the protective layer of the second quasiconductor pedestal 202 sidewall,
Follow-up form source region and drain region respectively in the second quasiconductor pedestal 202 both sides.
The method removing described protective layer 250 uses wet-etching technology, dry etch process or dry method
The etching technics that etching and wet etching combine.
In the present embodiment, wet-etching technology is used to remove described barrier layer 250 and described protective layer, tool
The etch process parameters of body is: the etching solution of employing is phosphoric acid solution, the percent by volume of phosphoric acid solution
Concentration is 70%～90%, and etching temperature is 120 degrees Celsius～200 degrees Celsius.
With reference to Figure 14 and Figure 15, wherein, Figure 14 is the schematic diagram formed on the basis of Figure 12, Figure 15
For the schematic diagram formed on the basis of Figure 13, form source region 270 and drain region 271, described source region 270 He
Drain region 271 lays respectively in the first groove 240 of grid structure 220 both sides.
The forming step in described source region 270 and drain region 271 is: at the first ditch of grid structure 220 both sides
Forming source-drain area material layer in groove 240, adulterate the second ion to source-drain area material layer.
Wherein, the formation process of described source-drain area material layer is epitaxial growth technology.
The material of described source-drain area material layer selects with the type of MOS transistor to be formed is correlated with, specifically
Ground, when MOS transistor to be formed is nmos pass transistor, the material of described source-drain area material layer
For carborundum, when MOS transistor to be formed is PMOS transistor, described source-drain area material layer
Material is SiGe.
When described source-drain area material layer is SiGe, the technological parameter of epitaxial growth source-drain area material layer is:
The gas used is GeH4、SiH4And H2, GeH4Flow be 800sccm～1000sccm, SiH4's
Flow is 800sccm～1000sccm, H2Flow be 50sccm～1000sccm, chamber pressure is
5mtorr～50mtorr, temperature is 500 degrees Celsius～800 degrees Celsius.
When described source-drain area material layer is carborundum, the technological parameter of epitaxial growth source-drain area material layer is:
The gas used is SiH4、CH4And H2, SiH4Flow be 800sccm～1000sccm, CH4Stream
Amount is 800sccm～1000sccm, H2Flow be 50sccm～1000sccm, chamber pressure is
5mtorr～50mtorr, temperature is 500 degrees Celsius～800 degrees Celsius.
In other embodiments, other technique can be used to form source-drain area material layer.
The selection of described second ion is also relevant, specifically, when treating to the type of the MOS transistor formed
The MOS transistor formed is when being nmos pass transistor, and described second ion is N-type ion, such as P or
As；When MOS transistor to be formed is PMOS transistor, described second ion is p-type ion,
Such as B or In.
It should be noted that in other embodiments of the invention, it is also possible to forming source-drain area material layer
While in situ doping the second ion.
Further embodiment of this invention additionally provides a kind of MOS transistor, brilliant with reference to Figure 16, described MOS
Body pipe includes: semiconductor substrate structure 300；It is positioned at the grid structure on semiconductor substrate structure 300 surface
310；Lay respectively at the source region 303 in grid structure 310 semiconductor substrates on two sides structure 300 and drain region 304；
It is positioned at the raceway groove 301 in grid structure 310 base semiconductor substrate structure 300；It is positioned at bottom raceway groove 301
And to the isolation pedestal 302 of raceway groove 301 protrusion, described isolation pedestal 302 is positioned at source region 303 and drain region
Between 304.
The material of described isolation pedestal 302 is silicon oxide.
Form the method for source region 303 and drain region 304 and grid structure 310 with reference to the source in previous embodiment
District 270 and drain region 271 and the forming method of grid structure 220；Described semiconductor substrate structure 300
Forming method is with reference to the forming method of quasiconductor pedestal in previous embodiment；Form described isolation pedestal 302
Method with reference to Figure 10 isolates the forming method of pedestal 260, no longer describe in detail.
Owing to having isolation pedestal 302 in semiconductor substrate structure 300, described isolation pedestal 302 is positioned at
Protruding bottom raceway groove 301 and to raceway groove 301, described isolation pedestal 302 can produce stress to raceway groove 301,
Improve the mobility of carrier in raceway groove；Described isolation pedestal 302 is positioned at source region 303 and drain region 304
Between, described source region 303 and drain region 304 lay respectively at grid structure 310 both sides so that lay respectively at
Anti-break-through isolation performance between source region 303 and the drain region 304 of grid structure 310 both sides strengthens.
It should be noted that the central area of the isolation pedestal 302 of Figure 16 signal is identical with the material of sidepiece.
In other embodiments, the central area of isolation pedestal 302 and the material of sidepiece differ, isolation
The material of pedestal 302 central area is identical with the material of semiconductor substrate structure 300, MOS transistor work
When making, can form substrate current, described substrate current is by isolating central area and the flow direction of pedestal 302
Bottom semiconductor substrate structure 300, described substrate current can take away partial heat so that MOS crystal
Pipe temperature operationally reduces, thus improves the stability of MOS transistor performance.
To sum up, the invention have the advantages that
The forming method of the MOS transistor that the present invention provides, owing to defining isolation in quasiconductor pedestal
Pedestal, on the one hand, enhance anti-break-through between the source region and the drain region that lay respectively at grid structure both sides every
From performance, effectively prevent described source region and drain region from break-through occurring；On the other hand, isolation pedestal is to raceway groove
Produce stress, improve the mobility of carrier in raceway groove.
The MOS transistor that the present invention provides, owing to there is formation isolation pedestal at semiconductor substrate structure,
Described isolation pedestal is positioned at trench bottom and protrudes to raceway groove, and described isolation pedestal can produce stress to raceway groove,
Improve the mobility of carrier in raceway groove；Described isolation pedestal between source region and drain region, described source
District and drain region lay respectively at grid structure both sides so that lay respectively at source region and the drain region of grid structure both sides
Between anti-break-through isolation performance strengthen.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (19)
1. the forming method of a MOS transistor, it is characterised in that including:
Thering is provided quasiconductor pedestal, described quasiconductor pedestal includes the first quasiconductor pedestal and is positioned at the first quasiconductor
Substrate seating surface and protrude from the second quasiconductor pedestal of the first quasiconductor pedestal；Described the second half lead
Susceptor body top surface has grid structure；
Protective layer is formed at grid structure top surface and sidewall surfaces, the second quasiconductor pedestal sidewall surfaces,
Described protective layer exposes the surface of grid structure both sides the first quasiconductor pedestal；
With described protective layer as mask, etch the first quasiconductor pedestal, form the first groove, described first ditch
Groove exposes the lower surface of part the second quasiconductor pedestal；
Forming the barrier layer being positioned at the first trench bottom surfaces, described barrier layer exposes the sidewall of the first groove；
With barrier layer as overcover, to the second quasiconductor base bottom, the first quasiconductor of the first groove sidepiece
Pedestal carries out oxidation processes, forms isolation pedestal；
Remove barrier layer and protective layer；
After removing barrier layer and protective layer, forming source region and drain region, described source region and drain region lay respectively at grid
In first groove of structure both sides.
The forming method of MOS transistor the most according to claim 1, it is characterised in that formed described
The method of the first groove is wet-etching technology, and concrete technological parameter is: the etching solution of employing is
Tetramethyl ammonium hydroxide solution, the concentration of volume percent of tetramethyl ammonium hydroxide solution is
10%～30%, etching temperature is 50 degrees Celsius～90 degrees Celsius.
The forming method of MOS transistor the most according to claim 1, it is characterised in that formed described
The step on barrier layer is: the first semiconductor-based seating face of the first channel bottom is carried out the first ion note
Enter；After first ion implanting, the first quasiconductor pedestal is made annealing treatment.
The forming method of MOS transistor the most according to claim 3, it is characterised in that described first
The technological parameter of ion implanting is: the ion of employing is Nitrogen ion, injects ion energy and is
2KeV～10KeV, injection ion dose is 1E15atom/cm2～1E16atom/cm2, implant angle is
5 degree～15 degree.
The forming method of MOS transistor the most according to claim 3, it is characterised in that described annealing
Being processed as spike annealing, the gas of employing is N2, temperature is 950 degrees Celsius～1050 degrees Celsius.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described stop
The material of layer is silicon nitride.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described stop
The thickness of layer is 5nm～15nm.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described oxidation
The method processed is dry oxidation technique, and concrete technological parameter is: the gas of employing is O2, temperature
Being 500 degrees Celsius～800 degrees Celsius, oxidization time is 20 minutes～60 minutes.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described isolation
The material of pedestal is silicon oxide.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described isolation
Pedestal includes the first isolation pedestal and is positioned at the second isolation pedestal at the first isolation pedestal top, described the
One isolation pedestal is positioned in the first quasiconductor pedestal of the first groove sidepiece, described second isolation pedestal position
Protrude in the second quasiconductor base bottom and to raceway groove.
The forming method of 11. MOS transistors according to claim 1, it is characterised in that use wet method
Etching technics etching removes described barrier layer and described protective layer, and concrete technological parameter is: employing
Etching solution is phosphoric acid solution, and the concentration of volume percent of phosphoric acid solution is 70%～90%, etching temperature
It it is 120 degrees Celsius～200 degrees Celsius.
The forming method of 12. MOS transistors according to claim 1, it is characterised in that described protection
Layer includes that the first protective layer and the second protective layer, described first protective layer are positioned at grid structure top surface,
Described second protective layer is positioned at gate structure sidewall surface and the second quasiconductor pedestal sidewall surfaces.
The forming method of 13. MOS transistors according to claim 1, it is characterised in that described protection
The material of layer is silicon nitride.
The forming method of 14. MOS transistors according to claim 1, it is characterised in that formed described
The step in source region and drain region is: form source-drain area material layer in the first groove of grid structure both sides；
Adulterate the second ion to source-drain area material layer.
The forming method of 15. MOS transistors according to claim 14, it is characterised in that use extension
Growth technique forms described source-drain area material layer.
The forming method of 16. MOS transistors according to claim 14, it is characterised in that when to be formed
MOS transistor when being nmos pass transistor, the material of described source-drain area material layer is carborundum；
When MOS transistor to be formed is PMOS transistor, the material of described source-drain area material layer is
SiGe.
The forming method of 17. MOS transistors according to claim 14, it is characterised in that when to be formed
MOS transistor when being nmos pass transistor, described second ion is N-type ion；When to be formed
MOS transistor when being PMOS transistor, described second ion is p-type ion.
18. 1 kinds of MOS transistors, it is characterised in that including:
Semiconductor substrate structure；
It is positioned at the grid structure on semiconductor substrate structure surface；
Lay respectively at the source region in grid structure semiconductor substrates on two sides structure and drain region；
It is positioned at the raceway groove in grid structure base semiconductor substrate structure；
Being positioned at trench bottom and the isolation pedestal protruded to raceway groove, described isolation pedestal is positioned at described source region and leakage
Between district.
19. MOS transistors according to claim 18, it is characterised in that the material of described isolation pedestal
For silicon oxide.
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| CN103985633A (en) * | 2013-02-08 | 2014-08-13 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of PMOS transistor |
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| JPH05206455A (en) * | 1992-01-27 | 1993-08-13 | Nec Corp | Semiconductor device and its manufacture |
| JPH05235345A (en) * | 1992-02-20 | 1993-09-10 | Nec Corp | Semiconductor device and manufacture thereof |
| US20070069300A1 (en) * | 2005-09-29 | 2007-03-29 | International Business Machines Corporation | Planar ultra-thin semiconductor-on-insulator channel mosfet with embedded source/drain |
| CN102456579A (en) * | 2010-10-27 | 2012-05-16 | 国际商业机器公司 | Semiconductor device having localized extremely thin silicon on insulator channel region |
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