CN106328488B - Super junction power device and preparation method thereof - Google Patents
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- CN106328488B CN106328488B CN201510359333.8A CN201510359333A CN106328488B CN 106328488 B CN106328488 B CN 106328488B CN 201510359333 A CN201510359333 A CN 201510359333A CN 106328488 B CN106328488 B CN 106328488B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 9
- 230000035945 sensitivity Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 146
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract
The invention provides a super junction power device and a preparation method thereof, wherein the preparation method comprises the following steps: sequentially forming a first epitaxial layer and a second epitaxial layer on a substrate; forming a groove vertical to the substrate in the first epitaxial layer and the second epitaxial layer, wherein the depth of the groove is equal to the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer; forming a third epitaxial layer in the groove corresponding to the first epitaxial layer, wherein the thickness of the first epitaxial layer is consistent with that of the third epitaxial layer so as to form a first-stage super junction power unit; and forming a fourth epitaxial layer above the third epitaxial layer, wherein the thickness of the second epitaxial layer is consistent with that of the fourth epitaxial layer so as to form a second-stage super junction power unit, and further completing the preparation process of the super junction power device. According to the technical scheme, the super-junction power device with the super-junction structure compatible with two doping concentrations is formed, the requirement of low on-resistance is met, and meanwhile the requirement of low sensitivity to charge imbalance is met.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a super junction power device and a preparation method thereof.
Background
At present, in the related art, the super junction power device is widely applied to the semiconductor device products due to its high breakdown voltage and low conduction characteristic, but with the continuous development of the semiconductor processing technology, the super junction power device still has the following defects:
(1) the super junction power device with low doping concentration has large on-resistance, so that the static power consumption of the super junction power device is large;
(2) the super junction power device with high doping concentration has high sensitivity to charge imbalance, so that the change amplitude of the breakdown voltage of the super junction power device is large.
Therefore, how to design a super junction type power device to simultaneously ensure high sensitivity to charge imbalance and high on-resistance becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention provides a preparation method of a super junction power device and a novel super junction power device based on the problems.
In view of this, the first aspect of the present invention provides a method for manufacturing a super junction power device, including: sequentially forming a first epitaxial layer and a second epitaxial layer on a substrate; forming a trench perpendicular to the substrate in the first epitaxial layer and the second epitaxial layer, wherein the depth of the trench is equal to the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer; forming a third epitaxial layer in a groove corresponding to the first epitaxial layer, wherein the thickness of the first epitaxial layer is consistent with that of the third epitaxial layer, so as to form a first-stage super junction power unit; and forming a fourth epitaxial layer above the third epitaxial layer, wherein the thickness of the second epitaxial layer is consistent with that of the fourth epitaxial layer so as to form a second-stage super junction power unit, and further completing the preparation process of the super junction power device.
In the technical scheme, the first super-junction power unit and the second super-junction power unit are formed, and the super-junction power units with two ion concentrations are compatibly prepared in the same device, so that low on-resistance and low sensitivity to charge imbalance are realized simultaneously, and the application range and the device reliability of the super-junction power device are further improved.
In the above technical solution, preferably, the forming of the first epitaxial layer includes the following specific steps: sequentially forming a first silicon-based layer corresponding to the first epitaxial layer on the substrate in a chemical vapor deposition mode; and carrying out first ion implantation treatment and annealing treatment on the first silicon-based layer to form a first epitaxial layer.
In the technical scheme, the first epitaxial layer is formed through chemical vapor deposition, so that the initial compensation of charges on the channel of the device is realized, the reliability of the device is further improved, and meanwhile, the production efficiency of the device is improved.
In the above technical solution, preferably, the forming of the first epitaxial layer includes the following specific steps: and forming the first epitaxial layer on the substrate through an epitaxial process.
In the technical scheme, the first epitaxial layer is formed through an epitaxial process, so that the structural reliability of the first epitaxial layer is ensured, and the reliability of the device is further improved.
In the above technical solution, preferably, the forming of the second epitaxial layer includes the following specific steps: and carrying out secondary ion implantation treatment and annealing treatment on the second silicon base layer to form a second epitaxial layer.
In the technical scheme, the second epitaxial layer is formed through chemical vapor deposition, so that the second-step compensation of charges on the channel of the device is realized, the reliability of the device is further improved, and meanwhile, the production efficiency of the device is improved.
In the above technical solution, preferably, the forming of the second epitaxial layer includes the following specific steps: forming the second epitaxial layer on the first epitaxial layer by an epitaxial process.
In the technical scheme, the second epitaxial layer is formed through an epitaxial process, so that the structural reliability of the second epitaxial layer is ensured, and the reliability of the device is further improved.
In the above technical solution, preferably, the forming the first epitaxial layer and the second epitaxial layer in sequence includes the following specific steps: sequentially forming a first silicon-based layer corresponding to the first epitaxial layer on the substrate in a chemical vapor deposition mode; carrying out first ion implantation treatment on the first silicon base layer; forming a second silicon-based layer corresponding to the second epitaxial layer on the first silicon-based layer in a chemical vapor deposition manner; performing second ion implantation treatment on the second silicon base layer; and annealing the first silicon-based layer and the second silicon-based layer to form the first epitaxial layer and the second epitaxial layer respectively, wherein the dosage of the first ion implantation treatment is lower than that of the second ion implantation treatment.
In the technical scheme, through the steps, the ion concentrations of the first epitaxial layer and the second epitaxial layer are controlled more accurately, and the reliability of the device is further ensured.
In the above technical solution, preferably, the method further includes: the ion concentration of the first epitaxial layer is controlled to be lower than that of the second epitaxial layer, and the ion concentration of the third epitaxial layer is controlled to be lower than that of the fourth epitaxial layer, wherein the ions of the first epitaxial layer, the second epitaxial layer and the substrate are first ions, the ions of the third epitaxial layer and the fourth epitaxial layer are second ions, and the types of the first ions are opposite to those of the second ions.
In the technical scheme, the ion concentrations and implantation doses of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer and the fourth epitaxial layer are controlled, so that the first super-junction power unit and the second super-junction power unit with different doping concentrations are compatibly prepared, and the characteristics of low on-resistance and low sensitivity to charge imbalance of the device are realized simultaneously.
The second aspect of the invention provides a super junction power device, which is prepared by adopting the preparation method of the super junction power device according to any one of the technical schemes.
In the technical scheme, the super-junction power device prepared by the preparation method realizes low sensitivity of the super-junction power unit with low doping concentration to charge unbalance and the characteristic of low on-resistance of the super-junction power unit with high doping concentration, and improves the practicability and reliability of the device.
In the above technical solution, preferably, the ion concentration of the first epitaxial layer is lower than the ion concentration of the second epitaxial layer.
In the foregoing technical solution, preferably, an ion concentration of the third epitaxial layer is lower than an ion concentration of the fourth epitaxial layer.
By the technical scheme, the low sensitivity of the super-junction power unit with low doping concentration to charge unbalance and the characteristic of low on-resistance of the super-junction power unit with high doping concentration are realized, and the practicability and reliability of the device are improved.
Drawings
Fig. 1 shows a cross-sectional schematic view of a process for manufacturing a super junction power device according to an embodiment of the present invention;
fig. 2 shows a cross-sectional schematic view of a process for manufacturing a super junction power device according to another embodiment of the present invention;
fig. 3 shows a cross-sectional schematic view of a manufacturing process of a super junction power device according to yet another embodiment of the present invention;
fig. 4 shows a cross-sectional schematic view of a manufacturing process of a super junction power device according to yet another embodiment of the present invention;
fig. 5 shows a schematic flow diagram of a method of manufacturing a superjunction power device according to an embodiment of the present invention.
Detailed Description
So that the manner in which the above recited objects, features and advantages of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.
Various embodiments of a process for manufacturing a superjunction power device according to an embodiment of the present invention are specifically described below with reference to fig. 1 to 5.
The first embodiment is as follows:
the device structures in fig. 1-4 and their corresponding numbering designations are: 1 substrate, 2 first epitaxial layer, 3 second epitaxial layer, 4 third epitaxial layer, 5 fourth epitaxial layer.
As shown in fig. 1, a first epitaxial layer 2 and a second epitaxial layer 3 are formed on a substrate 1.
As shown in fig. 2, the first epitaxial layer 2 and the second epitaxial layer 3 are etched to form a trench, the bottom of which is the surface layer of the substrate 1.
As shown in fig. 3, a third epitaxial layer 4 is formed in the trench, wherein the horizontal positions and thicknesses of the third epitaxial layer and the first epitaxial layer are the same, and the first epitaxial layer 2 and the third epitaxial layer 4 also form the first super junction power cell.
As shown in fig. 4, a fourth epitaxial layer 5 is formed in the trench, wherein the horizontal positions and thicknesses of the fourth epitaxial layer 5 and the second epitaxial layer 3 are the same, and the second epitaxial layer 3 and the fourth epitaxial layer 5 also form a second superjunction power cell.
Example two:
as shown in fig. 1 to 5, a method for manufacturing a super junction power device according to an embodiment of the present invention includes: step 502, forming a first epitaxial layer 2 and a second epitaxial layer 3 on a substrate 1 in sequence; step 504, forming a trench perpendicular to the substrate 1 in the first epitaxial layer 2 and the second epitaxial layer 3, wherein the depth of the trench is equal to the sum of the thicknesses of the first epitaxial layer 2 and the second epitaxial layer 3; step 506, forming a third epitaxial layer 4 in a groove corresponding to the first epitaxial layer 2, wherein the thickness of the first epitaxial layer 2 is consistent with that of the third epitaxial layer 4, so as to form a first-stage super junction power unit; and step 508, forming a fourth epitaxial layer 5 above the third epitaxial layer 4, wherein the thickness of the second epitaxial layer 3 is consistent with that of the fourth epitaxial layer 5, so as to form a second-stage super junction power unit, and further complete the preparation process of the super junction power device.
In the technical scheme, the first super-junction power unit and the second super-junction power unit are formed, and the super-junction power units with two ion concentrations are compatibly prepared in the same device, so that low on-resistance and low sensitivity to charge imbalance are realized simultaneously, and the application range and the device reliability of the super-junction power device are further improved.
In the above technical solution, preferably, the forming of the first epitaxial layer 2 includes the following specific steps: sequentially forming a first silicon-based layer corresponding to the first epitaxial layer 2 on the substrate 1 by means of chemical vapor deposition; and carrying out first ion implantation treatment and annealing treatment on the first silicon base layer to form a first epitaxial layer 2.
In the technical scheme, the first epitaxial layer 2 is formed by chemical vapor deposition, so that the initial compensation of charges on the channel of the device is realized, the reliability of the device is further improved, and meanwhile, the production efficiency of the device is improved.
In the above technical solution, preferably, the forming of the first epitaxial layer 2 includes the following specific steps: the first epitaxial layer 2 is formed on the substrate 1 by an epitaxial process.
In the technical scheme, the first epitaxial layer 2 is formed through an epitaxial process, so that the structural reliability of the first epitaxial layer 2 is ensured, and the reliability of the device is further improved.
In the above technical solution, preferably, the forming of the second epitaxial layer 3 includes the following specific steps: and carrying out secondary ion implantation treatment and annealing treatment on the second silicon base layer to form a second epitaxial layer 3.
In the technical scheme, the second epitaxial layer 3 is formed by chemical vapor deposition, so that the second-step compensation of charges on the channel of the device is realized, the reliability of the device is further improved, and meanwhile, the production efficiency of the device is improved.
In the above technical solution, preferably, the forming of the second epitaxial layer 3 includes the following specific steps: the second epitaxial layer 3 is formed on the first epitaxial layer 2 by an epitaxial process.
In the technical scheme, the second epitaxial layer 3 is formed through an epitaxial process, so that the structural reliability of the second epitaxial layer 3 is ensured, and the reliability of the device is further improved.
In the above technical solution, preferably, the forming of the first epitaxial layer 2 and the second epitaxial layer 3 in sequence includes the following specific steps: sequentially forming a first silicon-based layer corresponding to the first epitaxial layer 2 on the substrate 1 by means of chemical vapor deposition; carrying out first ion implantation treatment on the first silicon base layer; forming a second silicon-based layer corresponding to the second epitaxial layer 3 on the first silicon-based layer by means of chemical vapor deposition; performing second ion implantation treatment on the second silicon base layer; and annealing the first silicon-based layer and the second silicon-based layer to form the first epitaxial layer 2 and the second epitaxial layer 3 respectively, wherein the dosage of the first ion implantation treatment is lower than that of the second ion implantation treatment.
In the technical scheme, through the steps, the ion concentrations of the first epitaxial layer 2 and the second epitaxial layer 3 are controlled more accurately, and the reliability of the device is further ensured.
In the above technical solution, preferably, the method further includes: the ion concentration of the first epitaxial layer 2 is controlled to be lower than that of the second epitaxial layer 3, and the ion concentration of the third epitaxial layer 4 is controlled to be lower than that of the fourth epitaxial layer 5, wherein the ions of the first epitaxial layer 2, the second epitaxial layer 3 and the substrate 1 are first ions, the ions of the third epitaxial layer 4 and the fourth epitaxial layer 5 are second ions, and the types of the first ions are opposite to the types of the second ions.
In the technical scheme, the ion concentrations and implantation doses of the first epitaxial layer 2, the second epitaxial layer 3, the third epitaxial layer 4 and the fourth epitaxial layer 5 are controlled, so that the first super-junction power unit and the second super-junction power unit with different doping concentrations are compatibly prepared, and the characteristics of low on-resistance and low sensitivity to charge imbalance of the device are realized simultaneously.
The second aspect of the invention provides a super junction power device, which is prepared by adopting the preparation method of the super junction power device according to any one of the technical schemes.
In the technical scheme, the super-junction power device prepared by the preparation method realizes low sensitivity of the super-junction power unit with low doping concentration to charge unbalance and the characteristic of low on-resistance of the super-junction power unit with high doping concentration, and improves the practicability and reliability of the device.
In the above technical solution, preferably, the ion concentration of the first epitaxial layer 2 is lower than the ion concentration of the second epitaxial layer 3.
In the above technical solution, preferably, the ion concentration of the third epitaxial layer 4 is lower than the ion concentration of the fourth epitaxial layer 5.
The technical scheme of the invention is explained in detail with reference to the accompanying drawings, and in consideration of how to design a super junction type power device in the related technology to simultaneously ensure low sensitivity to charge imbalance and high on resistance, the invention provides a preparation method of the super junction type power device and a novel super junction type power device.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A method for preparing a super junction power device is characterized by comprising the following steps:
sequentially forming a first epitaxial layer and a second epitaxial layer on a substrate;
forming a trench perpendicular to the substrate in the first epitaxial layer and the second epitaxial layer, wherein the depth of the trench is equal to the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer;
forming a third epitaxial layer in a groove corresponding to the first epitaxial layer, wherein the thickness of the first epitaxial layer is consistent with that of the third epitaxial layer, so as to form a first-stage super junction power unit;
forming a fourth epitaxial layer above the third epitaxial layer, wherein the thickness of the second epitaxial layer is consistent with that of the fourth epitaxial layer, so as to form a second-stage super junction power unit, and further complete the preparation process of the super junction power device;
the first epitaxial layer and the third epitaxial layer form the first-stage super-junction power unit, the second epitaxial layer and the fourth epitaxial layer form the second-stage super-junction power unit, and the ion concentrations of the first-stage super-junction power unit and the second-stage super-junction power unit are different;
controlling the ion concentration of the first epitaxial layer to be lower than that of the second epitaxial layer, and controlling the ion concentration of the third epitaxial layer to be lower than that of the fourth epitaxial layer,
the first epitaxial layer, the second epitaxial layer and the substrate are ions of a first type, the third epitaxial layer and the fourth epitaxial layer are ions of a second type, and the types of the ions of the first type are opposite to the types of the ions of the second type.
2. The method for preparing the super junction power device according to claim 1, wherein the step of forming the first epitaxial layer comprises the following specific steps:
sequentially forming a first silicon-based layer corresponding to the first epitaxial layer on the substrate in a chemical vapor deposition mode;
and carrying out first ion implantation treatment and annealing treatment on the first silicon-based layer to form a first epitaxial layer.
3. The method for preparing the super junction power device according to claim 1, wherein the step of forming the first epitaxial layer comprises the following specific steps:
and forming the first epitaxial layer on the substrate through an epitaxial process.
4. The method for preparing the super junction power device according to claim 2, wherein the step of forming the second epitaxial layer comprises the following specific steps:
forming a second silicon-based layer corresponding to the second epitaxial layer on the first silicon-based layer in a chemical vapor deposition manner;
and carrying out secondary ion implantation treatment and annealing treatment on the second silicon base layer to form a second epitaxial layer.
5. The method for preparing the super junction power device according to claim 4, wherein the step of forming the second epitaxial layer comprises the following specific steps:
forming the second epitaxial layer on the first epitaxial layer by an epitaxial process.
6. The method for preparing the super junction power device according to claim 5, wherein the first epitaxial layer and the second epitaxial layer are formed in sequence, and the method comprises the following specific steps:
forming a first silicon-based layer corresponding to the first epitaxial layer on the substrate in a chemical vapor deposition mode;
carrying out first ion implantation treatment on the first silicon base layer;
forming a second silicon-based layer corresponding to the second epitaxial layer on the first silicon-based layer in a chemical vapor deposition manner;
performing second ion implantation treatment on the second silicon base layer;
annealing the first and second silicon-based layers to form the first and second epitaxial layers, respectively,
wherein the dosage of the first ion implantation treatment is lower than that of the second ion implantation treatment.
7. A super junction power device prepared by the method for preparing the super junction power device according to any one of claims 1 to 6.
8. The superjunction power device of claim 7, wherein the ion concentration of the first epitaxial layer is lower than the ion concentration of the second epitaxial layer.
9. The superjunction power device of claim 7 or 8, wherein an ion concentration of the third epitaxial layer is lower than an ion concentration of the fourth epitaxial layer.
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| JP2005019898A (en) * | 2003-06-27 | 2005-01-20 | Denso Corp | Semiconductor substrate and its manufacturing method |
| CN101853786A (en) * | 2005-10-06 | 2010-10-06 | 胜高股份有限公司 | Method for manufacturing semiconductor substrate |
| CN101989553A (en) * | 2009-08-07 | 2011-03-23 | 上海华虹Nec电子有限公司 | Method for manufacturing lengthwise region of CoolMOS |
| CN102479805A (en) * | 2010-11-30 | 2012-05-30 | 比亚迪股份有限公司 | Super junction semiconductor element and manufacture method thereof |
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| JP3973395B2 (en) * | 2001-10-16 | 2007-09-12 | 株式会社豊田中央研究所 | Semiconductor device and manufacturing method thereof |
| CN102456575A (en) * | 2010-10-28 | 2012-05-16 | 上海华虹Nec电子有限公司 | Making method for semiconductor device with super-junction structure and device structure |
| TWI469351B (en) * | 2011-11-29 | 2015-01-11 | Anpec Electronics Corp | Power transistor device with super junction and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005019898A (en) * | 2003-06-27 | 2005-01-20 | Denso Corp | Semiconductor substrate and its manufacturing method |
| CN101853786A (en) * | 2005-10-06 | 2010-10-06 | 胜高股份有限公司 | Method for manufacturing semiconductor substrate |
| CN101989553A (en) * | 2009-08-07 | 2011-03-23 | 上海华虹Nec电子有限公司 | Method for manufacturing lengthwise region of CoolMOS |
| CN102479805A (en) * | 2010-11-30 | 2012-05-30 | 比亚迪股份有限公司 | Super junction semiconductor element and manufacture method thereof |
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