CN106325360A - Apparatus and method for dynamic clock adjustment - Google Patents
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Abstract
本发明公开了一种动态时钟调整的装置和方法,该装置应用于一即时计算系统,包含:一研判计时器,检测即时计算系统执行一任务的一任务时间,并且计算任务时间与一即时系统周期的一时间差;一控制器,接收时间差,并且根据时间差与一参考时间来产生一控制信号;以及一时钟产生器,接收控制信号来产生调整的系统时钟,以提供给即时计算系统。本发明可实现及时地动态调整系统时钟来改善即时计算系统的计算效率。
The invention discloses a device and method for dynamic clock adjustment. The device is applied to a real-time computing system and includes: a judgment timer, detecting a task time when the real-time computing system performs a task, and calculating the task time and a real-time system a time difference of the cycle; a controller that receives the time difference and generates a control signal based on the time difference and a reference time; and a clock generator that receives the control signal to generate an adjusted system clock to provide a real-time computing system. The present invention can dynamically adjust the system clock in time to improve the computing efficiency of the real-time computing system.
Description
技术领域technical field
本发明是涉及即时计算系统技术领域,特别涉及一种动态时钟调整的装置和方法。The invention relates to the technical field of real-time computing systems, in particular to a device and method for dynamic clock adjustment.
背景技术Background technique
现有的数位即时计算系统需要时钟驱动来执行资料的计算或处理,若时钟越快速当然越快可以处理完成,但是并非每个状况都需要最高速的工作时钟,越高速的时钟可能越会耗电。理想上,只要满足计算及时完成且预留一点点剩余时间是最经济的方式。Existing digital real-time computing systems need to be driven by a clock to perform data calculation or processing. The faster the clock, the faster the processing can be completed, but not every situation requires the highest speed working clock, and the higher the clock speed, the more consumption Electricity. Ideally, it is the most economical way as long as the calculation is completed in time and a little remaining time is reserved.
一般即时计算系统是由预设的状况去调整时钟,例如使用控制器针对任务(Task)的计算需求将系统时钟产生器(CLOCK GENERATOR)调到预设的值来产生时钟。此种方法是属于开路控制的方式,无法作到动态省电的要求。A general real-time computing system adjusts the clock according to a preset condition, for example, a controller is used to adjust a system clock generator (CLOCK GENERATOR) to a preset value to generate a clock according to the computing requirements of a task. This method is an open-circuit control method, which cannot meet the requirement of dynamic power saving.
另一种调整时钟的方法是运用操作系统(Operating System,OS)中的讯息来调整系统时钟。带有操作系统的计算系统,其操作系统会获得一个中央处理器负载(CPU LOADING)值,因此针对CPU LOADING值来调整中央处理器时钟。此方法虽然可以做动态的调整时钟,但是无法保证其及时性。Another way to adjust the clock is to use the information in the Operating System (OS) to adjust the system clock. For a computing system with an operating system, the operating system will obtain a CPU LOADING value, so the CPU clock is adjusted according to the CPU LOADING value. Although this method can dynamically adjust the clock, it cannot guarantee its timeliness.
上述这些方法无法满足即时计算系统的及时地动态调整时钟的需求。本揭露提出一种动态时钟调整的技术,经由得到的资讯,闭回路控制的方式及时地动态调整系统时钟。The above-mentioned methods cannot meet the requirement of a real-time computing system to dynamically adjust the clock in a timely manner. This disclosure proposes a technology for dynamic clock adjustment, which dynamically adjusts the system clock in a timely manner in a closed-loop control manner through the obtained information.
发明内容Contents of the invention
根据本发明的一个方面,提供了一种动态时钟调整的装置,应用于一即时计算系统,此装置包含:一研判计时器,检测此即时计算系统执行一任务的一任务时间,并且计算此任务时间与一即时系统周期的一时间差;一控制器,接收该时间差,并且根据此时间差与一参考时间来产生一控制信号;以及一时钟产生器,接收此控制信号来产生调整的系统时钟,以提供给此即时计算系统。According to one aspect of the present invention, a device for dynamic clock adjustment is provided, which is applied to a real-time computing system, and the device includes: a research and judgment timer, which detects a task time for the real-time computing system to perform a task, and calculates the task A time difference between time and an instant system cycle; a controller, receiving the time difference, and generating a control signal according to the time difference and a reference time; and a clock generator, receiving the control signal to generate an adjusted system clock, to provided to this instant computing system.
在一个可选的实施方式中,研判计时器包含一计数器,根据即时计算系统执行任务的时钟进行计数来检测任务时间。In an optional embodiment, the judging timer includes a counter, which detects the task time by counting according to the clock of the real-time computing system executing the task.
在一个可选的实施方式中,研判计时器还包含一计算器或一计数器来计算任务时间与即时系统周期的时间差。In an optional implementation, the judging timer further includes a calculator or a counter to calculate the time difference between the task time and the real-time system period.
在一个可选的实施方式中,控制器是一比较器,比较时间差与参考时间来产生控制信号。In an optional embodiment, the controller is a comparator, which compares the time difference with a reference time to generate a control signal.
根据本发明的另一个方面,提供了一种动态时钟调整的方法,应用于一即时计算系统,此方法包含:检测此即时计算系统执行一任务的一任务时间;计算此任务时间与一即时系统周期的一时间差;使用一控制器,根据此时间差与一参考时间来产生一控制信号;以及使用一时钟产生器,接收此控制信号来产生调整的系统时钟,以提供给此即时计算系统。According to another aspect of the present invention, a method for dynamic clock adjustment is provided, which is applied to a real-time computing system. The method includes: detecting a task time when the real-time computing system executes a task; calculating the task time and a real-time system A time difference of the period; a controller is used to generate a control signal according to the time difference and a reference time; and a clock generator is used to receive the control signal to generate an adjusted system clock to provide to the real-time computing system.
在一个可选的实施方式中,所述方法使用一计数器,根据即时计算系统执行任务的时钟进行计数来检测任务时间。In an optional implementation, the method uses a counter to detect the task time by counting according to the clock of the real-time computing system executing the task.
在一个可选的实施方式中,所述方法使用一计算器或一计数器来计算任务时间与即时系统周期的时间差。In an optional implementation, the method uses a calculator or a counter to calculate the time difference between the task time and the real-time system cycle.
在一个可选的实施方式中,控制器是一比较器,比较时间差与参考时间来产生控制信号。In an optional embodiment, the controller is a comparator, which compares the time difference with a reference time to generate a control signal.
本发明提出一种动态时钟调整的技术,经由得到的信息,闭回路控制的方式及时地动态调整系统时钟。The present invention proposes a dynamic clock adjustment technology, through which the system clock is dynamically adjusted in a closed-loop control manner through the obtained information.
附图说明Description of drawings
图1是与本发明的一实施例的一示意图,说明一种动态时钟调整的装置。FIG. 1 is a schematic diagram of an embodiment of the present invention, illustrating a dynamic clock adjustment device.
图2是与本发明的一实施例的一示意图,说明第一图中的研判计时器。FIG. 2 is a schematic diagram of an embodiment of the present invention, illustrating the judgment timer in FIG. 1 .
图3是与本发明的一实施例的一示意图,说明控制器产生一控制信号。FIG. 3 is a schematic diagram of an embodiment of the present invention, illustrating that a controller generates a control signal.
图4是与本发明的一实施例的一示意图,说明时钟产生器接收该控制信号来产生系统时钟。FIG. 4 is a schematic diagram of an embodiment of the present invention, illustrating that the clock generator receives the control signal to generate the system clock.
图5是与本发明的一实施例的一示意图,说明一种动态时钟调整的方法。FIG. 5 is a schematic diagram of an embodiment of the present invention, illustrating a dynamic clock adjustment method.
其中,附图标记说明如下:Wherein, the reference signs are explained as follows:
100 动态时钟调整的装置100 Devices for Dynamic Clock Adjustment
110 研判计时器110 Judgment Timer
111 任务时间111 mission time
112 即时系统周期112 real-time system cycles
113 时间差113 time difference
120 控制器120 controller
121 参考时间121 Reference time
122 控制信号122 control signal
130 时钟产生器130 clock generator
131 系统时钟131 System Clock
510 检测即时计算系统执行一任务的一任务时间510 Detect a task time when the real-time computing system executes a task
520 计算任务时间与一即时系统周期的一时间差520 Calculate the time difference between task time and a real-time system cycle
530 使用一控制器,根据此时间差与一参考时间来产生一控制信号530 using a controller to generate a control signal according to the time difference and a reference time
540 使用一时钟产生器,接收此控制信号来产生调整的系统时钟,以提供给即时计算系统The 540 uses a clock generator to receive this control signal to generate an adjusted system clock for the real-time computing system
具体实施方式detailed description
下面参考伴随的附图,详细说明根据本发明的实施例,以使本领域技术人员易于了解。所述的创作可以采用多种变化的实施方式,当不能只限定于这些实施例。本发明省略已公知部分(well-known part)的描述,并且相同的参考号于本发明中代表相同的元件。Embodiments according to the present invention will be described in detail below with reference to the accompanying drawings so that those skilled in the art can easily understand. The described creation can be implemented in various variations, but should not be limited to these examples. The present invention omits descriptions of well-known parts, and the same reference numerals denote the same elements in the present invention.
本发明提出一种动态时钟调整的技术,及时地动态调整系统时钟来改善即时计算系统的计算效率。图1是本发明的一实施例的一示意图,说明一种动态时钟调整的装置。如图1所示,此装置100包含一一研判计时器110、一控制器120以及一时钟产生器130,其中研判计时器110检测即时计算系统执行一任务的一任务时间111,并且计算任务时间与一即时系统周期112的一时间差113;控制器120接收时间差113,并且根据该时间差113与一参考时间121来产生一控制信号122;时钟产生器130,接收该控制信号122来产生调整的系统时钟131,以提供给即时计算系统。The invention proposes a dynamic clock adjustment technology, which dynamically adjusts the system clock in time to improve the computing efficiency of the real-time computing system. FIG. 1 is a schematic diagram of an embodiment of the present invention, illustrating a dynamic clock adjustment device. As shown in Figure 1, this device 100 comprises one by one research and judge timer 110, a controller 120 and a clock generator 130, wherein research and judge timer 110 detects a task time 111 that real-time computing system executes a task, and calculates task time A time difference 113 with an instant system cycle 112; the controller 120 receives the time difference 113, and generates a control signal 122 according to the time difference 113 and a reference time 121; the clock generator 130 receives the control signal 122 to generate an adjusted system A clock 131 is provided to the real-time computing system.
根据图1中动态时钟调整的装置的实施例,其中研判计时器110检测即时计算系统执行一任务的一任务时间111,并且计算任务时间111与一即时系统周期112的一时间差113。图2是本发明的一实施例的一示意图,说明图1中的研判计时器。如图2所示,研判计时器110可以包含例如,但不限于一计数器,根据一即时计算系统执行一任务的时钟进行计数而获得任务时间111。According to the embodiment of the device for dynamic clock adjustment in FIG. 1 , the judgment timer 110 detects a task time 111 when the real-time computing system executes a task, and calculates a time difference 113 between the task time 111 and a real-time system period 112 . FIG. 2 is a schematic diagram of an embodiment of the present invention, illustrating the judgment timer in FIG. 1 . As shown in FIG. 2 , the judging timer 110 may include, for example, but not limited to a counter, which counts according to a clock of a real-time computing system executing a task to obtain the task time 111 .
研判计时器110还可以包含例如,但不限于一计算器(或计数器)来计算该任务时间111与一即时系统周期112的一时间差113。即时系统周期112是即时系统执行任务所需时间的上限,例如是执行每秒192K取样的音频信号处理的任务,则即时系统周期112为(1/192000)秒。又例如是执行每秒60次的更新处理的任务,则即时系统周期112为(1/60)秒。参考图2,即时系统周期112与任务时间111的时间差异即为时间差113,时间差113即是执行该任务的实际时间与时间上限的差异,亦即是执行任务的剩余时间。如前所述,研判计时器110可以包含一计算器或计数器来计算此时间差113。The judgment timer 110 may also include, for example, but not limited to, a calculator (or counter) to calculate a time difference 113 between the task time 111 and a real-time system period 112 . The real-time system period 112 is the upper limit of the time required for the real-time system to execute tasks. For example, the real-time system period 112 is (1/192000) seconds for an audio signal processing task of 192K samples per second. Another example is a task that performs update processing 60 times per second, then the real-time system cycle 112 is (1/60) second. Referring to FIG. 2 , the time difference between the real-time system cycle 112 and the task time 111 is the time difference 113 , and the time difference 113 is the difference between the actual time for executing the task and the time limit, that is, the remaining time for executing the task. As mentioned above, the judgment timer 110 may include a calculator or counter to calculate the time difference 113 .
根据图1中的实施例,控制器120接收时间差113,并且根据时间差113与一参考时间121来产生一控制信号122。图3是本发明的一实施范例的一示意图,说明控制器产生一控制信号。如图3的实施例所示,控制器120可以例如是一比较器,比较时间差113与参考时间121来产生控制信号122。其中参考时间121可以例如是一设定时间(例如是20微秒)或是即时系统周期112的某些比例,例如是即时系统周期112的10%。在一实施范例中,参考时间121代表最佳缓冲时间(例如是即时系统周期的10%),若时间差113大于参考时间121,表示执行任务的剩余时间多于最佳缓冲时间,亦即表示执行任务的系统时钟较快速,以至于有比最佳缓冲时间较高的剩余时间。此时控制器可以产生控制信号122,例如是一高电位信号。另一种情况是若时间差113小于参考时间121,表示执行任务的剩余时间少于最佳缓冲时间,亦即表示执行任务的系统时钟较慢,以至于有比最佳缓冲时间较低的剩余时间。此时控制器可以产生控制信号122,例如是一低电位信号。According to the embodiment in FIG. 1 , the controller 120 receives the time difference 113 and generates a control signal 122 according to the time difference 113 and a reference time 121 . FIG. 3 is a schematic diagram of an embodiment of the present invention, illustrating that a controller generates a control signal. As shown in the embodiment of FIG. 3 , the controller 120 can be, for example, a comparator, which compares the time difference 113 with the reference time 121 to generate the control signal 122 . The reference time 121 can be, for example, a set time (eg, 20 microseconds) or a certain proportion of the real-time system period 112 , such as 10% of the real-time system period 112 . In one embodiment, the reference time 121 represents the optimal buffer time (for example, 10% of the real-time system cycle), if the time difference 113 is greater than the reference time 121, it means that the remaining time for executing the task is longer than the optimal buffer time, that is, the execution The task's system clock is fast enough to have a higher remaining time than the optimal buffer time. At this time, the controller can generate a control signal 122 , such as a high potential signal. Another situation is that if the time difference 113 is less than the reference time 121, it means that the remaining time for executing the task is less than the optimal buffer time, that is, the system clock for executing the task is slower, so that there is a lower remaining time than the optimal buffer time . At this time, the controller can generate a control signal 122 , such as a low potential signal.
承上述,时钟产生器130接收该控制信号122来产生调整的系统时钟131,以提供给该即时计算系统。图4是本发明的一实施范例的一示意图,说明时钟产生器130接收该控制信号122来产生系统时钟131。例如上述的实施范例中,时钟产生器130可以根据控制器120产生高电位的控制信号122来产生比目前时钟更慢的系统时钟131(或是时钟产生器13可以根据低电位的控制信号122来产生比目前时钟更快的系统时钟131),以提供给该即时计算系统。According to the above, the clock generator 130 receives the control signal 122 to generate an adjusted system clock 131 to provide to the real-time computing system. FIG. 4 is a schematic diagram of an implementation example of the present invention, illustrating that the clock generator 130 receives the control signal 122 to generate the system clock 131 . For example, in the above-mentioned implementation example, the clock generator 130 can generate a system clock 131 slower than the current clock according to the control signal 122 of a high potential generated by the controller 120 (or the clock generator 13 can generate a system clock 131 according to the control signal 122 of a low potential Generate a faster system clock 131) than the current clock to provide to the real-time computing system.
根据另一个实施例,图5说明一种动态时钟调整的方法,应用于一即时计算系统,此方法包含:检测即时计算系统执行一任务的一任务时间,如步骤510所示;计算任务时间与一即时系统周期的一时间差,如步骤520所示;使用一控制器,根据此时间差与一参考时间来产生一控制信号,如步骤530所示;以及使用一时钟产生器,接收此控制信号来产生系统时钟,以提供给即时计算系统,如步骤540所示。According to another embodiment, FIG. 5 illustrates a method for dynamic clock adjustment, which is applied to a real-time computing system. The method includes: detecting a task time when the real-time computing system executes a task, as shown in step 510; calculating the task time and A time difference of an instant system cycle, as shown in step 520; use a controller to generate a control signal according to the time difference and a reference time, as shown in step 530; and use a clock generator to receive the control signal to A system clock is generated to provide to the real-time computing system, as shown in step 540 .
在步骤510中,检测此即时计算系统执行一任务的一任务时间,可以使用一计数器,根据一即时计算系统执行一任务的时钟进行计数而获得任务时间。In step 510, a task time for the real-time computing system to execute a task is detected, and a counter can be used to count according to a clock of the real-time computing system for executing a task to obtain the task time.
在步骤520中,计算任务时间与一即时系统周期的一时间差,可使用一计算器(或计数器)来计算任务时间与一即时系统周期的一时间差。即时系统周期是即时系统执行任务所需时间的上限,例如是执行每秒192K取样的音频信号处理的任务,则即时系统周期112为(1/192000)秒。即时系统周期又例如是执行每秒60次的更新处理的任务,则即时系统周期112为(1/60)秒。时间差即是执行任务的实际时间与时间上限的差异,亦即是执行任务的剩余时间。In step 520, a time difference between the task time and a real-time system period is calculated. A calculator (or counter) may be used to calculate the time difference between the task time and a real-time system period. The real-time system period is the upper limit of the time required for the real-time system to execute tasks. For example, the real-time system period 112 is (1/192000) seconds for an audio signal processing task of 192K samples per second. The real-time system cycle is, for example, a task that performs update processing 60 times per second, and the real-time system cycle 112 is (1/60) second. The time difference is the difference between the actual time for executing the task and the time limit, that is, the remaining time for executing the task.
在步骤530中,使用一控制器根据时间差与一参考时间来产生一控制信号,控制器可以例如是一比较器,比较时间差与参考时间来产生控制信号。其中参考时间可以例如是一设定时间(例如是20微秒)或是即时系统周期的某些比例,例如是即时系统周期的10%。在一实施例中,参考时间代表最佳缓冲时间(例如是即时系统周期的10%),若时间差大于参考时间,表示执行任务的剩余时间多于最佳缓冲时间,亦即表示执行任务的系统时钟较快速,以至于有比最佳缓冲时间较高的剩余时间。此时控制器可以产生控制信号,例如是一高电位信号。另一种情况是若时间差小于参考时间,表示执行任务的剩余时间少于最佳缓冲时间,亦即表示执行任务的系统时钟较慢,以至于有比最佳缓冲时间较低的剩余时间。此时控制器可以产生控制信号,例如是一低电位信号。In step 530 , a controller is used to generate a control signal according to the time difference and a reference time. The controller can be, for example, a comparator, which compares the time difference with the reference time to generate the control signal. The reference time can be, for example, a set time (eg, 20 microseconds) or a certain percentage of the real-time system cycle, such as 10% of the real-time system cycle. In one embodiment, the reference time represents the optimal buffer time (for example, 10% of the real-time system cycle), if the time difference is greater than the reference time, it means that the remaining time for executing the task is longer than the optimal buffer time, that is, the system executing the task The clock is faster so that there is a higher remaining time than the optimal buffer time. At this time, the controller can generate a control signal, such as a high potential signal. Another situation is that if the time difference is less than the reference time, it means that the remaining time for executing the task is less than the optimal buffer time, that is, it means that the system clock for executing the task is slow, so that the remaining time is lower than the optimal buffer time. At this time, the controller can generate a control signal, such as a low potential signal.
在步骤540中,使用时钟产生器接收该控制信号来产生系统时钟,以提供给即时计算系统。例如上述的实施范例中,时钟产生器可以根据控制器产生高电位的控制信号来产生比目前时钟更慢的系统时钟(或是时钟产生器可以根据低电位的控制信号来产生比目前时钟更快的系统时钟131),以提供给该即时计算系统。In step 540, a clock generator is used to receive the control signal to generate a system clock to provide to the real-time computing system. For example, in the above-mentioned implementation example, the clock generator can generate a system clock slower than the current clock according to the high potential control signal generated by the controller (or the clock generator can generate a faster system clock than the current clock according to the low potential control signal system clock 131) to provide to the real-time computing system.
综上所述,本揭露提出一种提动态时钟调整的技术,以闭回路控制的方式,经由控制器产生的控制信号来及时地动态调整系统时钟。To sum up, this disclosure proposes a technology for dynamic clock adjustment, which uses a closed-loop control method to dynamically adjust the system clock in a timely manner through the control signal generated by the controller.
以上所揭露的图示及说明,仅为本发明的较佳实施例而已,非为用以限定本发明的实施,本领域的技术人员其所依本发明的精神,所作的变化或修饰,皆应涵盖在随附的本案的权利要求书范围内。The illustrations and descriptions disclosed above are only preferred embodiments of the present invention, and are not intended to limit the implementation of the present invention. Any changes or modifications made by those skilled in the art according to the spirit of the present invention are all shall fall within the scope of the appended claims of this case.
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US20140201561A1 (en) * | 2013-01-15 | 2014-07-17 | International Business Machines Corporation | Clock skew analysis and optimization |
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JPS63181515A (en) * | 1987-01-22 | 1988-07-26 | Fujitsu Ltd | Automatic delay time adjustment method |
TWI317857B (en) * | 2006-11-10 | 2009-12-01 | Inventec Corp | Method for updating the timing of a baseboard management controller |
CN101295981A (en) * | 2007-04-27 | 2008-10-29 | 上海芯致电子科技有限公司 | System clock regulating circuit |
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