CN106303313A - The quantization summing circuit of compressed sensing cmos image sensor - Google Patents
The quantization summing circuit of compressed sensing cmos image sensor Download PDFInfo
- Publication number
- CN106303313A CN106303313A CN201610664911.3A CN201610664911A CN106303313A CN 106303313 A CN106303313 A CN 106303313A CN 201610664911 A CN201610664911 A CN 201610664911A CN 106303313 A CN106303313 A CN 106303313A
- Authority
- CN
- China
- Prior art keywords
- switch
- summing circuit
- voltage
- quantization
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/767—Horizontal readout lines, multiplexers or registers
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The present invention provides the quantization summing circuit of a kind of compressed sensing cmos image sensor, including: pixel sampling circuit, high-order quantization summing circuit and low level fine quantization circuit；Described pixel sampling circuit is sampled for the pixel selected compressed sensing cmos image sensor successively；The described high-order summing circuit that quantifies quantifies for the sampled voltage of sample circuit output is carried out summation, exports a high position for final quantized result, and produces a residual voltage；Described low bit quantification summing circuit quantifies for described residual voltage carries out summation, exports the low level of final quantized result.The present invention uses high-order quantization summing circuit and low bit quantification summing circuit two-layer configuration, and uses the working method of pipeline system so that low bit quantification summing circuit fine quantization process prevents take up extra system time.It addition, the present invention can make low bit quantification summing circuit input voltage be in non-negative state all the time, it is greatly expanded the range of application of the present invention.
Description
Technical field
The invention belongs to compressed sensing cmos image sensor design field, particularly relate to a kind of compressed sensing CMOS figure
Quantization summing circuit as sensor.
Background technology
According to the difference of signal sampling playback mode, cmos image sensor (CIS) can be divided into nyquist sampling CIS
With compressed sensing sampling CIS.Nyquist sampling is that most imageing sensor is used, and belongs to traditional sampling mode.
Compressed sensing sampling is then to exist under some special occasions.
The theoretical foundation of nyquist sampling is nyquist sampling theorem, i.e. when sample frequency is more than twice signal bandwidth
Time, primary signal just can be accurately recovered out.For imageing sensor, signal frequency is that image pixel is along with space bit
The change frequency put, thus can be along with the scene change of real image.So the most conservative way exports all pixels exactly
Information, the sample size i.e. exported is equal with number of pixels.
Compressed sensing sampling is the most different, and needed for it, sample number is relevant with the sparse degree of signal.The most sparse degree
Refer to primary signal is zero value number, the most sparse degree of number is the highest, and required sample number is the fewest.Therefore,
In view of image, this has openness in some specifically conversion base, and compressed sensing is no longer necessary to export each pixel
Pixel Information, but the sample of number of pixels it is much smaller than by the output of compressed sensing transformed samples.
It can be seen that compressed sensing CIS is compared with nyquist sampling CIS can be greatly reduced output data quantity, thus can
To reach speeding up data transmission and to reduce the effect of power consumption.
The method realizing compressed sensing sampling in cmos image sensors is all pixel values to be done once linear become
Changing, sampling process corresponds to once linear conversion process the most each time.In a sampling process, system will be random from whole
Choosing one part of pixel in individual pel array, then the pixel size to them is weighted suing for peace (linear transformation), the most defeated
Go out summed result.Required sampling number will be substantially less that number of pixels.
The most common way of this weighted sum linear transformation is weights size to be taken into randomly " 1 " and " 0 "." 1 " is right
The pixel answered will participate in summation, and the pixel of " 0 " correspondence is then not involved in summation.Therefore, each time compressed sensing sampling be exactly from
Pel array is chosen one part of pixel and its pixel value is carried out summation output.
Common several summing circuits are as shown in Fig. 1 a～Fig. 1 c, and wherein, Fig. 1 a is to utilize resistor network and operation amplifier
All signals are sued for peace by device, then quantify summed result with analog-digital converter (ADC).This method will use
Substantial amounts of resistance, precision and area all can be restricted.Fig. 1 b is to quantify each pixel value, so first with ADC array
By adder, all quantized result are carried out numeral afterwards to sue for peace.This method needs substantial amounts of ADC, and area and power consumption will be subject to
Limit.Paper (R.Robucci, J.D.Gray, L.K.Chiu, J.Romberg, and P.Hasler, " Compressive
sensing on a CMOS separable-transform image sensor,”Proc.IEEE,vol.98,no.6,
Pp.1089 1101, Jun.2010.) describe another kind of summing circuit, as illustrated in figure 1 c, pixel voltage is first converted into electricity by it
Flowing quantization of then suing for peace, the step of do so is more, and cumulative error is relatively big, thus the problem in terms of producing precision.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of compressed sensing cmos image and passes
The quantization summing circuit of sensor, for solving the problems such as the area of summing circuit is relatively big, quantified precision is the highest in prior art.
For achieving the above object and other relevant purposes, the present invention provides the amount of a kind of compressed sensing cmos image sensor
Changing summing circuit, described quantization summing circuit includes: pixel sampling circuit, high-order quantization summing circuit and low level fine quantization electricity
Road；Described pixel sampling circuit is sampled for the pixel selected compressed sensing cmos image sensor successively；Described
The high-order summing circuit that quantifies quantifies for the sampled voltage of sample circuit output is carried out summation, exports final quantized result
A high position, and produce a residual voltage；Described low bit quantification summing circuit quantifies for described residual voltage carries out summation, defeated
Go out the low level of final quantized result.
As a kind of preferred version quantifying summing circuit of the compressed sensing cmos image sensor of the present invention, described picture
Element sample circuit includes the array being made up of multiple sampling units, and described sampling unit includes that a switching tube and a D trigger
Device, the D of switching tube grid and next collecting unit that the Q output of described d type flip flop connects currently employed unit triggers
The D input of device, the first pole of described switching tube connects pixel cell, and the second pole is as the outfan of collecting unit.
Preferably, all d type flip flops of described pixel sampling circuit connect into circulating register structure, first picture
D type flip flop one high level of input of element value, remaining d type flip flop is output as low level so that sampling for the first time will export
First pixel voltage size, the most often one clock cycle of experience, the high level in d type flip flop will transfer to next D
Trigger thus realize next pixel is sampled.
As a kind of preferred version quantifying summing circuit of the compressed sensing cmos image sensor of the present invention, described height
Position quantization summing circuit includes the first summation module, first integrator, the first comparator and the first amplifier, and described first asks
Being connected to described pixel sampling circuit with module, described first integrator is connected to described first summation module, described first ratio
Relatively device is connected to institute first and states integrator, and the outfan of described first comparator is connected to the input of described first amplifier,
The outfan of described first amplifier is connected to described first summation module.
Preferably, described first summation module and first integrator are for tiring out each sampled voltage and feedback voltage
Adding, when the output voltage of first integrator is more than zero, described first comparator exports one instead by described first amplifier
Feedthrough voltage-Vref gives described first summation module so that when first integrator output voltage is more than zero, its input will deduct
One voltage Vref, when first integrator output voltage is less than zero, the first comparator is output as 0, and feedback voltage is also zero, this
Time first integrator only sampled voltage is carried out cumulative and there is no feedback voltage part, wherein, Vref is an electricity more than zero
Pressure.
Preferably, described first integrator is selected as operational amplifier, with ensure a high position quantify summing circuit gain and
Precision.
As a kind of preferred version quantifying summing circuit of the compressed sensing cmos image sensor of the present invention, described low
Position quantization summing circuit and described high-order quantization are also associated with a residual voltage sample circuit between summing circuit, for described
The high-order residual voltage quantifying summing circuit output is sampled.
Preferably, described low bit quantification summing circuit include the second summation module, second integral device, the second comparator and
Second amplifier, described second summation module is connected to described residual voltage sample circuit, and described second integral device is connected to institute
Stating the second summation module, described second comparator is connected to described second integral device, and the outfan of described second comparator connects
In the input of described second amplifier, the outfan of described second amplifier is connected to described second summation module.
Preferably, described second summation module and second integral device are for entering each residue sampled voltage and feedback voltage
Row is cumulative, and when the output voltage of second integral device is more than zero, described second comparator is by described second amplifier output one
Individual feedback voltage-Vref gives described second summation module so that when second integral device output voltage is more than zero, its input will
Deducting a voltage Vref, when second integral device output voltage is less than zero, the second comparator is output as 0, and feedback voltage is also
Zero, now residue sampled voltage is only carried out cumulative and does not has feedback voltage part by second integral device, wherein, Vref be one big
In the voltage of zero.
Preferably, it is phase inverter that described second integral device is selected, to reduce area and the power consumption of low bit quantification summing circuit.
As a kind of preferred version quantifying summing circuit of the compressed sensing cmos image sensor of the present invention, described height
It is also associated with a comparator between position quantization summing circuit and low bit quantification summing circuit, is used for judging residual voltage and high-order amount
Change the size of the DC offset voltage of summing circuit output, using the greater therein as remaining that low bit quantification summing circuit inputs
Remaining voltage, smaller is as the bias voltage of low bit quantification summing circuit so that the high-order summing circuit that quantifies inputs residual voltage
Quantified further at low bit quantification summing circuit with the absolute value of the difference of bias voltage, and input and do not have negative value.
As a kind of preferred version quantifying summing circuit of the compressed sensing cmos image sensor of the present invention, described height
Position quantization summing circuit runs the high-order portion of N number of all after date output quantization results, and then residual voltage samples low level amount
After changing summing circuit, next quantizing process will be carried out so that the quantization of described low bit quantification summing circuit is at described height
Within the time interval next time quantified of position quantization summing circuit, to save quantization time, wherein, N is that pel array comprises
Number of pixels.
As it has been described above, the quantization summing circuit of the compressed sensing cmos image sensor of the present invention, there is following useful effect
Really:
The invention provides a kind of summation sample circuit for compressed sensing cmos image sensor, be used for compression
Perception sampling process；Described summation sample circuit has high-order quantization summing circuit and low bit quantification summing circuit two-layer configuration,
And use the working method of pipeline system so that when low bit quantification summing circuit fine quantization process prevents take up extra system
Between.It addition, may be for the problem of negative value, the solution party that the present invention proposes in order to solve low bit quantification summing circuit input voltage
Method can make low bit quantification summing circuit input voltage be in non-negative state all the time, is greatly expanded the range of application of the present invention.
Accompanying drawing explanation
Fig. 1 a～Fig. 1 c is shown as the several embodiments schematic diagram of summing circuit of the prior art.
Fig. 2 is shown as the structured flowchart of the summation sample circuit for compressed sensing cmos image sensor of the present invention.
Fig. 3 is shown as the pixel sampling electricity of the summation sample circuit for compressed sensing cmos image sensor of the present invention
The structured flowchart on road.
Fig. 4 is shown as high-order quantization for the summation sample circuit of compressed sensing cmos image sensor of the present invention and asks
Structured flowchart with circuit.
Fig. 5 is shown as the low bit quantification for the summation sample circuit of compressed sensing cmos image sensor of the present invention and asks
Structured flowchart with circuit.
Fig. 6 is shown as high-order quantization for the summation sample circuit of compressed sensing cmos image sensor of the present invention and asks
Particular circuit configurations schematic diagram with circuit.
Fig. 7 is shown as the low bit quantification for the summation sample circuit of compressed sensing cmos image sensor of the present invention and asks
Particular circuit configurations schematic diagram with circuit.
Fig. 8 is shown as the integrated circuit knot of the summation sample circuit for compressed sensing cmos image sensor of the present invention
Structure schematic diagram.
Fig. 9 is shown as the work schedule of the summation sample circuit for compressed sensing cmos image sensor of the present invention
Figure.
Figure 10 is shown as the negative value input of the summation sample circuit for compressed sensing cmos image sensor of the present invention
Voltage solution schematic diagram.
Element numbers explanation
10 pixels
20 pixel sampling circuit
30 high-order quantization summing circuits
301 first summation modules
302 first integrators
303 first comparators
304 first amplifiers
40 low bit quantification summing circuits
401 second summation modules
402 second integral devices
403 second comparators
404 second amplifiers
50 residual voltage sample circuits
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by the most different concrete realities
The mode of executing is carried out or applies, the every details in this specification can also based on different viewpoints and application, without departing from
Various modification or change is carried out under the spirit of the present invention.
Refer to Fig. 2～Figure 10.It should be noted that the diagram provided in the present embodiment illustrates this most in a schematic way
The basic conception of invention, package count when then only showing the assembly relevant with the present invention rather than implement according to reality in diagram
Mesh, shape and size are drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its
Assembly layout kenel is likely to increasingly complex.
As in figure 2 it is shown, the present embodiment provides the quantization summing circuit of a kind of compressed sensing cmos image sensor, described amount
Change summing circuit to include: pixel sampling circuit 20, high-order quantization summing circuit 30 and low level fine quantization circuit；Described pixel is adopted
Sample circuit 20 is sampled for the pixel 10 selected compressed sensing cmos image sensor successively；Described high-order quantization is asked
Quantify for the sampled voltage of sample circuit output is carried out summation with circuit 30, export a high position for final quantized result, and
Produce a residual voltage；Described low bit quantification summing circuit 40 quantifies for described residual voltage carries out summation, exports
The low level of whole quantized result.
As it is shown on figure 3, described pixel sampling circuit 20 includes the array being made up of multiple sampling units, described sampling unit
Including a switching tube and a d type flip flop, the Q output of described d type flip flop connects the switching tube grid of currently employed unit
And the D input of the d type flip flop of next one collecting unit, the first pole of described switching tube connects pixel cell, and the second pole is made
Outfan for collecting unit.
In the present embodiment, simulating required and pixel output voltage with voltage source Vn, its sampling process is: described
All d type flip flops of pixel sampling circuit 20 connect into circulating register structure, the d type flip flop input of first pixel value
One high level, remaining d type flip flop is output as low level so that it is big that sampling for the first time will export first pixel voltage
Little, the most often one clock cycle of experience, the high level in d type flip flop will transfer to next d type flip flop thus realize right
Next pixel is sampled.
As shown in Figure 4, described high-order quantify summing circuit 30 include the first summation module 301, first integrator 302, the
One comparator 303 and the first amplifier 304, described first summation module 301 is connected to described pixel sampling circuit 20, described
First integrator 302 is connected to described first summation module 301, and described first comparator 303 is connected to institute first and states integrator,
The outfan of described first comparator 303 is connected to the input of described first amplifier 304, described first amplifier 304
Outfan is connected to described first summation module 301.In the present embodiment, described first integrator 302 is selected as operation amplifier
Device, to ensure that a high position quantifies gain and the precision of summing circuit 30.
Specifically, described first summation module 301 and first integrator 302 are for each sampled voltage and feedback voltage
Adding up, when the output voltage of first integrator 302 is more than zero, described first comparator 303 amplifies by described first
Device 304 exports a feedback voltage-Vref to described first summation module 301 so that first integrator 302 output voltage is more than
When zero, its input will deduct a voltage Vref, when first integrator 302 output voltage is less than zero, and the first comparator
303 are output as 0, and feedback voltage is also zero, and now sampled voltage is only carried out cumulative and do not has feedback voltage by first integrator 302
Part, wherein, Vref is the voltage more than zero.
As shown in Figure 6, the described high-order summing circuit 30 that quantifies specifically includes: the first switch Sp1, second switch Sn1, the 3rd
Switch Φ 1d, the 4th switch Φ 2d, the first electric capacity Cs1, the 5th switch Φ the 1, the 6th switch Φ the 2, second electric capacity Cc, the 7th switch
Φ 1d, the 8th switch Vrst1, the 3rd electric capacity Ci1, operational amplifier A, comparator E, the 9th switch Vrst2, amplifier F and
4th electric capacity C1, wherein, first end of described first switch Sp1 connects the first voltage Vrefp, and the second end connects described second and opens
Closing the second end and first end of the 4th switch Φ 2d of Sn1, first end of described second switch Sn1 connects the second voltage
Vrefn, first end of described 3rd switch Φ 1d connects input voltage Vi, and the second end connects the second of described 4th switch Φ 2d
End and first end of the first electric capacity Cs1, second end of described first electric capacity Cs1 connects the 5th switch Φ the 1, the 6th and switchs Φ 2
And second first end of electric capacity Cc, the second end ground connection of described 5th switch Φ 1, second end of described 6th switch Φ 2 connects
7th switch Φ 1d, the 8th switch Vrst1 and first end of the 3rd electric capacity Ci1, second end of described 7th switch Φ 1d connects
Second end of the second electric capacity Cc and the first input end of operational amplifier A, the second end ground connection of described 8th switch Vrst1,
Second input end grounding of described operational amplifier A, outfan connect second end of described 3rd electric capacity Ci1, the of comparator E
One input and first end of the 9th switch Vrst2, the second input end grounding of described comparator, the first outfan Sp1 connects
In high-positioned counter, the second outfan output signal Sn1, second end of described 9th switch Vrst2 connects described amplifier F's
Input and first end of the 4th electric capacity C1, the second end ground connection of described 4th electric capacity C1, the outfan of described amplifier F is used
In output residual voltage Vo1.
As in figure 2 it is shown, described low bit quantification summing circuit 40 and described high-order quantization are also associated with between summing circuit 30
One residual voltage sample circuit 50, for sampling to the described high-order residual voltage quantifying summing circuit 30 output.
As it is shown in figure 5, described low bit quantification summing circuit 40 include the second summation module 401, second integral device 402,
Two comparator 403 and the second amplifiers 404, described second summation module 401 is connected to described residual voltage sample circuit 50,
Described second integral device 402 is connected to described second summation module 401, and described second comparator 403 is connected to described second and amasss
Dividing device 402, the outfan of described second comparator 403 is connected to the input of described second amplifier 404, and described second amplifies
The outfan of device 404 is connected to described second summation module 401.In the present embodiment, described second integral device 402 is selected is anti-
Phase device, to reduce area and the power consumption of low bit quantification summing circuit 40.
Specifically, described second summation module 401 and second integral device 402 are for each residue sampled voltage and feedback
Voltage adds up, and when the output voltage of second integral device 402 is more than zero, described second comparator 403 is by described second
Amplifier 404 exports a feedback voltage-Vref to described second summation module 401 so that second integral device 402 output voltage
During more than zero, its input will deduct a voltage Vref, and when second integral device 402 output voltage is less than zero, second compares
Device 403 is output as 0, and feedback voltage is also zero, and now residue sampled voltage only is carried out adding up and do not has anti-by second integral device 402
Feedthrough voltage part, wherein, Vref is the voltage more than zero.
As it is shown in fig. 7, described low bit quantification summing circuit 40 specifically includes: first switch Sp2, second switch Sn2, the 3rd
Switch Φ 1d, the 4th switch Φ 2d, the first electric capacity Cs2, the second electric capacity Cs2, the 5th switch Φ 1d, the 6th switch Φ 2d, the 7th
Switch Φ the 1, the 8th switch Φ the 2, the 3rd electric capacity Cc, the 9th switch Φ 1d, the tenth switch Vrst3, the 4th electric capacity Ci2, phase inverter B
And comparator E, wherein, first end of described first switch Sp1 connects the first voltage Vrefp, and the second end connects described second
Second end of switch Sn1 and first end of the 4th switch Φ 2d, first end of described second switch Sn1 connects the second voltage
First end of Vrefn, described 3rd switch Φ 1d connects the residual voltage Vo1 of sampling, and the second end connects described 4th switch Φ
Second end of 2d and first end of the first electric capacity Cs2, second end of described first electric capacity Cs2 connects the 7th switch Φ the 1, the 8th
Switch first end of Φ 2, first end of the 3rd electric capacity Cc and second end of the second electric capacity Cs2, the of described second electric capacity Cs2
One end connects the first end and second end of the 5th switch Φ 1d of the 6th switch Φ 2d, first end of described 5th switch Φ 1d
Meeting bias voltage Vbias, the second end ground connection of described 6th switch Φ 2d, the described 7th switchs the second end ground connection of Φ 1, described
Second end of the 8th switch Φ 2 connects the 9th switch Φ 1d, the tenth switch Vrst3 and first end of the 4th electric capacity Ci2, and described the
Ten switch Vrst3 the second end ground connection, described 9th switch Φ 1d second end connect described 3rd electric capacity the second end and
The input of described phase inverter B, the outfan of described phase inverter connects second end of described 4th electric capacity Ci2 and comparator
First input end, the second input end grounding of described comparator, the first outfan connects low counter, the second outfan output
Signal Sn2.
In particular, it can be seen that the structure that high-order quantization summation low level amount becomes more meticulous is substantially coincident, such as Fig. 4～Fig. 7
Shown in.Each input voltage and feedback voltage can be added up by integration with summation module.When the output voltage of integrator is more than
When zero, comparator is output as 1, thus feeds back a reference voltage-Vref to input.Here Vref is one and is more than zero
Voltage, the when that namely integrator output terminal being more than zero, input will deduct a reference voltage Vref.When integrator is defeated
When going out voltage less than zero, comparator is output as 0, and feedback voltage is also zero.According to this structure, we can be analyzed knot as follows
Really:
V [1]=Vi [1]-D [1] * Vref
V [2]=V [1]+Vi [2]-D [2] * Vref
=Vi [1]+Vi [2]-(D [1]+D [2]) * Vref
By that analogy, can obtain:
It will be seen that when us by adder to 2nThe output of individual comparator can obtain 2 after suing for peacenIndividual input voltage
Meansigma methods, and precision is n-bit.Obviously, meansigma methods and summed result are equivalent, i.e. meansigma methods is just multiplied by input number
It it is the summation of input voltage.In above formula, V [n] is referred to as residual voltage, quantifies further to obtain:
Wherein, D1 is high-positioned counter output, and D2 is low counter output, and Vrm is final residual voltage.According to upper
Formula, high-positioned counter and low counter have been respectively completed rudenss quantization summation and the process of fine quantization so that overall accuracy
Reach (m+n) bit.
For the low bit quantification summing circuit 40 of band inverter structure, if the residual voltage of input is less than zero, then this
Time integrator output also can be less than zero, and then to cause feedback voltage be zero.The most just there is a serious problem.At this
Under the conditions of Zhong, the output of integrator can be integrated causing integrator the most persistently to reduce and final always to input
Lose integrating function.This situation appears in the Vo1 (residual voltage) situation less than Vbias (amp DC output voltage)
Under, because the input of the second integrator quantifying summing circuit is equivalent to Vo1 and deducts Vbias.In order to solve the problems referred to above, this
The bright negative value input voltage solution proposed shown in Figure 10.The high-order summing circuit 30 that quantifies of the present invention is asked with low bit quantification
And it is also associated with a comparator between circuit 40, for judging that residual voltage is inclined with the direct current of high-order quantization summing circuit 30 output
Putting the size of voltage, the residual voltage inputted as low bit quantification summing circuit 40 by the greater therein, smaller is as low
The bias voltage of position quantization summing circuit 40 so that the high-order summing circuit 30 that quantifies inputs the residual voltage difference with bias voltage
Absolute value is quantified further at low bit quantification summing circuit 40, and inputs and do not have negative value.
As shown in Figure 10, specifically, described negative value input voltage solution includes that comparator and voltage select to control
Module, first input end input the residual voltage Vo1_i, the second input input offset voltage Vbias_i, the of described comparator
One outfan and the second outfan are connected to described voltage and select first input end and second input of control module, are used for controlling
Make the first switch kp1 in described voltage selects control module, second switch kn1, the 3rd switch kp2 and the 4th switch kn2's
Conducting and shutoff, described voltage selects the 3rd input input residual voltage Vo1_i of control module, and four-input terminal input is partially
Putting voltage Vbias_i, described voltage selects control module to include the first switch kp1, second switch kn1, the 3rd switch kp2 and the
Four switch kn2, first end of described first switch kp1 and second switch kn1 connects residual voltage Vo1_i, described 3rd switch
First end of kp2 and the 4th switch kn2 connects bias voltage Vbias_i, and second end of described first switch kp1 connects described the
Second end of four switch kn2, second end of described second switch kn1 connects second end of described 3rd switch kp2, wherein, institute
State the first switch kp1 and the 3rd switch kp2 for simultaneously turning on or simultaneously turning off, described second switch kn1 and the 4th switch kn2 be
Simultaneously turn on or simultaneously turn off, by controlling described first switch kp1, second switch kn1, the 3rd switch kp2 and the 4th switch
Kn2 can realize the outgoing position conversion of residual voltage Vo1_i and bias voltage Vbias_i.
The structure of whole quantization summing circuit and sequential are the most as shown in Figure 8 and Figure 9.First high-order quantization summing circuit 30
The sampled signal of input can carry out summation and quantify and produce a residual voltage, then second level low bit quantification circuit can be to surplus
Remaining voltage quantifies again, improves quantified precision.After all quantizations complete, system can carry out resetting to quantify next time
Summation.From the sequential chart shown in Fig. 9, it may be seen that twice quantization have employed the structure of similar streamline, so that
Low bit quantification is also not take up the extra time.Specifically, the described high-order summing circuit 30 that quantifies runs N number of all after date output quantizations
The high-order portion of result, after then residual voltage being sampled low bit quantification summing circuit 40, will carry out the next one and quantify
Journey so that the quantization of described low bit quantification summing circuit 40 be described high-order quantify that summing circuit 30 upper once quantify time
Between within interval, thus be not take up extra system time, be greatly saved quantization time, wherein, N is that pel array comprises
Number of pixels, in the present embodiment, N=2n, wherein, n is whole number.
As it has been described above, the quantization summing circuit of the compressed sensing cmos image sensor of the present invention, there is following useful effect
Really:
The invention provides a kind of summation sample circuit for compressed sensing cmos image sensor, be used for compression
Perception sampling process；Described summation sample circuit has high-order quantization summing circuit 30 and low bit quantification summing circuit 40 two-stage knot
Structure, and use the working method of pipeline system so that low bit quantification summing circuit 40 fine quantization process prevents take up and extra is
The system time.It addition, may be for the problem of negative value in order to solve low bit quantification summing circuit 40 input voltage, the present invention proposes
Solution can make low bit quantification summing circuit 40 input voltage be in non-negative state all the time, is greatly expanded answering of the present invention
Use scope.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any ripe
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage knowing this technology.Cause
This, have usually intellectual such as complete with institute under technological thought without departing from disclosed spirit in art
All equivalences become are modified or change, and must be contained by the claim of the present invention.
Claims (14)
1. the quantization summing circuit of a compressed sensing cmos image sensor, it is characterised in that described quantization summing circuit bag
Include: pixel sampling circuit, high-order quantization summing circuit and low level fine quantization circuit；
Described pixel sampling circuit is sampled for the pixel selected compressed sensing cmos image sensor successively；
The described high-order summing circuit that quantifies quantifies for the sampled voltage of sample circuit output is carried out summation, exports final amount
Change a high position for result, and produce a residual voltage；
Described low bit quantification summing circuit quantifies for described residual voltage carries out summation, exports the low of final quantized result
Position.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 1, it is characterised in that: described
Pixel sampling circuit includes the array being made up of multiple sampling units, and described sampling unit includes that a switching tube and a D touch
Sending out device, the D of switching tube grid and next collecting unit that the Q output of described d type flip flop connects currently employed unit touches
Sending out the D input of device, the first pole of described switching tube connects pixel cell, and the second pole is as the outfan of collecting unit.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 2, it is characterised in that: described
All d type flip flops of pixel sampling circuit connect into circulating register structure, the d type flip flop input one of first pixel value
Individual high level, remaining d type flip flop is output as low level so that sampling for the first time will export first pixel voltage size,
The most often one clock cycle of experience, the high level in d type flip flop will be transferred to next d type flip flop thus realize next
Individual pixel is sampled.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 1, it is characterised in that: described
The high-order summing circuit that quantifies includes the first summation module, first integrator, the first comparator and the first amplifier, described first
Summation module is connected to described pixel sampling circuit, and described first integrator is connected to described first summation module, and described first
Comparator is connected to institute first and states integrator, and the outfan of described first comparator is connected to the input of described first amplifier
End, the outfan of described first amplifier is connected to described first summation module.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 4, it is characterised in that: described
First summation module and first integrator for each sampled voltage and feedback voltage are added up, defeated when first integrator
When going out voltage more than zero, described first comparator exports feedback voltage-Vref to described the by described first amplifier
One summation module so that when first integrator output voltage is more than zero, its input will deduct a voltage Vref, when first
When integrator output voltage is less than zero, the first comparator is output as 0, and feedback voltage is also zero, and now first integrator is only to adopting
Sample voltage carries out cumulative and does not has feedback voltage part, and wherein, Vref is the voltage more than zero.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 4, it is characterised in that: described
It is operational amplifier that first integrator is selected, to ensure that a high position quantifies gain and the precision of summing circuit.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 4, it is characterised in that: described
The high-order summing circuit that quantifies includes: the first switch, second switch, the 3rd switch, the 4th switch, the first electric capacity, the 5th switch, the
Six switches, the second electric capacity, the 7th switch, the 8th switch, the 3rd electric capacity, operational amplifier, comparator, the 9th switch, amplifier
And the 4th electric capacity, wherein, the first end of described first switch connects the first voltage, and the second end connects the of described second switch
Two ends and the first end of the 4th switch, the first end of described second switch connects the second voltage, the first of described 3rd switch
End connects input voltage, and the second end connects the second end and first end of the first electric capacity of described 4th switch, described first electricity
The second end held connects the 5th switch, the 6th switch and the first end of the second electric capacity, the second end ground connection of described 5th switch, institute
The second end stating the 6th switch connects the 7th switch, the 8th switch and the first end of the 3rd electric capacity, the second of described 7th switch
End connects the second end and the first input end of operational amplifier of the second electric capacity, the second end ground connection of described 8th switch, institute
Stating the second input end grounding of operational amplifier, outfan connects the first input of the second end of described 3rd electric capacity, comparator
End and the first end of the 9th switch, the second input end grounding of described comparator, the first outfan is connected to high-positioned counter, institute
The second end stating the 9th switch connects the input of described amplifier and the first end of the 4th electric capacity, the of described 4th electric capacity
Two end ground connection, the outfan of described amplifier is used for exporting residual voltage.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 1, it is characterised in that: described
Low bit quantification summing circuit and described high-order quantization are also associated with a residual voltage sample circuit between summing circuit, for institute
State the high-order residual voltage quantifying summing circuit output to sample.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 8, it is characterised in that: described
Low bit quantification summing circuit includes the second summation module, second integral device, the second comparator and the second amplifier, described second
Summation module is connected to described residual voltage sample circuit, and described second integral device is connected to described second summation module, described
Second comparator is connected to described second integral device, and the outfan of described second comparator is connected to the defeated of described second amplifier
Entering end, the outfan of described second amplifier is connected to described second summation module.
The quantization summing circuit of compressed sensing cmos image sensor the most according to claim 9, it is characterised in that: institute
State the second summation module and second integral device for each residue sampled voltage and feedback voltage are added up, work as second integral
When the output voltage of device is more than zero, described second comparator is given by described second amplifier one feedback voltage-Vref of output
Described second summation module so that when second integral device output voltage is more than zero, its input will deduct a voltage Vref,
When second integral device output voltage is less than zero, the second comparator is output as 0, and feedback voltage is also zero, now second integral device
Only carrying out cumulative to residue sampled voltage and do not have feedback voltage part, wherein, Vref is the voltage more than zero.
The quantization summing circuit of 11. compressed sensing cmos image sensors according to claim 9, it is characterised in that: institute
Stating second integral device and selecting is phase inverter, to reduce area and the power consumption of low bit quantification summing circuit.
The quantization summing circuit of 12. compressed sensing cmos image sensors according to claim 9, it is characterised in that: institute
State low bit quantification summing circuit to specifically include: the first switch, second switch, the 3rd switch, the 4th switch, the first electric capacity, second
Electric capacity, the 5th switch, the 6th switch, the 7th switch, the 8th switch, the 3rd electric capacity, the 9th switch, the tenth switch, the 4th electric capacity,
Phase inverter and comparator, wherein, the first end of described first switch connects the first voltage, and the second end connects described second switch
The second end and the first end of the 4th switch, the first end of described second switch connects the second voltage, described 3rd switch
First end connects the residual voltage of sampling, and the second end connects the second end and first end of the first electric capacity of described 4th switch,
Second end of described first electric capacity connects the 7th switch, the first end of the 8th switch, the first end of the 3rd electric capacity and the second electricity
The second end held, the first end of described second electric capacity connects the first end and second end of the 5th switch of the 6th switch, described
First termination bias voltage of the 5th switch, the second end ground connection of described 6th switch, the second end ground connection of described 7th switch,
Second end of described 8th switch connects the 9th switch, the tenth switch and the first end of the 4th electric capacity, the of described tenth switch
Two end ground connection, the second end of described 9th switch connects the second end and the input of described phase inverter of described 3rd electric capacity,
The outfan of described phase inverter connects the second end and the first input end of comparator of described 4th electric capacity, described comparator
Second input end grounding, the first outfan connects low counter.
The quantization summing circuit of 13. compressed sensing cmos image sensors according to claim 1, it is characterised in that: institute
State high-order quantization and be also associated with a comparator between summing circuit and low bit quantification summing circuit, be used for judging that residual voltage is with high
The size of the DC offset voltage of position quantization summing circuit output, inputs the greater therein as low bit quantification summing circuit
Residual voltage, smaller is as the bias voltage of low bit quantification summing circuit so that high-order quantify summing circuit input residue
Voltage is quantified at low bit quantification summing circuit further with the absolute value of the difference of bias voltage, and input does not haves negative
Value.
The quantization summing circuit of 14. compressed sensing cmos image sensors according to claim 1, it is characterised in that: institute
State the high-order summing circuit that quantifies and run the high-order portion of N number of all after date output quantization results, then residual voltage is sampled low
After the quantization summing circuit of position, next quantizing process will be carried out so that the quantization of described low bit quantification summing circuit is in institute
Within stating the high-order time interval next time quantified quantifying summing circuit, to save quantization time, wherein, N is pel array
The number of pixels comprised.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610664911.3A CN106303313B (en) | 2016-08-12 | 2016-08-12 | The quantization summing circuit of compressed sensing cmos image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610664911.3A CN106303313B (en) | 2016-08-12 | 2016-08-12 | The quantization summing circuit of compressed sensing cmos image sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106303313A true CN106303313A (en) | 2017-01-04 |
| CN106303313B CN106303313B (en) | 2019-04-30 |
Family
ID=57670811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610664911.3A Active CN106303313B (en) | 2016-08-12 | 2016-08-12 | The quantization summing circuit of compressed sensing cmos image sensor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106303313B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020082736A1 (en) * | 2018-10-24 | 2020-04-30 | 宁波飞芯电子科技有限公司 | Counting method and device, and counting system and pixel array applying same |
| CN112054483A (en) * | 2020-08-04 | 2020-12-08 | 上海空间电源研究所 | Simple high-reliability overvoltage protection circuit |
| CN112269099A (en) * | 2020-10-12 | 2021-01-26 | 广东电网有限责任公司广州供电局 | Voltage sag state estimation method and system based on compressed sensing theory |
| CN114019449A (en) * | 2022-01-10 | 2022-02-08 | 南京理工大学 | Signal source direction-of-arrival estimation method, signal source direction-of-arrival estimation device, electronic device, and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6670904B1 (en) * | 2002-08-22 | 2003-12-30 | Micron Technology, Inc. | Double-ramp ADC for CMOS sensors |
| CN101227551A (en) * | 2007-01-17 | 2008-07-23 | 索尼株式会社 | Solid-state imaging device and imaging apparatus |
| CN101656539A (en) * | 2008-08-18 | 2010-02-24 | 意法半导体有限公司 | analogue-to-digital converter |
| CN101873136A (en) * | 2009-04-24 | 2010-10-27 | 索尼公司 | Integrated AD converter, solid photographic device and camera arrangement |
| CN102347769A (en) * | 2011-05-26 | 2012-02-08 | 天津大学 | Control circuit of analog-to-digital converter and control method thereof |
| US20140035771A1 (en) * | 2012-08-03 | 2014-02-06 | Realtek Semiconductor Corp. | Predictive successive approximation register analog-to-digital conversion device and method |
| US20140160332A1 (en) * | 2011-04-11 | 2014-06-12 | Sony Corporation | Solid-state image sensor and camera system |
| CN103986470A (en) * | 2014-05-20 | 2014-08-13 | 天津大学 | Low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and converter |
-
2016
- 2016-08-12 CN CN201610664911.3A patent/CN106303313B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6670904B1 (en) * | 2002-08-22 | 2003-12-30 | Micron Technology, Inc. | Double-ramp ADC for CMOS sensors |
| CN101227551A (en) * | 2007-01-17 | 2008-07-23 | 索尼株式会社 | Solid-state imaging device and imaging apparatus |
| CN101656539A (en) * | 2008-08-18 | 2010-02-24 | 意法半导体有限公司 | analogue-to-digital converter |
| CN101873136A (en) * | 2009-04-24 | 2010-10-27 | 索尼公司 | Integrated AD converter, solid photographic device and camera arrangement |
| US20140160332A1 (en) * | 2011-04-11 | 2014-06-12 | Sony Corporation | Solid-state image sensor and camera system |
| CN102347769A (en) * | 2011-05-26 | 2012-02-08 | 天津大学 | Control circuit of analog-to-digital converter and control method thereof |
| US20140035771A1 (en) * | 2012-08-03 | 2014-02-06 | Realtek Semiconductor Corp. | Predictive successive approximation register analog-to-digital conversion device and method |
| CN103986470A (en) * | 2014-05-20 | 2014-08-13 | 天津大学 | Low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and converter |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020082736A1 (en) * | 2018-10-24 | 2020-04-30 | 宁波飞芯电子科技有限公司 | Counting method and device, and counting system and pixel array applying same |
| CN112955955A (en) * | 2018-10-24 | 2021-06-11 | 宁波飞芯电子科技有限公司 | Counting method, counting device, counting system using counting device and pixel array |
| US11950004B2 (en) | 2018-10-24 | 2024-04-02 | Ningbo Abax Sensing Co., Ltd. | Counting method, a counting device and a counting system and a pixel array using the counting device |
| CN112054483A (en) * | 2020-08-04 | 2020-12-08 | 上海空间电源研究所 | Simple high-reliability overvoltage protection circuit |
| CN112269099A (en) * | 2020-10-12 | 2021-01-26 | 广东电网有限责任公司广州供电局 | Voltage sag state estimation method and system based on compressed sensing theory |
| CN114019449A (en) * | 2022-01-10 | 2022-02-08 | 南京理工大学 | Signal source direction-of-arrival estimation method, signal source direction-of-arrival estimation device, electronic device, and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106303313B (en) | 2019-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106303313A (en) | The quantization summing circuit of compressed sensing cmos image sensor | |
| CN103201956B (en) | There is the sigma-delta ADC of test circuit | |
| CN103378861A (en) | Analog-to-digital converter system and method | |
| CN102347769B (en) | Control circuit of analog-to-digital converter and control method thereof | |
| CN110288510B (en) | Proximity sensor vision perception processing chip and Internet of things sensing device | |
| CN108158577B (en) | Low-power-consumption electrocardiosignal processing circuit and method based on compressed sensing | |
| US7107306B2 (en) | Method and apparatus for adaptive real-time signal conditioning, processing, analysis, quantification, comparision, and control | |
| CN104333347B (en) | A kind of switching current gauss low frequency filter | |
| CN103529379B (en) | For the choosing method in low-resolution signal source in high-precision adc test | |
| CN105072359A (en) | CMOS (Complementary Metal Oxide Semiconductor) image sensor imaging system and method based on compressed sensing | |
| CN107396009A (en) | Pulse frequency modulated type image sensor circuit and its processing method | |
| CN103207571A (en) | Encoder signal simulation system and method applied to simulator of loading and unloading machine | |
| CN202856717U (en) | Variable type Sigma-Delta modulator | |
| CN110690901A (en) | High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit | |
| CN105245798A (en) | CCD video compression measurement imaging system based on block-oriented compression sensing, and control method | |
| CN103716055B (en) | A kind of Pre-modulation integral multichannel parallel analog information conversion circuit | |
| CN104883192B (en) | The reconstructing method of non-cooperation ultra-broadband signal based on mixing compression sampling | |
| Cauwenberghs | Delta-sigma cellular automata for analog VLSI random vector generation | |
| CN116011682A (en) | Meteorological data prediction method and device, storage medium and electronic device | |
| CN115425976A (en) | ADC sampling data calibration method and system based on FPGA | |
| CN104038231A (en) | Nonlinear signal conversion circuit of CMOS image sensor | |
| CN102710237B (en) | First-order digital low-pass filtering method, filter and electronic equipment | |
| CN207148206U (en) | The current sampling system and battery simulator of a kind of battery simulator | |
| CN109889200A (en) | A kind of voltage signal based on frequency quantization device turns the circuit of frequency signal | |
| CN111490787A (en) | ∑ -delta modulator and method for reducing nonlinearity and gain error |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |