CN106301369A - A kind of position round-robin method simultaneously improving analog-digital converter SFDR and SNR - Google Patents
A kind of position round-robin method simultaneously improving analog-digital converter SFDR and SNR Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
Abstract
A kind of position round-robin method simultaneously improving analog-digital converter SFDR and SNR of this disclosure of the invention, the technical field of application is the high-precision adc in Microelectronics and Solid State Electronics field.The position round-robin method that the present invention proposes is applicable to the gradually-appoximant analog-digital converter of any structure, its core concept is to split highest order (MSB) electric capacity and time high-order (MSB 1) electric capacity, capacitor array is divided into four groups, same input voltage is changed twice, twice transformation result is averaging and obtains corresponding digital output code, in transformation process, the circulation of each position all changes electric capacity order, reaches the effect to capacitance error consecutive mean.Therefore, compared with the bearing calibration that tradition dependence correction DAC and correcting algorithm improve the linearity, there is the effect that structure is simpler, chip occupying area is less, be easier on sheet realization.
Description
Technical field
The present invention relates to a kind of novel gradually-appoximant analog-digital converter (SAR ADC:Successive
Approximation Register Analog-to-Digital Converter) position round-robin method, direct applied technology
Field is the high-precision adc in Microelectronics and Solid State Electronics field.
Background technology
In SOC(system on a chip), analog-digital converter (ADC:Analog-to-Digital Converter) is to connect simulation system
System and the bridge of digital information processing system (DSP:Digital Signal Processor), the most of signal in nature
The most all analog quantity, our mankind can directly perception be the most all analogue signal, such as light, sound, pressure and temperature
Degree etc., therefore data converter effect in SoC is most important, as it is shown in figure 1, it converts analog signals into digital signal
Delivering to DSP process, result is converted to analogue signal through digital to analog converter again, and the performance of analog-digital converter is to system
Stability, reliability and persistency all have significant effect.
Different application scenarios is the most different to the requirement of analog-digital converter characteristic, and the design of high-performance analog-digital converter is always
It it is one of the difficult point of design of integrated circuit.Although at a high speed, high accuracy and low-power consumption are the important development of analog-digital converter
Direction, but be not the performance indications weighing analog-digital converter, along with improving constantly of system on chip degree, weigh analog digital conversion
The performance indications of device also tend to diversification, and wherein dynamic indicator mainly includes signal to noise ratio (SNR:Signal-to-Noise
Ratio), signal noise distortion ratio (SNDR:Signal-to-Noise-and-Distortion Ratio), total harmonic distortion
(THD:Total Harmonic Distortion), SFDR (SFDR:Spurious-Free Dynamic
And effective accuracy (ENOB:Effective Number of Bits) etc. Range).The dynamic property of analog-digital converter and electricity
Hold coupling closely related.
In order to adapt to the application requirement of different SOC(system on a chip), analog-digital converter also occurs in that many during its development
Planting structure type, current analog-digital converter mainly includes all-parallel A/D converter, production line analog-digital converter and over-sampling
Analog-digital converter, compares the analog-digital converter of the several types such as streamline, over-sampling and full parellel, Approach by inchmeal analog digital conversion
Utensil has that simple in construction, area are little, easy of integration, easily realize the advantages such as able to programme, has been widely used for touch screen, industry control
The systems such as system, biologic medical and radio sensing network.
Tradition three level binary capacitor type gradually-appoximant analog-digital converters as in figure 2 it is shown, its operation principle include sampling,
Keep and three processes of Charge scaling, the matching of electric capacity be determine gradually-appoximant analog-digital converter dynamic property key because of
Element, especially in high-precision applications, the matching problem of gradually-appoximant analog-digital converter electric capacity is always challenging difficulty
Topic, this is owing to being limited by state-of-the-art, and electric capacity can only meet the matching precision of 10, it is not easy to realize high accuracy, false
If it is C that specific capacitance C obeys average0, standard deviation is σcNormal distribution, i.e. C～N (C0,σc), then the m being connected in parallel
Obedience average is mC by individual electric capacity0, standard deviation isNormal distribution, can be expressed as:
Document [Y.-H.Chung, M.-H.Wu, and H.-S.Li, " A 12-bit 8.47-fJ/Conversion-Step
Capacitor-Swapping SAR ADC in 110-nm CMOS”,IEEE Trans.on Circuits and
Systems-I, vol.62, no.1, pp.10--18, Jan.2015.] use high-low position capacitor array exchange position circulation side
Method, can be effectively improved SFDR, but can not improve SNR, document [John G.Kauffman, Pascal Witte, Matthias
Lehmann,Joachim Becker,Yiannos Manoli and Maurits Ortmanns,“A 72dB DR,CTΔΣ
Modulator Using Digitally Estimated,Auxiliary DAC Linearization Achieving
88fJ/conv-step in a 25MHz BW”,IEEE J.Solid-State Circuits,vol.49,no.2,
Pp.392--404, Feb.2014.] use foreground analog correction technology that capacitance mismatch is corrected, need to interrupt analog digital conversion
The normal work of device, although SFDR can be significantly improved, but SNR can not be improved, document [W.Liu, P.Huang, and Y.Chiu,
“A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration”,Proc.of
IEEE CICC, pp.1--4, Sept.2012.] use " least mean-square error " (LMS:Least Mean Square) algorithm school
Positive capacitance mismatch, and correcting scheme based on LMS algorithm is under conditions of given error modeling, precision is high and calibrates effect
Good, if but initial value is chosen improper, and algorithm complex can be caused to increase, even result in the problems such as algorithm not convergence, be not easy to sheet
Upper realization, can not improve SNR equally.
Summary of the invention
Existing capacitance mismatch alignment technique can only improve SFDR, it is impossible to improves SNR, the present invention is directed to the deficiencies in the prior art
Part Curve guide impeller one can improve SFDR and SNR simultaneously, it is not necessary to introduces correction DAC, does not interrupt the normal work of analog-digital converter
Making, structure is simpler, chip occupying area is less, the gradually-appoximant analog-digital converter that can improve that is easier on sheet realize moves
The position round-robin method of state property energy.The position round-robin method that the present invention proposes is applicable to the gradually-appoximant analog-digital converter of any structure,
Its core concept is to split highest order (MSB) electric capacity and time high-order (MSB-1) electric capacity, capacitor array is divided into four groups, to same
One input voltage is changed twice, and twice transformation result is averaging and obtains corresponding digital output code, in transformation process, every time
Position circulation all changes electric capacity order, reaches the effect to capacitance error consecutive mean.The position round-robin method base that the present invention is proposed
12 three level binary capacitor type gradually-appoximant analog-digital converters in Fig. 2 are illustrated, as in figure 2 it is shown, 12 three level
Binary capacitor type gradually-appoximant analog-digital converter is made up of electric capacity DAC, comparator and digital control circuit, compares sectional capacitance
Type structure, binary capacitor type structure is not owing to having floating node, so the linearity is more preferable than segmentation capacitive structure.
The technical scheme is that a kind of position round-robin method simultaneously improving analog-digital converter SFDR and SNR, the method
Including:
Step 1: all specific capacitances in binary capacitor type gradually-appoximant analog-digital converter are equally divided into 4 groups, first
During secondary conversion, first and second group of electric capacity is as highest order, and the 3rd group of electric capacity is as a secondary high position, to first input voltage vin (1)
Carry out position circulation after sampling, produce the output codons Dout (1) _ 1 corresponding to first input voltage vin (1)；
Step 2: during second time conversion, not resampling, still first input voltage vin (1) is changed, the
Two, three groups of electric capacity are as highest order, and the 4th group of electric capacity still produces corresponding to first input as a secondary high position, second time conversion
The output codons Dout (1) _ 2 of voltage Vin (1)；Dout (1) _ 1 and Dout (1) _ 2 two code word are averaging, obtain corresponding to
Code word Dout (1) of first input voltage vin (1)；
Step 3: during third time conversion, third and fourth group electric capacity is as highest order, and first group of electric capacity is as a secondary high position, to the
Carry out position circulation after two input voltage vin (2) samplings, produce the output codons corresponding to second input voltage vin (2)
Dout(2)_1；
Step 4: during the 4th conversion, not resampling, still second input voltage vin (2) is changed, the
One, four groups of electric capacity are as highest order, and second group of electric capacity is as a secondary high position, and the 4th conversion still produces corresponding to second input
The output codons Dout (2) _ 2 of voltage Vin (2)；Dout (2) _ 1 and Dout (2) _ 2 two code word are averaging, obtain corresponding to
Code word Dout (2) of second input voltage vin (2)；
Step 5: during the 5th conversion, third and fourth group electric capacity is as highest order, and first group of electric capacity is as a secondary high position, to the
Carry out position circulation after three input voltage vin (3) samplings, produce the output codons corresponding to the 3rd input voltage vin (3)
Dout(3)_1；
Step 6: during the 6th conversion, not resampling, still the 3rd input voltage vin (3) is changed, the
Two, three groups of electric capacity are as highest order, and the 4th group of electric capacity is as a secondary high position, and the 6th conversion still produces corresponding to the 3rd input
The output codons Dout (3) _ 2 of voltage Vin (3)；Dout (3) _ 1 and Dout (3) _ 2 two code word are averaging, obtain corresponding to
Code word Dout (3) of the 3rd input voltage vin (3)；
During the follow-up output codons of ADC, the mode of the 7th conversion is identical with first time, the mode of the 8th conversion
Identical with second time, circulate successively.
The present invention proposes a kind of position round-robin method that can simultaneously improve gradually-appoximant analog-digital converter SFDR and SNR, and it is special
Point is: need not introduce any correcting algorithm, it is not necessary to introduces correction DAC, and does not interrupt analog-digital converter and normally work.
The position round-robin method that the present invention proposes can improve SFDR and SNR simultaneously, therefore, relies on correction DAC and correcting algorithm with tradition
The bearing calibration improving the linearity is compared, and has that structure is simpler, chip occupying area is less, is easier on sheet to realize
Effect.
Accompanying drawing explanation
Fig. 1 is the effect of data converter.
Fig. 2 is 12 three level binary capacitor type gradually-appoximant analog-digital converters.
Fig. 3 is the position round-robin method for gradually-appoximant analog-digital converter capacitor array that the present invention proposes.
Fig. 4 is 12 gradually-appoximant analog-digital converter FFT simulation results that the present invention proposes.
Fig. 5 is 12 gradually-appoximant analog-digital converter FFT simulation results of tradition.
Detailed description of the invention
The present invention proposes a kind of position round-robin method that can simultaneously improve gradually-appoximant analog-digital converter SFDR and SNR, such as Fig. 3
Shown in, highest order in Fig. 2 (MSB) electric capacity 1024C is split into 256C, 128C ... C, C and 256C, 128C ... two groups of electric capacity of C, C,
A secondary high position (MSB-1) electric capacity 512C splits into 256C, 128C ... C, C, will be divided into four groups by 2048 specific capacitances in Fig. 2, this
Four groups of electric capacity represent by different colors in figure 3, and first group of electric capacity C31～C40 black represent, second group of electric capacity C21～
C30 purple represents, the 3rd group of electric capacity C11～C20 redness represent, the 4th group of electric capacity C1～C10 blueness represent, often group is all
Comprising 512 specific capacitances, i.e. 256C, 128C ... C, C, change same input voltage twice, twice transformation result asks flat
All obtaining corresponding digital output code, in transformation process, the circulation of each position uses different capacitor combinations, it is achieved capacitance error
Consecutive mean, thus reach to improve the purpose of SNR and SFDR simultaneously.
Conversion for the first time: carry out position circulation, highest order (MSB) electric capacity to after first input voltage vin (1) sampling
1024C is collectively constituted by first and second group of electric capacity (C21～C40), and a secondary high position (MSB-1) electric capacity 512C is by the 3rd group of electric capacity (C11
～C20) composition, C2～C10, as bit capacitor, produces the output codons Dout corresponding to first input voltage vin (1)
(1)_1；
Second time conversion: not resampling, still changes first input voltage vin (1), highest order (MSB)
Electric capacity 1024C is organized electric capacity (C11～C30) by second and third and collectively constitutes, and a secondary high position (MSB-1) electric capacity 512C is by the 4th group of electric capacity
(C1～C10) forms, C32～C40 still produces corresponding to first input voltage vin as bit capacitor, second time conversion
(1) output codons Dout (1) _ 2；Dout (1) _ 1 and Dout (1) _ 2 two code word are averaging, obtain corresponding to first
Code word Dout (1) of input voltage vin (1)；
Third time conversion: carry out position circulation, highest order (MSB) electric capacity to after second input voltage vin (2) sampling
1024C is organized electric capacity (C1～C20) by third and fourth and collectively constitutes, a secondary high position (MSB-1) electric capacity 512C by first group of electric capacity (C31～
C40) composition, C22～C30, as bit capacitor, produces the output codons Dout corresponding to second input voltage vin (2)
(2)_1；
4th conversion: not resampling, still changes second input voltage vin (2), highest order (MSB)
Electric capacity 1024C is collectively constituted by first, fourth group of electric capacity (C1～C10, C31～C40), and a secondary high position (MSB-1) electric capacity 512C is by
Two groups of electric capacity (C21～C30) compositions, C12～C20 is as bit capacitor, and the 4th conversion still produces corresponding to second defeated
Enter the output codons Dout (2) _ 2 of voltage Vin (2)；Dout (2) _ 1 and Dout (2) _ 2 two code word are averaging, obtain correspondence
Code word Dout (2) in second input voltage vin (2)；
5th conversion: carry out position circulation, highest order (MSB) electric capacity to after the 3rd input voltage vin (3) sampling
1024C is organized electric capacity (C1～C20) by third and fourth and collectively constitutes, a secondary high position (MSB-1) electric capacity 512C by first group of electric capacity (C31～
C40) composition, C22～C30, as bit capacitor, produces the output codons Dout corresponding to the 3rd input voltage vin (3)
(3)_1；；
6th conversion: not resampling, still changes the 3rd input voltage vin (3), highest order (MSB)
Electric capacity 1024C is organized electric capacity (C11～C30) by second and third and collectively constitutes, and a secondary high position (MSB-1) electric capacity 512C is by the 4th group of electric capacity
(C1～C10) forms, C32～C40 is as bit capacitor, and the 6th conversion still produces corresponding to the 3rd input voltage vin
(3) output codons Dout (3) _ 2；Dout (3) _ 1 and Dout (3) _ 2 two code word are averaging, obtain corresponding to the 3rd
Code word Dout (3) of input voltage vin (3)；
During the follow-up output codons of ADC, during ADC output codons, the mode of the 7th conversion is with for the first time
Identical, the mode of the 8th conversion is identical with second time, circulates successively.
As shown in Figure 4, specific capacitance value is 12 gradually-appoximant analog-digital converter FFT simulation results that the present invention proposes
10f, specific capacitance mismatch errorIt is 0.04, and 12 gradually-appoximant analog-digital converter FFT simulation result such as Fig. 5 of tradition
Shown in.
Table 1 summarizes 12 Approach by inchmeal analog digital conversion that 12 gradually-appoximant analog-digital converters of tradition propose with the present invention
The performance comparison of the SFDR emulation of device.Table 1 shows: compare traditional resistor capacitor type gradually-appoximant analog-digital converter, and the present invention will
SFDR improves 23dB, SNR and improves 5.2dB.
The present invention is directed to conventional successive approach analog-digital converter and propose a kind of new position circulating technology, it is only necessary to will be the highest
Two electric capacity split, and circulation all uses different capacitor combinations in each position, it is possible to realize the optimization of dynamic property, compare
The method that conventionally employed correction DAC technique or correcting algorithm improve dynamic property, it is simple that the present invention controls logic, and hardware is opened
Sell little, power consumption and chip area can be saved.
Table 1: SFDR, SNR contrast of 12 SAR ADC that 12 SAR ADC of tradition propose with the present invention
| SFDR(dB) | SNR(dB) | |
| 12 SAR ADC of tradition | 62.8 | 65.3 |
| 12 SAR ADC that the present invention proposes | 85.8 | 70.5 |
Claims (1)
1. improving a position round-robin method of analog-digital converter SFDR and SNR, the method includes simultaneously:
Step 1: all specific capacitances in binary capacitor type gradually-appoximant analog-digital converter are equally divided into 4 groups, turns for the first time
When changing, first and second group of electric capacity is as highest order, and the 3rd group of electric capacity is as a secondary high position, to first input voltage vin (1) sampling
Carry out position circulation afterwards, produce the output codons Dout (1) _ 1 corresponding to first input voltage vin (1)；
Step 2: during second time conversion, not resampling, still first input voltage vin (1) is changed, second and third
Group electric capacity is as highest order, and the 4th group of electric capacity still produces corresponding to first input voltage as a secondary high position, second time conversion
The output codons Dout (1) _ 2 of Vin (1)；Dout (1) _ 1 and Dout (1) _ 2 two code word are averaging, obtain corresponding to first
Code word Dout (1) of individual input voltage vin (1)；
Step 3: during third time conversion, third and fourth group electric capacity is as highest order, and first group of electric capacity is as a secondary high position, to second
Carry out position circulation after input voltage vin (2) sampling, produce the output codons Dout corresponding to second input voltage vin (2)
(2)_1；
Step 4: during the 4th conversion, not resampling, still second input voltage vin (2) is changed, first, fourth
Group electric capacity is as highest order, and second group of electric capacity is as a secondary high position, and the 4th conversion still produces corresponding to second input voltage
The output codons Dout (2) _ 2 of Vin (2)；Dout (2) _ 1 and Dout (2) _ 2 two code word are averaging, obtain corresponding to second
Code word Dout (2) of individual input voltage vin (2)；
Step 5: during the 5th conversion, third and fourth group electric capacity is as highest order, and first group of electric capacity is as a secondary high position, to the 3rd
Carry out position circulation after input voltage vin (3) sampling, produce the output codons Dout corresponding to the 3rd input voltage vin (3)
(3)_1；
Step 6: during the 6th conversion, not resampling, still the 3rd input voltage vin (3) is changed, second and third
Group electric capacity is as highest order, and the 4th group of electric capacity is as a secondary high position, and the 6th conversion still produces corresponding to the 3rd input voltage
The output codons Dout (3) _ 2 of Vin (3)；Dout (3) _ 1 and Dout (3) _ 2 two code word are averaging, obtain corresponding to the 3rd
Code word Dout (3) of individual input voltage vin (3)；
During the follow-up output codons of ADC, the mode of the 7th conversion is identical with first time, the mode and that the 8th time is changed
Secondary phase is same, circulates successively.
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