CN106298880B - Sull and preparation method, transistor and preparation method, display backboard - Google Patents
Sull and preparation method, transistor and preparation method, display backboard Download PDFInfo
- Publication number
- CN106298880B CN106298880B CN201610894719.3A CN201610894719A CN106298880B CN 106298880 B CN106298880 B CN 106298880B CN 201610894719 A CN201610894719 A CN 201610894719A CN 106298880 B CN106298880 B CN 106298880B
- Authority
- CN
- China
- Prior art keywords
- sull
- layer
- channel layer
- transistor
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 229910052738 indium Inorganic materials 0.000 claims abstract description 17
- 239000004615 ingredient Substances 0.000 claims abstract description 14
- 229910052718 tin Inorganic materials 0.000 claims abstract description 14
- 229910052725 zinc Inorganic materials 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 56
- 239000000758 substrate Substances 0.000 claims description 45
- 238000002161 passivation Methods 0.000 claims description 37
- 238000000151 deposition Methods 0.000 claims description 25
- 239000010409 thin film Substances 0.000 claims description 24
- 238000009413 insulation Methods 0.000 claims description 23
- 238000000137 annealing Methods 0.000 claims description 20
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 17
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 16
- 239000010408 film Substances 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 239000011701 zinc Substances 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 12
- 239000001257 hydrogen Substances 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 11
- 229910000077 silane Inorganic materials 0.000 claims description 10
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 229910021529 ammonia Inorganic materials 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000011787 zinc oxide Substances 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005984 hydrogenation reaction Methods 0.000 claims description 5
- 229910003437 indium oxide Inorganic materials 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- 150000004678 hydrides Chemical class 0.000 claims description 2
- ZEWMZYKTKNUFEF-UHFFFAOYSA-N indium;oxozinc Chemical compound [In].[Zn]=O ZEWMZYKTKNUFEF-UHFFFAOYSA-N 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 230000000694 effects Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 112
- 238000010586 diagram Methods 0.000 description 22
- 239000000463 material Substances 0.000 description 18
- 239000000126 substance Substances 0.000 description 9
- 239000008186 active pharmaceutical agent Substances 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000012528 membrane Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000007773 growth pattern Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 1
- 241000720974 Protium Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000012010 growth Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
- H01L29/247—Amorphous materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of sull and preparation method, transistor and preparation method, display backboard, the ingredient of the sull be include one of Zn, In and Sn or a variety of, and the oxide of H can effectively improve the carrier mobility of sull by hydrogenating to sull；In turn, using the sull as the channel layer of transistor, the carrier mobility of transistor can be further increased, to effectively meet the needs of novel display technology is to high mobility.
Description
Technical field
The present invention relates to technical field of electronic devices, and in particular to a kind of sull and preparation method, transistor and
Preparation method, display backboard.
Background technique
Thin film transistor (TFT) is widely used in liquid crystal display device as pixel switch element.Wherein, in thin film transistor (TFT)
The carrier mobility of channel layer is the key that determine liquid crystal display device performance；The carrier mobility of thin film transistor (TFT) is got over
Height, the driving capability and switching speed of thin film transistor (TFT) are higher, so as to support liquid crystal display device high-resolution, high frame per second
Etc. technical needs.
In order to meet requirement of the liquid crystal display device to the high carrier mobility of thin film transistor (TFT), usually using amorphous
The channel layer as thin film transistor (TFT) such as silicon, polysilicon or oxide semiconductor material.Specifically, magnetic is usually utilized at present
The method of control sputtering forms amorphous indium gallium zinc oxygen film on substrate, and using amorphous indium gallium zinc oxygen film as thin film transistor (TFT)
The mobility of channel layer, the thin film transistor (TFT) can reach in 10-15cm2/Vs。
However, inventors discovered through research that, since liquid crystal display device is just towards high-resolution, high frame per second and large scale
Direction is developed, such as in 65 cun, the 8K liquid crystal display of 240Hz, shows the carrier mobility of the thin film transistor (TFT) in backboard
Rate needs to reach 30cm2/ Vs is even higher, and above-mentioned thin film transistor (TFT) is difficult to meet the needs of novel liquid crystal display device.Therefore,
How to obtain the higher oxide semiconductor material of mobility and corresponding thin film transistor (TFT) is that those skilled in the art need
The technical issues of solution.
Summary of the invention
The application provides a kind of sull and preparation method, transistor and preparation method, display backboard, existing to solve
The problem for having the mobility of thin film transistor (TFT) in technology low.
According in a first aspect, providing a kind of sull in a kind of embodiment, the ingredient of the sull is packet
Include one of Zn, In and Sn or a variety of and H oxide.
Optionally, the electronic carrier field-effect mobility of the sull is greater than or equal to 100cm2/Vs。
Optionally, the oxide is gallium indium zinc oxide.
According to second aspect, a kind of preparation method of above-mentioned sull is provided in a kind of embodiment, this method includes
Following steps:
Channel layer is formed on underlay substrate, wherein the ingredient of the channel layer be include one of Zn, In and Sn or
A variety of oxides；
The channel layer is hydrogenated, hydrogenated amorphous sull is formed, wherein the electricity of the hydrogenated amorphous sull
Sub- carrier field-effect mobility is greater than or equal to 100cm2/Vs。
Optionally, described that channel layer is formed on underlay substrate, comprising the following steps: in the gas comprising oxygen and argon gas
In atmosphere, one of gallium indium zinc oxygen, zinc oxide, indium oxide and tin indium oxide are regard as target, in a manner of rf magnetron sputtering
Form the channel layer, wherein the partial pressure of the oxygen is between 0% to 90%.
Optionally, the rf magnetron sputtering mode is formed in the technique of the channel layer, and the partial pressure of the oxygen is
25%.
Optionally, the channel layer is hydrogenated, hydride amorphous oxide thin film is formed, comprising the following steps:
Use silane and ammonia as process gas, using plasma reinforced chemical vapour deposition mode, in the channel
Passivation layer is formed on layer；Wherein, the passivation layer includes silicon nitride layer and/or silicon oxide layer；
In nitrogen atmosphere, thermal annealing is carried out.
Optionally, formed on the channel layer in the technique of passivation layer, the partial pressure of the silane 0.5%-10% it
Between, for the partial pressure of the ammonia between 0.5%-20%, depositing temperature is greater than or equal to 100 DEG C.
Optionally, in thermal anneal process, annealing temperature is 350 DEG C, and annealing time is 1 hour.
Optionally, it is formed on underlay substrate in the technique of channel layer, the underlay substrate includes glass substrate, Metal Substrate
One of plate, plastic base and organic film substrate are a variety of.
According to the third aspect, a kind of transistor is provided in a kind of embodiment, the transistor includes sull channel
Layer；The ingredient of the used sull of sull channel layer be include one of Zn, In and Sn or a variety of, with
And the oxide of H.
Optionally, the transistor further include: substrate, gate electrode, gate insulation layer, source electrode, drain electrode and passivation layer,
In:
The gate electrode setting is on substrate；
The gate insulation layer is covered on the gate electrode and on the part of substrate not covered by gate electrode；
The sull channel layer setting is on the gate insulation layer and on position corresponding with gate electrode；
The side of the sull channel layer is arranged in the source electrode；
The other side of the sull channel layer is arranged in the drain electrode；
The passivation layer is arranged on drain electrode, source electrode and sull channel layer not by the drain electrode and source
Electrode covering part on, and between the passivation layer on drain electrode and sull channel layer and source electrode and oxide it is thin
There is conductive hole between passivation layer on film channel layer.
Optionally, the passivation layer includes silicon dioxide layer and/or silicon nitride layer.
According to fourth aspect, a kind of embodiment provides a kind of preparation method of above-mentioned transistor, and this method includes following step
It is rapid:
Depositing gate electrode on substrate；
The gate insulation layer of the gate electrode and substrate is covered in gate electrode disposed thereon；
The deposition oxide thin film channel layer on gate insulation layer, the used sull of sull channel layer
Ingredient be include one of Zn, In and Sn or a variety of and H oxide；
Source electrode and drain electrode is deposited respectively at the both ends of the sull channel layer；
Hydrogen-rich passivation layer is deposited on the source electrode, drain electrode and sull channel layer；
Carry out thermal annealing.
According to the 5th aspect, a kind of embodiment provides a kind of display backboard, which includes above-mentioned transistor.
Sull and preparation method, transistor and preparation method, display backboard according to above-described embodiment, the oxygen
The ingredient of compound film be include one of Zn, In and Sn or a variety of and H oxide, by sull into
Row hydrogenation, can effectively improve the carrier mobility of sull, using the sull as the channel of transistor
Layer, to further increase the carrier mobility of transistor, effectively meets the needs of display technology is to high mobility.
Detailed description of the invention
Fig. 1 is a kind of flow diagram of the preparation method of sull provided in an embodiment of the present invention；
Fig. 2 is the post-depositional membrane structure schematic diagram of channel layer provided in an embodiment of the present invention；
Fig. 3 is a kind of solid state diffusion process flow diagram provided in an embodiment of the present invention；
Fig. 4 is the membrane structure schematic diagram after a kind of deposit passivation layer provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram of transistor provided in an embodiment of the present invention；
Fig. 6 is a kind of flow diagram of crystal tube preparation method provided in an embodiment of the present invention；
Fig. 7 is the transistor arrangement schematic diagram after depositing gate electrode provided in an embodiment of the present invention；
Fig. 8 is the transistor arrangement schematic diagram after deposition gate insulation layer provided in an embodiment of the present invention；
Fig. 9 is the transistor arrangement schematic diagram after deposition oxide thin film channel layer provided in an embodiment of the present invention；
Figure 10 is the transistor arrangement schematic diagram after deposition source electrode and drain electrode provided in an embodiment of the present invention；
Figure 11 is the transistor arrangement schematic diagram after deposition hydrogen-rich passivation layer provided in an embodiment of the present invention；
Figure 12 is a kind of output characteristic curve of transistor provided in an embodiment of the present invention；
Figure 13 is a kind of transfer characteristic curve of transistor provided in an embodiment of the present invention.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.
Sull provided in an embodiment of the present invention, the ingredient of the sull include in Zn, In and Sn element
One or more and H oxides.In the specific implementation, the sull can be thin for hydrogenated amorphous oxide
Film；More specifically, the sull can be gallium indium zinc oxide (English: indium gallium zinc
Oxide, referred to as: IGZO), zinc oxide (chemical formula ZnO), indium oxide (chemical formula In2O3) and tin indium oxide (it is English:
Indium tin oxide, referred to as: ITO) one of or a variety of mixtures, the obtained amorphous oxides after over hydrogenation
Film.Moreover, in embodiments of the present invention, electronic carrier field-effect mobility can achieve 100cm2/ Vs or more.
It is a kind of flow diagram of the preparation method of sull provided in an embodiment of the present invention, the oxygen referring to Fig. 1
The preparation method of compound film the following steps are included:
Step S101: forming channel layer on underlay substrate, wherein the ingredient of the channel layer is to include in Zn, In and Sn
One or more oxides.
It is the post-depositional membrane structure schematic diagram of channel layer provided in an embodiment of the present invention, in the present invention see also Fig. 2
In embodiment, using the method for rf magnetron sputtering under room temperature environment on underlay substrate 1 depositing trench layer 2.
Wherein, underlay substrate 1 is using glass substrate.Certainly, in the specific implementation, the underlay substrate 1 can make
With one of glass substrate, metal substrate, plastic base and organic film substrate or a variety of.
In rf magnetron sputtering technical process, target be can choose using in IGZO, zinc oxide, indium oxide and ITO
It is one or more.Preferably, selection uses IGZO in embodiments of the present invention, to form the channel layer 2 being made of IGZO.It penetrates
The process gas of frequency magnetron sputtering includes oxygen and argon gas, and wherein the partial pressure range of oxygen is between 0% to 90%, preferably
Ground, the partial pressure of the oxygen are 25%.
In addition, it is necessary to explanation, the technique of depositing trench layer 2 is not limited to rf magnetron sputtering side on underlay substrate 1
Method can also use the methods of sol-gal process, direct current or reactive magnetron sputtering method.
Step S102: hydrogenating the channel layer, forms hydrogenated amorphous sull.
Solid-state diffusion method, hydrogen plasma can be used in the specific implementation in hydrogenated amorphous sull in order to obtain
The methods of facture, hydrogen ion implantation or hydrogen environment annealing method realize the hydrogenation treatment to channel layer 2.
In embodiments of the present invention, the hydrogenation process of channel layer will be described in detail by taking solid-state diffusion method as an example.
It is a kind of solid state diffusion process flow diagram provided in an embodiment of the present invention, which includes following referring to Fig. 3
Step:
Step S1021: passivation layer is formed on the channel layer.
It referring to fig. 4, is the membrane structure schematic diagram after a kind of deposit passivation layer provided in an embodiment of the present invention, such as Fig. 4 institute
Show, the embodiment of the present invention is using plasma reinforced chemical vapour deposition (English: Plasma Enhanced Chemical Vapor
Deposition, referred to as: PECVD) method in the top growth of passivation layer 3 of channel layer 2, the material of the passivation layer 3 is nitrogen
SiClx (chemical formula SiNx) material, the process gas of chemical vapor deposition include silane (chemical formula SiH4) and ammonia
(chemical formula NH3)；Wherein, the partial pressure of the silane is between 0.5%-10%, it is preferable that is greater than or equal to 1%；The ammonia
The partial pressure of gas is between 0.5%-20%, it is preferable that is greater than or equal to 1%；Depositing temperature is greater than or equal to 100 DEG C.
The above process is only a kind of exemplary embodiment for forming passivation layer provided in an embodiment of the present invention, is being embodied
When, the passivation layer 3 can also be the double-layer structure of silica and silicon nitride；Moreover, the method for generating passivation layer 3 is also not necessarily limited to
PECVD method can also use the methods of atomic layer deposition.
Step S1022: thermal annealing is carried out.
After obtaining membrane structure as shown in Figure 4, it is also necessary to anneal to above structure, so that protium is from blunt
Change in layer 3 and diffuse to channel layer 2, forms hydrogenated amorphous sull.
Specifically, in nitrogen range, thermal annealing is carried out to structure shown in Fig. 4, annealing temperature is 350 DEG C, when annealing
Between be 1 hour.Certainly, in the specific implementation, above-mentioned annealing time and annealing temperature are only a preferred parameter values, the annealing temperature
Degree and annealing time can be set to other any numerical value, in embodiments of the present invention without limitation.
The sull of preparation of the embodiment of the present invention, carrier field-effect mobility are greater than 100cm2/ Vs, effectively mentions
High mobility, so as to meet the needs of display is to high mobility oxide film material.
Sull based on the above embodiment, the embodiment of the invention also provides a kind of transistor, the transistor
Using above-mentioned sull as channel layer, to further improve the carrier mobility of transistor.Wherein, the crystal
Pipe can be understood as field effect transistor or thin film transistor (TFT).
It is a kind of structural schematic diagram of transistor provided in an embodiment of the present invention referring to Fig. 5, which is bottom gate apical grafting
Touch the transistor of structure, including substrate 11, gate electrode 12, gate insulation layer 13, sull channel layer 14, source electrode 15, leakage
Electrode 16 and passivation layer 17.
Wherein, the gate electrode 12 is arranged on substrate 11.In the specific implementation, the substrate 11 can select glass base
One of plate, metal substrate, plastic base and organic film substrate or a variety of combinations.The material of the gate electrode 12 includes
But one of it is not limited to molybdenum, titanium and aluminium or a variety of and other alloy materials.
The gate insulation layer 13 is covered on the gate electrode 12 and the part of substrate 11 not covered by gate electrode 12
On.The gate insulation layer 13 includes that nitridation silicon single-layer, oxidation silicon single-layer or silica and silicon nitride are double-deck.
The sull channel layer 14 is arranged on the gate insulation layer 13 and position corresponding with gate electrode 12
On.The ingredient of the used sull of the sull channel layer 14 be include one of Zn, In and Sn or a variety of,
And the oxide of H；More specifically, the material of the sull channel layer 14 includes but is not limited to after hydrogenating
One of IGZO, zinc oxide, indium oxide and ITO or a variety of.
The side of the sull channel layer 14 is arranged in the source electrode 15, and the drain electrode 16 is arranged described
The other side of sull channel layer 14.In embodiments of the present invention, material used in the source electrode 15 and drain electrode 16
Material includes but is not limited to one of molybdenum, titanium and aluminium or a variety of and other alloy materials.
The passivation layer 17 is arranged on source electrode 15, drain electrode 16 and sull channel layer 14 not by the source
On the part that electrode 15 and drain electrode 16 cover, and between the passivation layer 17 in source electrode 15 and sull channel layer 14 with
And there is conductive hole between the passivation layer 17 on drain electrode 16 and sull channel layer 14, the conductive hole is for source electricity
Pole 15 and drain electrode 15 connect.
In addition, it is necessary to explanation, transistor provided in an embodiment of the present invention is only an exemplary embodiment, the crystal
Pipe can also be transistor of other structures, such as top-gated top contact, the contact of top-gated bottom or the contact of bottom gate bottom etc., but all make
It uses the oxide film material of above-described embodiment as the transistor of channel layer, protection scope of the present invention should all be fallen into.
In order to prepare transistor shown in fig. 5, the embodiment of the present invention also provides a kind of crystal tube preparation method.
It is a kind of flow diagram of crystal tube preparation method provided in an embodiment of the present invention referring to Fig. 6, this method includes
Following steps:
Step S201: depositing gate electrode on substrate.
It is the transistor arrangement schematic diagram after depositing gate electrode provided in an embodiment of the present invention referring to Fig. 7, of the invention real
Apply in example, using the method for magnetically controlled DC sputtering at room temperature on substrate 11 depositing gate electrode 12, and use photoetching process figure
Change.Wherein, the material of substrate 11 is glass substrate, and the material of gate electrode 12 is molybdenum.The power of magnetically controlled DC sputtering is 500W, work
Skill gas is argon gas.
Certainly, it should be noted that the growing method of gate electrode includes but is not limited to direct current magnetron sputtering process, can also be made
With such as the methods of thermal evaporation.
Step S202: the gate insulation layer of the gate electrode and substrate is covered in gate electrode disposed thereon.
It is the transistor arrangement schematic diagram after deposition gate insulation layer provided in an embodiment of the present invention, in the present invention referring to Fig. 8
In embodiment, using PECVD method gate electrode 12 disposed thereon gate insulation layer 13.The material of gate insulation layer 13 is oxidation
Silicon (chemical formula SiOx) material, the process gas of chemical vapor deposition include silane (chemical formula SiH4) and an oxidation
Phenodiazine (chemical formula N2O)；Wherein, the partial pressure of silane is 5%, and the partial pressure of nitrous oxide is 80%, and depositing temperature is 300
℃.In the specific implementation, the growing method of gate insulation layer is not limited to above-mentioned PECVD method, can also use such as atomic layer deposition
Long-pending mode deposits gate insulation layer.
Step S203: the deposition oxide thin film channel layer on gate insulation layer, the sull channel layer are used
The ingredient of sull be include one of Zn, In and Sn or a variety of and H oxide.
It is the transistor arrangement schematic diagram after deposition oxide thin film channel layer provided in an embodiment of the present invention referring to Fig. 9,
In embodiments of the present invention, using the method for rf magnetron sputtering under room temperature environment on gate insulation layer 13 deposition oxide film
Channel layer 14, and it is graphical using photoetching process.Wherein, the channel layer materials of magnetron sputtering use IGZO.The process gas of sputtering
Body includes oxygen and argon gas, and wherein the partial pressure range of oxygen is between 0% to 90%, it is preferable that the partial pressure of oxygen is with 25%.
Specifically, the growth pattern of sull may refer to the description of above-mentioned sull preparation process embodiment, herein not
It repeats again.
Step S204: source electrode and drain electrode is deposited respectively at the both ends of the sull channel layer.
It is the transistor arrangement schematic diagram after deposition source electrode and drain electrode provided in an embodiment of the present invention referring to Figure 10,
In embodiments of the present invention, source electrode 15 and drain electrode 16 are deposited using the method for magnetically controlled DC sputtering at room temperature, and uses light
Carving technology is graphical.Wherein, the material of source electrode 15 and drain electrode 16 is molybdenum.The power of magnetically controlled DC sputtering is 500W, technique
Gas is argon gas.Moreover, in the specific implementation, the growing method of gate electrode includes but is not limited to direct current magnetron sputtering process, may be used also
To use such as the methods of thermal evaporation.
Step S205: hydrogen-rich passivation layer is deposited on the gate electrode, drain electrode and sull channel layer.
It is the transistor arrangement schematic diagram after deposition hydrogen-rich passivation layer provided in an embodiment of the present invention, at this referring to Figure 11
In inventive embodiments, using the method for PECVD in the upper of the source electrode 15, drain electrode 16 and sull channel layer 14
Fang Shengchang hydrogen-rich passivation layer 17, and it is graphical using photoetching process.The material of hydrogen-rich passivation layer is that (chemical formula is silicon nitride
SiNx) material, the process gas of chemical vapor deposition include silane and ammonia；Wherein, the partial pressure of silane is in 0.5%-10%
Between between, it is preferable that be greater than or equal to 1%；The partial pressure of the ammonia is between 0.5%-20%, it is preferable that is greater than or waits
In 1%；The depositing temperature is greater than or equal to 100 DEG C.Specifically, the growth pattern of hydrogen-rich passivation layer may refer to above-mentioned oxidation
The description of object thin film preparation process embodiment, details are not described herein.
Step S206: thermal annealing is carried out.
In embodiments of the present invention, hydrogen diffusion in thermal annealing in hydrogen-rich passivation layer 17 is made using the method for solid-state diffusion
To sull channel layer 14, hydrogenated amorphous sull is formed, the temperature of thermal annealing is 350 DEG C, and anneal duration is 1
Hour, atmosphere is N2.Specifically, thermal anneal process also can be found in retouching for above-mentioned sull preparation process embodiment
It states, details are not described herein.
Referring to Figure 12, it is a kind of output characteristic curve of transistor provided in an embodiment of the present invention, tests and draw this
Output characteristic curve of one thin film transistor (TFT) of embodiment preparation at 25 DEG C of room temperature.In grid voltage VGSWhen=15V, source and drain
Voltage VDSIt is set as the drain current I of 0VDS=7.17 × 10-8A, source-drain voltage VDSIt is set as the drain current I of 20VDS=
2.91×10-3A。
Referring to Figure 13, it is a kind of transfer characteristic curve of transistor provided in an embodiment of the present invention, tests and draw this reality
Apply transfer characteristic curve of the thin film transistor (TFT) of example preparation at 25 DEG C of room temperature.In drain voltage VDSWhen=0.1V, grid
Voltage VGSIt is set as the drain current I of -5.5VDS=1.04 × 10-10A, grid voltage VGSIt is set as the drain current I of 20VDS=
2.56×10-5A, and it is 352cm that extraction, which obtains the field-effect mobility of the thin film transistor (TFT),2V1s-1.It can be seen that the present invention is real
The transistor for applying example preparation, effectively increases the mobility of transistor, migrates so as to meet display device to transistor height
The requirement of rate.
The embodiment of the invention also provides a kind of display backboard, the display backboard is equipped with the crystal in above-described embodiment
Pipe, since the transistor has very high mobility, so that support of the display backboard to new display technology be effectively ensured.
Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not to limit
The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple
It deduces, deform or replaces.
Claims (11)
1. a kind of preparation method of sull, which comprises the following steps:
Channel layer is formed on underlay substrate, wherein it includes one of Zn, In and Sn or a variety of that the ingredient of the channel layer, which is,
Oxide；
The channel layer is hydrogenated, hydrogenated amorphous sull is formed, wherein the electronics of the hydrogenated amorphous sull carries
It flows subfield effect mobility and is greater than or equal to 100cm2/Vs；
It is described that channel layer is formed on underlay substrate, comprising the following steps: in the atmosphere comprising oxygen and argon gas, by gallium
One of indium zinc oxygen, zinc oxide, indium oxide and tin indium oxide are used as target, and the channel is formed in a manner of rf magnetron sputtering
Layer；
The rf magnetron sputtering mode is formed in the technique of the channel layer, and the partial pressure of the oxygen is 25%；
The hydrogenation channel layer, forms hydride amorphous oxide thin film, comprising the following steps:
Use silane and ammonia as process gas, using plasma reinforced chemical vapour deposition mode, on the channel layer
Form passivation layer；Wherein, the passivation layer includes silicon nitride layer and/or silicon oxide layer；
In nitrogen atmosphere, thermal annealing is carried out；
It is formed on the channel layer in the technique of passivation layer, the partial pressure of the silane is between 0.5%-10%, the ammonia
Partial pressure between 0.5%-20%, depositing temperature be greater than or equal to 100 DEG C.
2. the preparation method of sull as described in claim 1, which is characterized in that in thermal anneal process, annealing temperature
Degree is 350 DEG C, and annealing time is 1 hour.
3. the preparation method of sull as described in claim 1, which is characterized in that form channel layer on underlay substrate
Technique in, the underlay substrate includes one of glass substrate, metal substrate, plastic base and organic film substrate or more
Kind.
4. a kind of sull, which is characterized in that the sull is made up of claim 1-3 either method；
The ingredient of the sull be include one of Zn, In and Sn or a variety of and H oxide.
5. sull as claimed in claim 4, which is characterized in that the electronic carrier field-effect of the sull
Mobility is greater than or equal to 100cm2/Vs。
6. sull as claimed in claim 4, which is characterized in that the oxide is gallium indium zinc oxide.
7. a kind of transistor, which is characterized in that the transistor includes sull channel layer；The sull channel
Sull used by layer is made up of claim 1-3 either method；
The ingredient of the sull be include one of Zn, In and Sn or a variety of and H oxide.
8. transistor as claimed in claim 7, which is characterized in that the transistor further include: substrate, gate electrode, gate insulation
Layer, source electrode, drain electrode and passivation layer, in which:
The gate electrode setting is on substrate；
The gate insulation layer is covered on the gate electrode and on the part of substrate not covered by gate electrode；
The sull channel layer setting is on the gate insulation layer and on position corresponding with gate electrode；
The side of the sull channel layer is arranged in the source electrode；
The other side of the sull channel layer is arranged in the drain electrode；
The passivation layer is arranged on drain electrode, source electrode and sull channel layer not by the drain electrode and source electrode
On the part of covering, and between the passivation layer on drain electrode and sull channel layer and source electrode and sull ditch
There is conductive hole between passivation layer in channel layer.
9. transistor as claimed in claim 8, which is characterized in that the passivation layer includes silicon dioxide layer and/or silicon nitride
Layer.
10. a kind of preparation method of transistor, which comprises the following steps:
Depositing gate electrode on substrate；
The gate insulation layer of the gate electrode and substrate is covered in gate electrode disposed thereon；
The deposition oxide thin film channel layer on gate insulation layer, the sull channel layer are passed through using sull
If claim 1-3 either method is made, wherein ingredient be include one of Zn, In and Sn or a variety of and H oxidation
Object；
Source electrode and drain electrode is deposited respectively at the both ends of the sull channel layer；
Hydrogen-rich passivation layer is deposited on the source electrode, drain electrode and sull channel layer；
Carry out thermal annealing.
11. a kind of display backboard, which is characterized in that including the transistor as described in claim 7 to 9 is any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610894719.3A CN106298880B (en) | 2016-10-13 | 2016-10-13 | Sull and preparation method, transistor and preparation method, display backboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610894719.3A CN106298880B (en) | 2016-10-13 | 2016-10-13 | Sull and preparation method, transistor and preparation method, display backboard |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298880A CN106298880A (en) | 2017-01-04 |
| CN106298880B true CN106298880B (en) | 2019-08-27 |
Family
ID=57717429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610894719.3A Active CN106298880B (en) | 2016-10-13 | 2016-10-13 | Sull and preparation method, transistor and preparation method, display backboard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298880B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766890B (en) * | 2018-04-13 | 2020-10-02 | 北京理工大学 | Method for preparing metal oxide thin film transistor at low temperature |
| CN109449086B (en) * | 2018-11-08 | 2021-01-15 | 中山大学 | Thin film transistor, preparation method thereof and display device |
| CN115497831B (en) * | 2022-09-23 | 2023-06-20 | 西安工程大学 | Method for optimizing interface of amorphous InGaZn-O thin film transistor at room temperature |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101258607A (en) * | 2005-09-06 | 2008-09-03 | 佳能株式会社 | Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous |
| CN104037234A (en) * | 2014-07-01 | 2014-09-10 | 武汉大学 | Hydrogen-passivated zinc oxide-base thin film transistor and preparation method thereof |
| CN105118856A (en) * | 2008-10-24 | 2015-12-02 | 株式会社半导体能源研究所 | Oxide semiconductor, thin film transistor, and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101511076B1 (en) * | 2009-12-08 | 2015-04-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
-
2016
- 2016-10-13 CN CN201610894719.3A patent/CN106298880B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101258607A (en) * | 2005-09-06 | 2008-09-03 | 佳能株式会社 | Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous |
| CN105118856A (en) * | 2008-10-24 | 2015-12-02 | 株式会社半导体能源研究所 | Oxide semiconductor, thin film transistor, and display device |
| CN104037234A (en) * | 2014-07-01 | 2014-09-10 | 武汉大学 | Hydrogen-passivated zinc oxide-base thin film transistor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106298880A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104064688B (en) | There is manufacture method and this TFT substrate of the TFT substrate of storage electric capacity | |
| CN103745978B (en) | Display device, array base palte and preparation method thereof | |
| CN106128963B (en) | Thin film transistor (TFT) and preparation method, array substrate and preparation method, display panel | |
| CN103700706B (en) | Preparation method of thin film transistor and array substrate | |
| CN102842619B (en) | A kind of semiconductor device and manufacture method thereof | |
| CN106129086B (en) | TFT substrate and preparation method thereof | |
| CN102683422A (en) | Oxide thin film transistor and manufacturing method thereof as well as array substrate and display device | |
| CN104037090B (en) | Oxide thin film transistor construction manufacturing method and oxide thin film transistor structure | |
| CN106298879B (en) | The production method of top-gated and vertical structure TFT | |
| CN104241392A (en) | Thin-film transistor, preparation method of thin-film transistor, display substrate and display device | |
| CN102522429A (en) | Thin film transistor on basis of metal oxide and preparation method and application thereof | |
| CN106128944A (en) | The manufacture method of metal oxide thin-film transistor array base palte | |
| CN105633170A (en) | Metal oxide thin film transistor and preparation method therefor, array substrate and display apparatus | |
| CN106298880B (en) | Sull and preparation method, transistor and preparation method, display backboard | |
| CN105006487A (en) | Top gate self-aligned metal oxide semiconductor thin-film transistor and preparation method thereof | |
| CN104867985A (en) | Thin film transistor, preparation method thereof, array substrate and display apparatus | |
| CN104576753B (en) | A kind of low-temperature polysilicon film transistor and its manufacturing method | |
| CN103346089A (en) | Self-aligned double-layer channel metallic oxide thin film transistor and manufacturing method thereof | |
| CN104362179A (en) | Thin-film transistor, manufacturing method of thin-film transistor, array substrate and display device | |
| CN102646715A (en) | TFT (thin film transistor) and manufacturing method thereof | |
| CN104576399A (en) | Film transistor and manufacturing method thereof | |
| CN104681491B (en) | Cmos circuit structure, its preparation method, display base plate and display device | |
| CN102709185A (en) | Polysilicon active layer-containing thin film transistor, manufacturing method thereof and array substrate | |
| CN104157610A (en) | Manufacture method of oxide semiconductor TFT substrate, and structure of the oxide semiconductor TFT substrate | |
| CN109148597A (en) | Thin film transistor (TFT) and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |