CN106298804B - Dot structure and preparation method thereof and display panel - Google Patents
Dot structure and preparation method thereof and display panel Download PDFInfo
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- CN106298804B CN106298804B CN201610726282.2A CN201610726282A CN106298804B CN 106298804 B CN106298804 B CN 106298804B CN 201610726282 A CN201610726282 A CN 201610726282A CN 106298804 B CN106298804 B CN 106298804B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
The present invention relates to a kind of dot structure and preparation method thereof and display panels.Above-mentioned dot structure includes: substrate；Column active layer, is disposed on the substrate, and column active layer includes that source electrode, drain electrode and the channel between source electrode and drain electrode, source electrode, channel and drain electrode are stacked；First insulating layer around the outside for coating column active layer and covers substrate；First conductive layer, around the outside for being coated on the first insulating layer；First capacitor dielectric layer, around the outside for being coated on the first conductive layer；Second conductive layer, around the outside for being coated on first capacitor dielectric layer；Second capacitor dielectric layer, around the outside for being coated on the second conductive layer；Second insulating layer, the top of the first insulating layer of covering, the first conductive layer, first capacitor dielectric layer, the second conductive layer and the second capacitor dielectric layer；Pixel electrode is arranged on column active layer, connects with source electrode or drain electrode.Dot structure of the invention reduces the area of TFT unit, improves the PPI of display panel.
Description
Technical field
The present invention relates to display panel fields, more particularly to a kind of dot structure and preparation method thereof and display surface
Plate.
Background technique
In recent years, the raising of the pixel density (PPI) of display panel is generally limited to thin film transistor (TFT) in dot structure
(TFT) PPI can be improved by the size and wiring spacing that reduce TFT in size and wiring spacing.For example,
Wiring spacing can be reduced by the method for common electrode, achieve the effect that improve PPI.However, due to traditional dot structure
It is substantially all the form for being similar to and making a cake to tile from level to level, reduces pixel by TFT size and wiring spacing is reduced
The area that structure is occupied is very limited, and the development of PPI is caused to be in bottleneck period, it is difficult to continue to improve PPI.
Summary of the invention
Based on this, it is necessary to aiming at the problem that development of PPI is in bottleneck period, is difficult to continue to improve PPI, provide a kind of energy
Enough increase substantially the dot structure of PPI.
A kind of dot structure, comprising:
Substrate；
Column active layer, on the substrate, the column active layer includes source electrode, drains and positioned at the source for setting
Channel between pole and the drain electrode, the source electrode, the channel and the drain electrode are stacked；
First insulating layer around the outside for coating the column active layer and covers the substrate；
First conductive layer, around the outside for being coated on first insulating layer；
First capacitor dielectric layer, around the outside for being coated on first conductive layer；
Second conductive layer, around the outside for being coated on the first capacitor dielectric layer；
Second capacitor dielectric layer, around the outside for being coated on second conductive layer；
Second insulating layer covers first insulating layer, first conductive layer, the first capacitor dielectric layer, described
The top of second conductive layer and the second capacitor dielectric layer；
And pixel electrode, it is arranged on the column active layer, is connected with the source electrode or the drain electrode.
Compared with traditional dot structure to tile from level to level, above-mentioned dot structure proposed by the present invention is circular column
Shape forms solid type ring-type coated TFT, area shared by TFT unit is reduced, to improve the PPI of display panel.
The contact for exposing the column active layer is provided in the second insulating layer in one of the embodiments,
Hole, the contact hole are oppositely arranged with the column active layer, the pixel electrode by the contact hole and the source electrode or
Drain connection described in person.
The dot structure further includes the buffer layer of setting on the substrate in one of the embodiments,.
The buffer layer includes silicon nitride layer and the oxidation stacked gradually on the substrate in one of the embodiments,
Silicon layer.
The pixel electrode is selected from zinc, Zinc-tin alloy, indium stannum alloy, indium kirsite, indium gallium in one of the embodiments,
At least one of kirsite and indium Zinc-tin alloy.
A kind of preparation method of dot structure is also provided, comprising the following steps:
On substrate formed column active layer, the column active layer include source electrode, drain electrode and be located at the source electrode and
Channel between the drain electrode, the source electrode, the channel and the drain electrode are stacked；
The first insulating layer is formed on the outside of the column active layer and the substrate；
The first conductive layer around cladding is formed in the outside of first insulating layer；
The first capacitor dielectric layer around cladding is formed in the outside of first conductive layer；
The second conductive layer around cladding is formed in the outside of the first capacitor dielectric layer；
The second capacitor dielectric layer around cladding is formed in the outside of second conductive layer；
First insulating layer, first conductive layer, the first capacitor dielectric layer, second conductive layer and
The top of the second capacitor dielectric layer forms second insulating layer；
Pixel electrode, the pixel electrode and the source electrode or the drain electrode are formed on the top of the column active layer
Connection.
Compared with traditional dot structure to tile from level to level, the system proposed by the present invention by above-mentioned dot structure
The dot structure that Preparation Method is prepared is circular cylindrical, forms solid type ring-type coated TFT, reduces shared by TFT unit
Area, to improve the PPI of display panel.
In one of the embodiments, the step of forming column active layer on substrate are as follows:
The first amorphous silicon layer is deposited on the substrate；
The first polysilicon layer is generated by the first amorphous silicon layer described in crystallization；
The first polysilicon layer adulterated after first polysilicon layer by ion implanting formation is patterned, to form source
Pole；
The second amorphous silicon layer is formed on the source electrode；
The second polysilicon layer is generated by the second amorphous silicon layer described in crystallization；
The second polysilicon layer adulterated after second polysilicon layer by ion implanting formation is patterned, to form ditch
Road；
Third amorphous silicon layer is formed on the channel；
Third polysilicon layer is generated by third amorphous silicon layer described in crystallization；
The third polysilicon layer adulterated after the third polysilicon layer by ion implanting formation is patterned, to form leakage
Pole.
It in one of the embodiments, further include position opposite with the column active layer on the second insulating layer
The step of forming the contact hole for exposing the column active layer, the pixel electrode pass through the contact hole and the source electrode
Or the drain electrode connection.
It further include in the substrate in one of the embodiments, before the step of forming column active layer on substrate
The step of upper formation buffer layer.
In addition, a kind of display panel is also provided, including above-mentioned dot structure.Since above-mentioned dot structure is circular column
Shape forms solid type ring-type coated TFT, area shared by TFT unit is reduced, to improve the PPI of display panel.
Detailed description of the invention
Fig. 1 is the flow chart of the preparation method of the dot structure of an embodiment；
Fig. 2 is the schematic diagram of the buffer layer for preparing dot structure of an embodiment；
Fig. 3 is the flow chart that column active layer is formed on the buffer layer of dot structure of an embodiment；
Fig. 4 is the schematic diagram of the column active layer for preparing dot structure of an embodiment；
Fig. 5 is the schematic diagram of the first insulating layer for preparing dot structure of an embodiment；
Fig. 6 is the schematic diagram of the first conductive layer for preparing dot structure of an embodiment；
Fig. 7 is the schematic diagram of the first capacitor dielectric layer for preparing dot structure of an embodiment；
Fig. 8 is the schematic diagram of the second conductive layer for preparing dot structure of an embodiment；
Fig. 9 is the schematic diagram of the second capacitor dielectric layer for preparing dot structure of an embodiment；
Figure 10 is the schematic diagram of the second insulating layer for preparing dot structure of an embodiment；
Figure 11 is the schematic diagram of the pixel electrode for preparing dot structure of an embodiment；
Figure 12 is the schematic cross-section of the dot structure of an embodiment.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.Many details are explained in the following description in order to fully understand this hair
It is bright.But the invention can be embodied in many other ways as described herein, those skilled in the art can be not
Similar improvement is done in the case where violating intension of the present invention, therefore the present invention is not limited by the specific embodiments disclosed below.
As shown in Figure 1, the preparation method of the dot structure of an embodiment, comprising the following steps:
S100, column active layer is formed on substrate, column active layer includes source electrode, drains and positioned at source electrode and drain electrode
Between channel, source electrode, channel and drain electrode are stacked.
Fig. 2 is referred to, substrate 100 can be by SiO2Make transparent glass material as main component to be made.Alternatively, substrate
100 can also be made of the other materials of opaque material or such as plastic components etc.However, being embodied in substrate for image
For the bottom emission organic light-emitting display device of 100 sides, substrate 100 must be made of clear material.
In a preferred embodiment, before the step of forming column active layer 120 on the substrate 100, dot structure
Preparation method may also include on the substrate 100 formed buffer layer 110 the step of, as shown in Figure 2.Buffer layer 110 is to promote
The levelness of substrate and the intrusion for preventing impurity.Buffer layer 110 includes 111 He of silicon nitride layer stacked gradually on the substrate 100
Silicon oxide layer 112.SiN can be usedxAnd/or SiOxBy such as plasma enhanced chemical vapor deposition (PECVD) technology,
The various deposition techniques of atmospheric pressure cvd (APCVD) technology and low pressure chemical vapor deposition (LPCVD) technology etc carry out buffer layer 110.
Wherein, as shown in Figure 3 and Figure 4, the step of forming column active layer 120 on buffer layer 110 are as follows:
S110, the first amorphous silicon layer is deposited on the buffer layer.
Can using such as plasma enhanced chemical vapor deposition (PECVD) technology, atmospheric pressure cvd (APCVD) technology and
The various deposition techniques of low pressure chemical vapor deposition (LPCVD) technology etc deposit the first amorphous silicon layer.
S120, the first polysilicon layer is generated by the first amorphous silicon layer of crystallization.
First amorphous silicon layer can pass through such as rapid thermal annealing (Rapid Thermal Annealing, RTA), quasi- point
Sub- laser annealing (Excimer laser Annealing, ELA), solid phase crystallization (Solid Phase Crystallization,
SPC), metal inducement crystallization (Metal Induced Crystallization, MIC), metal inducement transverse direction crystallization
(Metal Induced Lateral Crystallization, MILC) or continuously lateral crystallize (Sequential Lateral
Solidification, SLS) etc various technologies by crystallization.
The first polysilicon layer of doping is formed after S130, the first polysilicon layer of patterning, by ion implanting to be formed
Source electrode.
The electrode pattern of source electrode 121 can be formed by exposure etching, wherein etching can be carved using dry or wet
Erosion.The form that can be injected using P+ or P- when doping.
S140, the second amorphous silicon layer is formed on source electrode.
The method of the second amorphous silicon layer is formed referring to S110.
S150, the second polysilicon layer is generated by the second amorphous silicon layer of crystallization.
Specific method is referring to S120.
The second polysilicon layer of doping is formed after S160, the second polysilicon layer of patterning, by ion implanting to be formed
Channel.
Channel 122 is covered on source electrode 121, therefore the electrode pattern of the electrode pattern of channel 122 and source electrode 121 keeps one
It causes, can also be formed by exposure etching.Wherein, etching can use dry or wet etch.When doping can using P+ or
The form of P- injection.Certainly, source electrode 121 is different with the doping way of channel 122.When source electrode 121 is injected using P-, channel
122 are injected using P+.
S170, third amorphous silicon layer is formed on channel.
The method of third amorphous silicon layer is formed referring to S110.
S180, third polysilicon layer is generated by crystallization third amorphous silicon layer.
Specific method is referring to S120.
The third polysilicon layer of doping is formed after S190, patterning third polysilicon layer, by ion implanting to be formed
Drain electrode.
The doping way of drain electrode 123 is identical as the doping way of source electrode 121.Certainly, the position of source electrode 121 and drain electrode 123
It can be interchanged.
As shown in figure 4, foring column active layer on buffer layer 110 in the preparation method of dot structure of the invention
120.Column active layer 120 include stack gradually source electrode 121, channel 122 and drain electrode 123, this be different from traditional source electrode,
The form that channel and drain electrode are arranged on substrate or buffer layer, therefore, this preparation method of the invention takes full advantage of
Solid space, reduces the area of plane of active layer occupancy, to reduce the size of TFT, is conducive to improve PPI.
It should be noted that buffer layer 110 can be arranged on the substrate 100 according to demand, certainly, it can also be not provided with buffer layer
110.When not needing setting buffer layer 110, column active layer 120 can be directly formed on the substrate 100.
S200, the first insulating layer is formed on the outside of column active layer and substrate.
First insulating layer 130 can be by using any one in PEVCD technology, APCVD technology or LPCVD technology
Deposit such as SiNxOr SiOxEtc inorganic insulation layer be made.The position of first insulating layer 130 is as shown in Figure 5.First
Insulating layer 130 serves as the gate insulation layer of TFT, such as Fig. 6 between the column active layer 120 and the first conductive layer 140 of TFT
It is shown.
S300, the first conductive layer around cladding is formed in the outside of the first insulating layer.
First conductive layer 140 can by various deposition methods from Ag, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li,
At least one of Ca, Mo, Ti, MoW and Al/Cu conductive material are made.First conductive layer 140 serves as the grid of TFT, and
Serve as the first electrode of capacitor.
S400, the first capacitor dielectric layer around cladding is formed in the outside of the first conductive layer.
The position of first capacitor dielectric layer 150 is as shown in Figure 7.First capacitor dielectric layer 150 can also pass through PEVCD skill
Any one deposition such as SiN in art, APCVD technology or LPCVD technologyxOr SiOxEtc inorganic insulation layer production and
At.In addition, first capacitor dielectric layer 150 also may include such as SiON, Al2O3、TiO2、Ta2O5、HFO2、ZrO2, barium strontium titanate
(BST) and the inorganic insulation layer of lead zirconate titanate (PZT) etc.Moreover, first capacitor dielectric layer 150 can be by mixed deposit system
At wherein such as phenol polymer derivant (phenol based polymer derivative), acrylic polymer
The organic insulator and nothing of (acryl based polymer) and acylamide polymer (amide based polymer) etc
Machine insulating layer alternating deposit.First capacitor dielectric layer 150 can not only play insulation effect, moreover it is possible to reach and keep out aqueous vapor and machinery
The scratch of property.
S500, the second conductive layer around cladding is formed in the outside of first capacitor dielectric layer.
The position of second conductive layer 160 is as shown in Figure 8.Identical as the first conductive layer 140, the second conductive layer 160 can also
To pass through various deposition methods from Ag, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, MoW and Al/Cu
At least one conductive material is made.Second conductive layer 160 serves as the second electrode of capacitor.
S600, the second capacitor dielectric layer around cladding is formed in the outside of the second conductive layer.
The position of second capacitor dielectric layer 170 is as shown in Figure 9.Identical as first capacitor dielectric layer 150, the second capacitor is situated between
Matter layer 170 can also pass through any one deposition such as SiN in PEVCD technology, APCVD technology or LPCVD technologyxOr
SiOxEtc inorganic insulation layer be made.In addition, the second capacitor dielectric layer 170 also may include such as SiON, Al2O3、
TiO2、Ta2O5、HFO2、ZrO2, barium strontium titanate (BST) and lead zirconate titanate (PZT) etc inorganic insulation layer.Moreover, the second capacitor
Dielectric layer 170 can be by mixed deposit system at wherein such as phenol polymer derivant (phenol based polymer
Derivative), acrylic polymer (acryl based polymer) and acylamide polymer (amide based
) etc polymer organic insulator and inorganic insulation layer alternating deposit.Second capacitor dielectric layer 170 can not only play absolutely
Edge effect, moreover it is possible to reach and keep out aqueous vapor and mechanical scratch.
S700, it is situated between in the first insulating layer, the first conductive layer, first capacitor dielectric layer, the second conductive layer and the second capacitor
The top of matter layer forms second insulating layer.
The position of second insulating layer 180 is as shown in Figure 10.Identical as the first insulating layer 130, second insulating layer 180 can lead to
It crosses using any one deposition such as SiN in PEVCD technology, APCVD technology or LPCVD technologyxOr SiOxEtc it is inorganic
Insulating layer is made.In addition, second insulating layer 180 can also be the organic insulator of PLA etc.
The preparation method of the pixel electrode of one embodiment further include in second insulating layer 180 with column active layer 120
Opposite position forms the step of contact hole 200 for exposing column active layer 120.Contact hole 200 can be carved by exposure
The method of erosion is prepared.
S800, pixel electrode, pixel electrode and source electrode or drain electrode connection are formed on the top of column active layer.
Pixel electrode 190 is connect by contact hole 200 with drain electrode 123 in present embodiment, and certainly, pixel electrode 190 can
Selectively connected with source electrode or drain electrode.
The material of pixel electrode 190 is metal or metal alloy, for example, can close selected from zinc, Zinc-tin alloy, indium tin
At least one of gold, indium kirsite, indium gallium kirsite and indium Zinc-tin alloy.Pixel electrode 190 can also pass through various depositions
Method and exposure etching are made.
Compared with traditional dot structure to tile from level to level, the system proposed by the present invention by above-mentioned dot structure
The dot structure that Preparation Method is prepared is circular cylindrical, forms solid type ring-type coated TFT, reduces shared by TFT unit
Area, to improve the PPI of display panel.
1 and Figure 12 referring to Figure 1, the dot structure of an embodiment, including substrate 100, buffer layer 110, column are active
The 120, first insulating layer 130 of layer, the first conductive layer 140, first capacitor dielectric layer 150, the second conductive layer 160, the second capacitor are situated between
Matter layer 170, second insulating layer 180 and pixel electrode 190.
Wherein, buffer layer 110 is arranged on the substrate 100.Buffer layer 110 is to promote the levelness of substrate and prevent impurity
Intrusion.The buffer layer 110 of present embodiment includes silicon nitride layer 111 and the silicon oxide layer stacked gradually on the substrate 100
112.Certainly, buffer layer 110 can also be not provided with according to use demand.
Column active layer 120 is arranged on buffer layer 110.Column active layer 120 includes source electrode 121, drain electrode 123 and position
In channel 122 between the two, source electrode 121, channel 122 and drain electrode 123 are stacked.
First insulating layer 130 is around the outside for coating column active layer 120 and covers buffer layer 110.
First conductive layer 140 is around the outside for being coated on the first insulating layer 130.
First capacitor dielectric layer 150 is around the outside for being coated on the first conductive layer 140.
Second conductive layer 160 is around the outside for being coated on first capacitor dielectric layer 150.
Second capacitor dielectric layer 170 is around the outside for being coated on the second conductive layer 160.
First insulating layer 130 of the covering of second insulating layer 180, the first conductive layer 140, first capacitor dielectric layer 150, second are led
The top of electric layer 160 and the second capacitor dielectric layer 170.
Pixel electrode 190 is arranged on column active layer 120, connect with drain electrode 123.Certainly, pixel electrode 190 may be selected
Ground is connect with source electrode 121 or drain electrode 123.Pixel electrode 190 is selected from zinc, Zinc-tin alloy, indium stannum alloy, indium kirsite, indium gallium
At least one of kirsite and indium Zinc-tin alloy.
In addition, being provided with the contact hole 200 for exposing column active layer 120 in second insulating layer 180.Contact hole 200
It is oppositely arranged with column active layer 120, pixel electrode 190 is connect by contact hole 200 with source electrode 121 or drain electrode 123.
Compared with traditional dot structure to tile from level to level, above-mentioned dot structure proposed by the present invention is circular column
Shape forms solid type ring-type coated TFT, area shared by TFT unit is reduced, to improve the PPI of display panel.
In addition, the present invention also provides a kind of display panel, including above-mentioned dot structure.Since above-mentioned dot structure is ring
Shape column forms solid type ring-type coated TFT, area shared by TFT unit is reduced, to improve display panel
PPI。
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of dot structure characterized by comprising
Substrate；
Column active layer, setting on the substrate, the column active layer include source electrode, drain electrode and be located at the source electrode and
Channel between the drain electrode, the source electrode, the channel and the drain electrode are stacked；
First insulating layer around the outside for coating the column active layer and covers the substrate；
First conductive layer, around the outside for being coated on first insulating layer；
First capacitor dielectric layer, around the outside for being coated on first conductive layer；
Second conductive layer, around the outside for being coated on the first capacitor dielectric layer；
Second capacitor dielectric layer, around the outside for being coated on second conductive layer；
Second insulating layer covers first insulating layer, first conductive layer, the first capacitor dielectric layer, described second
The top of conductive layer and the second capacitor dielectric layer；
And pixel electrode, it is arranged on the column active layer, is connected with the source electrode or the drain electrode.
2. dot structure according to claim 1, which is characterized in that be provided in the second insulating layer for exposing
The contact hole of column active layer is stated, the contact hole is oppositely arranged with the column active layer, and the pixel electrode passes through described
Contact hole and the source electrode or the drain electrode connect.
3. dot structure according to claim 1, which is characterized in that the dot structure further includes being arranged in the substrate
On buffer layer.
4. dot structure according to claim 3, which is characterized in that the buffer layer includes being sequentially laminated on the substrate
On silicon nitride layer and silicon oxide layer.
5. dot structure according to claim 1, which is characterized in that the pixel electrode is selected from zinc, Zinc-tin alloy, indium tin
At least one of alloy, indium kirsite, indium gallium kirsite and indium Zinc-tin alloy.
6. a kind of preparation method of dot structure, which comprises the following steps:
Form column active layer on substrate, the column active layer includes source electrode, drain electrode and is located at the source electrode and described
Channel between drain electrode, the source electrode, the channel and the drain electrode are stacked；
The first insulating layer is formed on the outside of the column active layer and the substrate；
The first conductive layer around cladding is formed in the outside of first insulating layer；
The first capacitor dielectric layer around cladding is formed in the outside of first conductive layer；
The second conductive layer around cladding is formed in the outside of the first capacitor dielectric layer；
The second capacitor dielectric layer around cladding is formed in the outside of second conductive layer；
In first insulating layer, first conductive layer, the first capacitor dielectric layer, second conductive layer and described
The top of second capacitor dielectric layer forms second insulating layer；
Pixel electrode, the pixel electrode and the source electrode are formed on the top of the column active layer or the drain electrode connects
It connects.
7. the preparation method of dot structure according to claim 6, which is characterized in that form column active layer on substrate
The step of are as follows:
The first amorphous silicon layer is deposited on the substrate；
The first polysilicon layer is generated by the first amorphous silicon layer described in crystallization；
The first polysilicon layer adulterated after first polysilicon layer by ion implanting formation is patterned, to form source electrode；
The second amorphous silicon layer is formed on the source electrode；
The second polysilicon layer is generated by the second amorphous silicon layer described in crystallization；
The second polysilicon layer adulterated after second polysilicon layer by ion implanting formation is patterned, to form channel；
Third amorphous silicon layer is formed on the channel；
Third polysilicon layer is generated by third amorphous silicon layer described in crystallization；
The third polysilicon layer adulterated after the third polysilicon layer by ion implanting formation is patterned, to form drain electrode.
8. the preparation method of dot structure according to claim 6, which is characterized in that further include in the second insulating layer
The step of upper position opposite with the column active layer forms the contact hole for exposing the column active layer, the pixel
Electrode is connected by the contact hole and the source electrode or the drain electrode.
9. the preparation method of dot structure according to claim 6, which is characterized in that form column active layer on substrate
The step of before, further include the steps that on the substrate formed buffer layer.
10. a kind of display panel, which is characterized in that including dot structure such as according to any one of claims 1 to 5.
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| JP6347704B2 (en) * | 2013-09-18 | 2018-06-27 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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| JP2005167164A (en) * | 2003-12-05 | 2005-06-23 | Mitsui Chemicals Inc | Transistor and formation method therefor |
| CN102082178A (en) * | 2009-11-30 | 2011-06-01 | 华映视讯（吴江）有限公司 | Vertical thin film transistor (TFT) and manufacturing method thereof as well as display device and manufacturing method thereof |
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