CN106298797B - The production method and the array substrate as made from this method of array substrate - Google Patents
The production method and the array substrate as made from this method of array substrate Download PDFInfo
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- CN106298797B CN106298797B CN201510261908.2A CN201510261908A CN106298797B CN 106298797 B CN106298797 B CN 106298797B CN 201510261908 A CN201510261908 A CN 201510261908A CN 106298797 B CN106298797 B CN 106298797B
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- array substrate
- insulating cover
- layer
- grid
- channel layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
Abstract
A kind of production method of array substrate, this method comprises: providing thin film transistor (TFT), which includes channel layer；Form the insulating cover for covering the thin film transistor (TFT)；And the channel layer is covered by insulating cover described in ultraviolet light and with a shelter, the insulating cover does not become transparent from translucent under the irradiation of the ultraviolet light by the part that the shelter covers.The present invention also provides a kind of array substrates as made from this method.The production method of array substrate provided by the present invention and the array substrate as made from this method due to when bleaching insulating cover channel layer be blocked by obstructions, which will not be destroyed, so as to obtain more stable array substrate.
Description
Technical field
The present invention relates to a kind of production method of array substrate and a kind of array substrates as made from this method.
Background technique
Liquid crystal display panel generally includes array substrate, opposite substrate and is folded in the array substrate and opposite substrate
Between liquid crystal layer.Wherein, which would generally be covered with an insulating cover close to the side of liquid crystal layer, e.g. flat
Smoothization layer etc..For the light transmittance for improving the insulating cover, it will usually the insulating cover described in Ultraviolet photobleaching.However,
The irradiation of ultraviolet light is easily destroyed the channel layer in array substrate.
Summary of the invention
In consideration of it, it is necessary to provide a kind of production methods of array substrate, this method comprises:
Thin film transistor (TFT) is provided, which includes channel layer；
Form the insulating cover for covering the thin film transistor (TFT)；And
The channel layer, the insulating cover are covered by insulating cover described in ultraviolet light and with a shelter
Do not become transparent from translucent under the irradiation of the ultraviolet light by the part that the shelter covers.
It there is a need to provide a kind of array substrate as made from the above method.
A kind of array substrate, the array substrate include substrate, form thin film transistor (TFT) on the substrate and covering
The insulating cover of the thin film transistor (TFT), the thin film transistor (TFT) include channel layer, and the insulating cover corresponds to described logical
The position of channel layer be it is translucent, it is transparent that the insulating cover, which corresponds to the position other than the channel layer,.
It compares with the prior art, the production method of array substrate provided by the present invention and as made from this method
Array substrate due to when bleaching insulating cover channel layer be blocked by obstructions, which will not be destroyed, so as to
Obtain more stable array substrate.
Detailed description of the invention
Fig. 1 is the display panel of the specific embodiment of the invention.
Fig. 2 is the array substrate of the specific embodiment of the invention.
Fig. 3 is the cross-sectional view that III-III cutting line is done along Fig. 2.
Fig. 4 is the flow chart of the first embodiment of array substrate manufacturing method of the present invention.
Fig. 5 to Fig. 9 is the substep schematic diagram of each step in Fig. 4.
Figure 10 is the flow chart of the second embodiment of array substrate manufacturing method of the present invention.
Figure 11-12 is the substep schematic diagram of each step in Figure 10.
Main element symbol description
| Display panel | 1 |
| Array substrate | 10 |
| Opposite substrate | 11 |
| Liquid crystal layer | 12 |
| Substrate | 101 |
| Grid | 102 |
| Gate insulating layer | 103 |
| Channel layer | 104 |
| Source electrode | 105 |
| Drain electrode | 106 |
| Data insulating layer | 107 |
| Insulating cover | 108 |
| Grid line | 151 |
| Data line | 152 |
| Pixel electrode | 153 |
| Through-hole | 161 |
| First area | 108a |
| Second area | 108b |
| Exposure mask | 300 |
The present invention that the following detailed description will be further explained with reference to the above drawings.
Specific embodiment
Referring to Fig. 1, display panel 1 provided by the specific embodiment of the invention includes array substrate 10, opposite substrate
11 and liquid crystal layer 12.The liquid crystal layer 12 is located between the array substrate 10 and opposite substrate 11.In present embodiment
In, the array substrate 10 is thin film transistor base plate, and the opposite substrate 11 is colored filter substrate.
Referring to Figure 2 together with Fig. 3, array substrate 10 provided by the specific embodiment of the invention includes substrate 101, grid
Pole 102, gate insulating layer 103, channel layer 104, source electrode 105, drain electrode 106, data insulating layer 107, insulating cover 108, grid
Polar curve 151, data line 152 and pixel electrode 153.Wherein, the grid 102, gate insulating layer 103, channel layer 104, source
Pole 105 and drain electrode 106 collectively form a thin film transistor (TFT).
Specifically, the grid 102 is formed on the substrate 101 with grid line 151.The gate insulating layer 103 covers
Cover the grid 102 and grid line 151.The setting of channel layer 104 is on the gate insulating layer 103 and described in the face of position
Grid 102.The source electrode 105, drain electrode 106 and data line 152 are formed on the gate insulating layer 103, and the source electrode
105 are covered each by the both ends of the channel layer 104 with drain electrode 106.The data insulating layer 107 covers the gate insulating layer
103, channel layer 104, source electrode 105, drain electrode 106 and data line 152.The pixel electrode 153 is formed in the data insulation
On layer 107, and the through-hole 161 being provided on the data insulating layer 107 by one and the drain electrode 106 are electrically connected.It is described
Insulating cover 108 is formed on the data insulating layer 107 and covers the pixel electrode 153.In the present embodiment, institute
Stating insulating cover 108 is a planarization layer, and surface of the insulating cover 108 far from the data insulating layer 107 is in one
Flat surface.
The insulating cover 108 includes the first area 108a for corresponding to the channel layer 104 and the corresponding channel
The second area 108b of position other than layer 104.The first area 108a be it is translucent, certain Huang is presented sometimes
Color.The second area 108b is transparent.The second area 108b is to be become under the irradiation of ultraviolet light from translucent
Bright.
In the present embodiment, the material of the substrate 101 is selected from transparent substrate, such as glass, quartz or organic polymer
Object etc..The grid 102, grid line 151, source electrode 105, drain electrode 106 and data line 152 material be selected from metal, such as aluminium,
Titanium, molybdenum, tantalum, copper etc..The material in the channel 104 is selected from semiconductor, such as metal oxide, amorphous silicon or polysilicon etc..Institute
The material for stating gate insulating layer 103 and data insulating layer 107 is selected from transparent insulation material, such as silica, silicon nitride, oxidation
Aluminium and silicon oxynitride etc..The material of the pixel electrode 153 is selected from transparent conductive material, such as tin indium oxide (ITO).It is described exhausted
Edge coating 108 is selected from the organic material for capableing of bleach under the irradiation of ultraviolet light, for example, by using the PC of Japanese JSR company
(polycarbonate) series, the flat layer material of Fuji Photo Film Co., Ltd. and benzo cyclic ethylene (BCB) etc..
It will be described below by production method of two specific embodiments to array substrate 10 of the present invention.This hair
The production method of array substrate 10 provided by bright specific embodiment is mainly by ultraviolet light insulating cover 108
When using a shelter cover the channel layer 104, to avoid the channel layer 104 by ultraviolet photo damage.
Referring to Fig. 4, the flow chart of the first embodiment for 10 production method of array substrate of the present invention.It should illustrate
It is that 10 production method of array substrate of the present invention is not limited to the sequence of following step, and in other embodiments, the present invention
10 production method of array substrate can only include a portion of step as described below or part steps therein can be by
It deletes.The first embodiment of 10 production method of array substrate of the present invention is carried out below with reference to the explanation of each process step of Fig. 4
It is discussed in detail.
Step S201 referring to Fig. 5, providing substrate 101, and forms grid 102 on the substrate 101.
Specifically, substrate 101 is provided first, forms a metal layer on the substrate 101, and pass through yellow light process pattern
Change the metal layer to form the grid 102.
It is appreciated that the grid line 151 is formed in same yellow light process with the grid 102.
In the present embodiment, the material of the substrate 101 is selected from transparent substrate, such as glass, quartz or organic polymer
Object etc..The metal is, for example, aluminium, titanium, molybdenum, tantalum, copper etc..
Step S202, referring to Fig. 6, the gate insulating layer 103 for covering the grid 102 is formed on the substrate 101,
Semi-conductor layer is formed on the gate insulating layer 103, and institute is patterned by yellow light process under the masking of an exposure mask 300
Semiconductor layer is stated to form channel layer 104.
In the present embodiment, the material of the gate insulating layer 103 is selected from transparent insulation material, such as silica, nitrogen
SiClx, aluminium oxide and silicon oxynitride etc..The semiconductor layer is, for example, metal oxide, amorphous silicon or polysilicon etc..
Step S203, referring to Fig. 7, forming source electrode 105 and drain electrode 106, the source electrode on the gate insulating layer 103
105 are covered each by the both ends of the channel layer 104 with drain electrode 106.
Specifically, a metal layer is formed on the gate insulating layer 103 first, and by described in yellow light process patterning
Metal layer is to form the source electrode 105 and drain electrode 106.
It is appreciated that the data line 152 is formed in same step with the source electrode 105 and drain electrode 106.
In the present embodiment, the metal is, for example, aluminium, titanium, molybdenum, tantalum, copper etc..
Step S204 covers the gate insulating layer 103, channel layer 104, source electrode 105 and leakage referring to Fig. 8, being formed
The data insulating layer 107 of pole 106, and insulating cover 108 is formed on the data insulating layer 107.
In the present embodiment, the material of the data insulating layer 107 is selected from transparent insulation material, such as silica, nitrogen
SiClx, aluminium oxide and silicon oxynitride etc..The insulating cover 108, which is selected from, bleach to be had under the irradiation of ultraviolet light
Machine material, for example, by using Japanese JSR company PC (polycarbonate) series, Fuji Photo Film Co., Ltd. flat layer material and
Benzo cyclic ethylene (BCB) etc..
Step S205, referring to Fig. 9, being covered by insulating cover 108 described in ultraviolet light and with the exposure mask 300
The channel layer 104, photograph of the part 108b that the insulating cover 108 is not covered by the exposure mask 300 in the ultraviolet light
Penetrating down from translucent becomes transparent.
As a result, in the present embodiment, it is insulated by the exposure mask 300 when forming channel layer 104 as ultraviolet light
The shelter used when coating 108 can be avoided channel layer 108 by ultraviolet photo damage, to obtain more stable array
Substrate 10.
Referring to Fig. 10, the flow chart of the second embodiment for 10 production method of array substrate of the present invention.It should illustrate
, 10 production method of array substrate of the present invention is not limited to the sequence of following step, and in other embodiments, this hair
Bright 10 production method of array substrate can only include a portion of step as described below or part steps therein can be with
It is deleted.Below with reference to each process step of Figure 10 explanation to the second embodiment of 10 production method of array substrate of the present invention into
Row is discussed in detail.
Step S301, please refers to Figure 11, and providing array substrate semi-finished product includes that grid 102, channel layer 104 and insulation are covered
Cap rock 108, the channel layer 104 is between the grid 102 and the insulating cover 108.
Specifically, the array substrate semi-finished product further include substrate 101, gate insulating layer 103, source electrode 105, drain electrode 106
And data insulating layer 107.Wherein, the grid 102 is formed on the substrate 101.The gate insulating layer 103 is formed in
On the substrate 101 and cover the grid 102.The channel layer 104 be formed on the gate insulating layer 103 and position just
To the grid 102.The source electrode 105 is formed on the gate insulating layer 103 with drain electrode 106 and is covered each by the channel
104 both ends of layer.The data insulating layer 107 covers the gate insulating layer 103, channel layer 104, source electrode 105 and drain electrode
106.The insulating cover 108 covers the data insulating layer 107.
In the present embodiment, the material of the substrate 101 is selected from transparent substrate, such as glass, quartz or organic polymer
Object etc..The material of the grid 102, source electrode 105 and drain electrode 106 is selected from metal, such as aluminium, titanium, molybdenum, tantalum, copper etc..It is described logical
The material in road 104 is selected from semiconductor, such as metal oxide, amorphous silicon or polysilicon etc..The gate insulating layer 103 and number
Transparent insulation material, such as silica, silicon nitride, aluminium oxide and silicon oxynitride etc. are selected from according to the material of insulating layer 107.It is described
Insulating cover 108 is selected from the organic material for capableing of bleach under the irradiation of ultraviolet light, for example, by using the PC of Japanese JSR company
(polycarbonate) series, the flat layer material of Fuji Photo Film Co., Ltd. and benzo cyclic ethylene (BCB) etc..
Step S302, please refers to Figure 12, by ultraviolet light from the grid 103 far from the insulating cover 108 one
The insulating cover 108 is irradiated in side, the part that the insulating cover 108 is not covered by the grid 103 is described ultraviolet
Become transparent from translucent under the irradiation of light.
As a result, in the present embodiment, the screening used when by grid 103 as ultraviolet light insulating cover 108
Block material can be avoided channel layer 108 by ultraviolet photo damage, to obtain more stable array substrate 10.Compared to production side
The first embodiment of method, present embodiment is since without reusing the exposure mask 300, processing procedure is simpler.
The above examples are only used to illustrate the technical scheme of the present invention and are not limiting, upper and lower, the left and right occurred in diagram
Direction understands only for facilitating, although being described the invention in detail referring to preferred embodiment, the ordinary skill of this field
Personnel should be appreciated that and can modify to technical solution of the present invention or equivalent replacement, without departing from technical solution of the present invention
Spirit and scope.
Claims (10)
1. a kind of production method of array substrate, this method comprises:
Thin film transistor (TFT) is provided, which includes channel layer；
Form the insulating cover for covering the thin film transistor (TFT)；And
Cover the channel layer by insulating cover described in ultraviolet light and with a shelter, the insulating cover not by
The part of the shelter masking becomes transparent from translucent under the irradiation of the ultraviolet light；
The thin film transistor (TFT) further includes grid, and the channel layer is described between the grid and the insulating cover
Ultraviolet light irradiates the insulating cover far from the side of the insulating cover from the grid, and the grid is as the screening
Block material.
2. the production method of array substrate as described in claim 1, which is characterized in that the material of the grid is metal.
3. the production method of array substrate as described in claim 1, which is characterized in that the forming method of the channel layer includes:
Semi-conductor layer is formed, and the semiconductor layer is patterned to form channel by yellow light process under the masking of an exposure mask
Layer.
4. the production method of array substrate as described in claim 1, which is characterized in that insulation described in the ultraviolet light is covered
The part that cap rock is not covered by the shelter, the part that the insulating cover is not covered by the shelter is described ultraviolet
It by translucent be bleached is transparent under the irradiation of light.
5. the production method of array substrate as described in claim 1, which is characterized in that the insulating cover is far from described thin
The surface of film transistor is in a flat surface.
6. a kind of array substrate, which includes substrate, forms thin film transistor (TFT) on the substrate and cover institute
The insulating cover of thin film transistor (TFT) is stated, surface of the insulating cover far from the thin film transistor (TFT) is in a flat table
Face, the thin film transistor (TFT) include to form grid on the substrate and be located at the grid and the insulating cover it
Between channel layer, the grid as ultraviolet light from the grid far from the insulating cover side irradiation it is described insulation cover
Shelter when cap rock, so that the position that the insulating cover corresponds to the channel layer is translucent, the insulation covering
Position other than the corresponding channel layer of layer is transparent.
7. array substrate as claimed in claim 6, which is characterized in that the insulating cover is selected from organic material.
8. array substrate as claimed in claim 6, which is characterized in that the thin film transistor (TFT) further includes gate insulating layer, source
Pole and drain electrode, the gate insulating layer form on the substrate and cover the grid, and the channel layer is formed in the grid
On the insulating layer of pole and grid described in the face of position, the source electrode and drain electrode form on the gate insulating layer and are covered each by institute
State channel layer opposite sides.
9. array substrate as claimed in claim 6, which is characterized in that the insulating cover corresponds to other than the channel layer
Position is to become transparent from translucent under the irradiation of ultraviolet light.
10. array substrate as claimed in claim 6, which is characterized in that the array substrate further includes data insulating layer, described
Data insulating layer is formed on the gate insulating layer, covers the gate insulating layer, source electrode, drain electrode and channel layer, and by institute
Insulating cover is stated to be covered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510261908.2A CN106298797B (en) | 2015-05-21 | 2015-05-21 | The production method and the array substrate as made from this method of array substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510261908.2A CN106298797B (en) | 2015-05-21 | 2015-05-21 | The production method and the array substrate as made from this method of array substrate |
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| Publication Number | Publication Date |
|---|---|
| CN106298797A CN106298797A (en) | 2017-01-04 |
| CN106298797B true CN106298797B (en) | 2019-06-18 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737294B1 (en) * | 2003-04-04 | 2004-05-18 | Au Optronics Corp. | Method of reducing surface leakage currents of a thin-film transistor substrate |
| CN1781057A (en) * | 2003-04-30 | 2006-05-31 | 韩商.Adms技术股份有限公司 | Negative resist composition for organic insulator of high aperture LCD |
| CN101964309A (en) * | 2010-09-01 | 2011-02-02 | 友达光电股份有限公司 | Manufacturing method of thin film transistor |
-
2015
- 2015-05-21 CN CN201510261908.2A patent/CN106298797B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737294B1 (en) * | 2003-04-04 | 2004-05-18 | Au Optronics Corp. | Method of reducing surface leakage currents of a thin-film transistor substrate |
| CN1781057A (en) * | 2003-04-30 | 2006-05-31 | 韩商.Adms技术股份有限公司 | Negative resist composition for organic insulator of high aperture LCD |
| CN101964309A (en) * | 2010-09-01 | 2011-02-02 | 友达光电股份有限公司 | Manufacturing method of thin film transistor |
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| CN106298797A (en) | 2017-01-04 |
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