CN106298797A - The manufacture method of array base palte and the array base palte prepared by the method - Google Patents
The manufacture method of array base palte and the array base palte prepared by the method Download PDFInfo
- Publication number
- CN106298797A CN106298797A CN201510261908.2A CN201510261908A CN106298797A CN 106298797 A CN106298797 A CN 106298797A CN 201510261908 A CN201510261908 A CN 201510261908A CN 106298797 A CN106298797 A CN 106298797A
- Authority
- CN
- China
- Prior art keywords
- array base
- base palte
- insulating cover
- channel layer
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000010409 thin film Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 29
- 239000012212 insulator Substances 0.000 claims description 26
- 230000004888 barrier function Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000001678 irradiating effect Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000011368 organic material Substances 0.000 claims description 4
- 238000004061 bleaching Methods 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000012774 insulation material Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 3
- 239000005977 Ethylene Substances 0.000 description 3
- 235000010724 Wisteria floribunda Nutrition 0.000 description 3
- 125000005605 benzo group Chemical group 0.000 description 3
- 239000007844 bleaching agent Substances 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229920000620 organic polymer Polymers 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The manufacture method of a kind of array base palte, the method includes: providing thin film transistor (TFT), this thin film transistor (TFT) includes channel layer；Form the insulating cover covering described thin film transistor (TFT)；And irradiate described insulating cover by ultraviolet light and cover described channel layer with a shelter, the part that described insulating cover is not covered by described shelter is become transparent from translucent under the irradiation of described ultraviolet light.The present invention also provides for a kind of array base palte prepared by the method.The manufacture method of array base palte provided by the present invention and the array base palte that prepared by the method due to when bleaching insulating cover channel layer be blocked by obstructions, this channel layer will not be destroyed such that it is able to obtains more stable array base palte.
Description
Technical field
The present invention relates to the manufacture method of a kind of array base palte and a kind of array base palte prepared by the method.
Background technology
Display panels generally includes array base palte, opposite substrate and is folded in the liquid crystal layer between described array base palte and opposite substrate.Wherein, this array base palte would generally be coated with an insulating cover, e.g. planarization layer etc. near the side of liquid crystal layer.For improving the light transmittance of described insulating cover, it will usually with insulating cover described in Ultraviolet photobleaching.But, the irradiation of ultraviolet light is easily destroyed the channel layer in array base palte.
Summary of the invention
In consideration of it, be necessary to provide the manufacture method of a kind of array base palte, the method includes:
Thering is provided thin film transistor (TFT), this thin film transistor (TFT) includes channel layer；
Form the insulating cover covering described thin film transistor (TFT)；And
Irradiating described insulating cover by ultraviolet light and cover described channel layer with a shelter, the part that described insulating cover is not covered by described shelter is become transparent from translucent under the irradiation of described ultraviolet light.
There is a need to provide a kind of array base palte prepared by said method.
A kind of array base palte, this array base palte includes substrate, forms thin film transistor (TFT) on the substrate and cover the insulating cover of described thin film transistor (TFT), described thin film transistor (TFT) includes channel layer, the position of the corresponding described channel layer of described insulating cover is translucent, and the position beyond the corresponding described channel layer of described insulating cover is transparent.
Compare with prior art, the manufacture method of array base palte provided by the present invention and the array base palte that prepared by the method due to when bleaching insulating cover channel layer be blocked by obstructions, this channel layer will not be destroyed such that it is able to obtains more stable array base palte.
Accompanying drawing explanation
Fig. 1 is the display floater of the specific embodiment of the invention.
Fig. 2 is the array base palte of the specific embodiment of the invention.
Fig. 3 is the sectional view that III-III line of cut is done along Fig. 2.
Fig. 4 is the flow chart of the first embodiment of array substrate manufacturing method of the present invention.
Fig. 5 to Fig. 9 is the substep schematic diagram of each step in Fig. 4.
Figure 10 is the flow chart of the second embodiment of array substrate manufacturing method of the present invention.
Figure 11-12 is the substep schematic diagram of each step in Figure 10.
Main element symbol description
| Display floater | 1 |
| Array base palte | 10 |
| Opposite substrate | 11 |
| Liquid crystal layer | 12 |
| Substrate | 101 |
| Grid | 102 |
| Gate insulator | 103 |
| Channel layer | 104 |
| Source electrode | 105 |
| Drain electrode | 106 |
| Data insulating barrier | 107 |
| Insulating cover | 108 |
| Gate line | 151 |
| Data wire | 152 |
| Pixel electrode | 153 |
| Through hole | 161 |
| First area | 108a |
| Second area | 108b |
| Mask | 300 |
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
Referring to Fig. 1, the display floater 1 that the specific embodiment of the invention is provided includes array base palte 10, opposite substrate 11 and liquid crystal layer 12.Described liquid crystal layer 12 is located between described array base palte 10 and opposite substrate 11.In the present embodiment, described array base palte 10 is thin film transistor base plate, and described opposite substrate 11 is colored filter substrate.
Seeing also Fig. 2 and Fig. 3, the array base palte 10 that the specific embodiment of the invention is provided includes substrate 101, grid 102, gate insulator 103, channel layer 104, source electrode 105, drain electrode 106, data insulating barrier 107, insulating cover 108, gate line 151, data wire 152 and pixel electrode 153.Wherein, described grid 102, gate insulator 103, channel layer 104, source electrode 105 collectively form a thin film transistor (TFT) with drain electrode 106.
Specifically, described grid 102 is formed on described substrate 101 with gate line 151.Described gate insulator 103 covers described grid 102 and gate line 151.Described channel layer 104 is arranged on described gate insulator 103 and position is just to described grid 102.Described source electrode 105, drain electrode 106 and data wire 152 are formed on described gate insulator 103, and described source electrode 105 is covered each by the two ends of described channel layer 104 with drain electrode 106.Described data insulating barrier 107 covers described gate insulator 103, channel layer 104, source electrode 105, drain electrode 106 and data wire 152.Described pixel electrode 153 is formed on described data insulating barrier 107, and is electrically connected with described drain electrode 106 by a through hole 161 being opened on described data insulating barrier 107.Described insulating cover 108 is formed on described data insulating barrier 107 and covers described pixel electrode 153.In the present embodiment, described insulating cover 108 is a planarization layer, and described insulating cover 108 is a smooth surface away from the surface of described data insulating barrier 107.
Described insulating cover 108 includes the second area 108b of the position beyond the first area 108a of corresponding described channel layer 104 and corresponding described channel layer 104.Described first area 108a is translucent, presents certain yellow sometimes.Described second area 108b is transparent.Described second area 108b is to be become transparent from translucent under the irradiation of ultraviolet light.
In the present embodiment, the material of described substrate 101 is selected from transparent base, such as glass, quartz or organic polymer etc..The material of described grid 102, gate line 151, source electrode 105, drain electrode 106 and data wire 152 is selected from metal, such as aluminum, titanium, molybdenum, tantalum, copper etc..The material of described passage 104 is selected from quasiconductor, such as metal-oxide, non-crystalline silicon or polysilicon etc..The material of described gate insulator 103 and data insulating barrier 107 is selected from transparent insulation material, such as silicon oxide, silicon nitride, aluminium oxide and silicon oxynitride etc..The material of described pixel electrode 153 is selected from transparent conductive material, such as tin indium oxide (ITO).Described insulating cover 108 selected from can under the irradiation of ultraviolet light the organic material of bleach, for example with PC (Merlon) series, the flatness layer material of Fuji Photo Film Co., Ltd. and the benzo ring ethylene (BCB) etc. of JSR company of Japan.
By two detailed description of the invention, the manufacture method of array base palte 10 of the present invention will be described below.The manufacture method of the array base palte 10 that the specific embodiment of the invention is provided is mainly by using a shelter to cover described channel layer 104 when ultraviolet light irradiates insulating cover 108, thus avoids described channel layer 104 to be destroyed by ultraviolet light.
Refer to Fig. 4, for the flow chart of the first embodiment of array base palte 10 manufacture method of the present invention.Be it should be noted that, array base palte 10 manufacture method of the present invention is not limited to the order of following step, and in other embodiments, array base palte 10 manufacture method of the present invention can only include a portion of the following stated step, or part steps therein can be deleted.First embodiment of array base palte 10 manufacture method of the present invention is described in detail by the explanation below in conjunction with each process step of Fig. 4.
Step S201, refers to Fig. 5, it is provided that substrate 101, and forms grid 102 on described substrate 101.
Specifically, first provide substrate 101, described substrate 101 is formed a metal level, and patterns described metal level to form described grid 102 by gold-tinted processing procedure.
It is appreciated that described gate line 151 is formed in same gold-tinted processing procedure with described grid 102.
In the present embodiment, the material of described substrate 101 is selected from transparent base, such as glass, quartz or organic polymer etc..Described metal e.g. aluminum, titanium, molybdenum, tantalum, copper etc..
Step S202, refer to Fig. 6, described substrate 101 is formed the gate insulator 103 covering described grid 102, described gate insulator 103 is formed semi-conductor layer, and patterns described semiconductor layer to form channel layer 104 by gold-tinted processing procedure under the covering of a mask 300.
In the present embodiment, the material of described gate insulator 103 is selected from transparent insulation material, such as silicon oxide, silicon nitride, aluminium oxide and silicon oxynitride etc..Described semiconductor layer e.g. metal-oxide, non-crystalline silicon or polysilicon etc..
Step S203, refers to Fig. 7, forms source electrode 105 and drain electrode 106 on described gate insulator 103, and described source electrode 105 and drain electrode 106 are covered each by the two ends of described channel layer 104.
Specifically, on described gate insulator 103, first form a metal level, and pattern described metal level to form described source electrode 105 and drain electrode 106 by gold-tinted processing procedure.
It is appreciated that described data wire 152 is formed with drain electrode 106 with described source electrode 105 in same step.
In the present embodiment, described metal e.g. aluminum, titanium, molybdenum, tantalum, copper etc..
Step S204, refers to Fig. 8, is formed and covers described gate insulator 103, channel layer 104, source electrode 105 and the data insulating barrier 107 of drain electrode 106, and forms insulating cover 108 on described data insulating barrier 107.
In the present embodiment, the material of described data insulating barrier 107 is selected from transparent insulation material, such as silicon oxide, silicon nitride, aluminium oxide and silicon oxynitride etc..Described insulating cover 108 selected from can under the irradiation of ultraviolet light the organic material of bleach, for example with PC (Merlon) series, the flatness layer material of Fuji Photo Film Co., Ltd. and the benzo ring ethylene (BCB) etc. of JSR company of Japan.
Step S205, refer to Fig. 9, irradiating described insulating cover 108 by ultraviolet light and cover described channel layer 104 with described mask 300, part 108b that described insulating cover 108 is not covered by described mask 300 is become transparent from translucent under the irradiation of described ultraviolet light.
Thus, in the present embodiment, the shelter used when irradiating insulating cover 108 by the mask 300 when forming channel layer 104 as ultraviolet light, it is possible to avoid channel layer 108 to be destroyed by ultraviolet light, thus obtain more stable array base palte 10.
Refer to Figure 10, for the flow chart of the second embodiment of array base palte 10 manufacture method of the present invention.Be it should be noted that, array base palte 10 manufacture method of the present invention is not limited to the order of following step, and in other embodiments, array base palte 10 manufacture method of the present invention can only include a portion of the following stated step, or part steps therein can be deleted.Second embodiment of array base palte 10 manufacture method of the present invention is described in detail by the explanation below in conjunction with each process step of Figure 10.
Step S301, refers to Figure 11, it is provided that array base palte semi-finished product include grid 102, channel layer 104 and insulating cover 108, and described channel layer 104 is between described grid 102 and described insulating cover 108.
Specifically, described array base palte semi-finished product also include substrate 101, gate insulator 103, source electrode 105, drain electrode 106 and data insulating barrier 107.Wherein, described grid 102 is formed on described substrate 101.Described gate insulator 103 is formed on described substrate 101 and covers described grid 102.Described channel layer 104 is formed on described gate insulator 103 and position is just to described grid 102.Described source electrode 105 is formed on described gate insulator 103 and is covered each by described channel layer 104 two ends with drain electrode 106.Described data insulating barrier 107 covers described gate insulator 103, channel layer 104, source electrode 105 and drain electrode 106.Described insulating cover 108 covers described data insulating barrier 107.
In the present embodiment, the material of described substrate 101 is selected from transparent base, such as glass, quartz or organic polymer etc..The material of described grid 102, source electrode 105 and drain electrode 106 is selected from metal, such as aluminum, titanium, molybdenum, tantalum, copper etc..The material of described passage 104 is selected from quasiconductor, such as metal-oxide, non-crystalline silicon or polysilicon etc..The material of described gate insulator 103 and data insulating barrier 107 is selected from transparent insulation material, such as silicon oxide, silicon nitride, aluminium oxide and silicon oxynitride etc..Described insulating cover 108 selected from can under the irradiation of ultraviolet light the organic material of bleach, for example with PC (Merlon) series, the flatness layer material of Fuji Photo Film Co., Ltd. and the benzo ring ethylene (BCB) etc. of JSR company of Japan.
Step S302, refer to Figure 12, by ultraviolet light from described grid 103 away from described insulating cover 108 side irradiate described insulating cover 108, the part that described insulating cover 108 is not covered by described grid 103 is become transparent from translucent under the irradiation of described ultraviolet light.
Thus, in the present embodiment, the shelter used when irradiating insulating cover 108 by grid 103 as ultraviolet light, it is possible to avoid channel layer 108 to be destroyed by ultraviolet light, thus obtain more stable array base palte 10.Compared to the first embodiment of manufacture method, present embodiment is owing to without reusing described mask 300, processing procedure is simpler.
Above example is only in order to illustrate technical scheme and unrestricted, upper and lower, the left and right direction that occur in diagram understand only for convenient, although the present invention being described in detail with reference to preferred embodiment, it will be understood by those within the art that, technical scheme can be modified or equivalent, without deviating from the spirit and scope of technical solution of the present invention.
Claims (12)
1. a manufacture method for array base palte, the method includes:
Thering is provided thin film transistor (TFT), this thin film transistor (TFT) includes channel layer；
Form the insulating cover covering described thin film transistor (TFT)；And
Irradiating described insulating cover by ultraviolet light and cover described channel layer with a shelter, the part that described insulating cover is not covered by described shelter is become transparent from translucent under the irradiation of described ultraviolet light.
2. the manufacture method of array base palte as claimed in claim 1, it is characterized in that, described thin film transistor (TFT) also includes grid, described channel layer is between described grid and described insulating cover, described ultraviolet light from described grid away from described insulating cover side irradiate described insulating cover, described grid is as described shelter.
3. the manufacture method of array base palte as claimed in claim 2, it is characterised in that the material of described grid is metal.
4. the manufacture method of array base palte as claimed in claim 1, it is characterised in that the forming method of this channel layer includes:
Form semi-conductor layer, and pattern described semiconductor layer to form channel layer by gold-tinted processing procedure under the covering of a mask.
5. the manufacture method of array base palte as claimed in claim 4, it is characterised in that described mask is as described shelter.
6. the manufacture method of array base palte as claimed in claim 1, it is characterized in that, described ultraviolet light irradiates the part that described insulating cover is not covered by described shelter, and the part that described insulating cover is not covered by described shelter is bleached as transparent by translucent under the irradiation of described ultraviolet light.
7. the manufacture method of array base palte as claimed in claim 1, it is characterised in that described insulating cover is a smooth surface away from the surface of described thin film transistor (TFT).
8. an array base palte, this array base palte includes substrate, forms thin film transistor (TFT) on the substrate and cover the insulating cover of described thin film transistor (TFT), described insulating cover is a smooth surface away from the surface of described thin film transistor (TFT), described thin film transistor (TFT) includes channel layer, the position of the corresponding described channel layer of described insulating cover is translucent, and the position beyond the corresponding described channel layer of described insulating cover is transparent.
9. array base palte as claimed in claim 8, it is characterised in that described insulating cover is selected from organic material.
10. array base palte as claimed in claim 8, it is characterized in that, described thin film transistor (TFT) also includes grid, gate insulator, source electrode and drain electrode, described grid is formed on the substrate, described gate insulator is formed on the substrate and covers described grid, described channel layer is formed on described gate insulator and position is just to described grid, and described source electrode and drain electrode are formed on described gate insulator and are covered each by described channel layer opposite sides.
11. array base paltes as claimed in claim 8, it is characterised in that the position beyond the corresponding described channel layer of described insulating cover is to be become transparent from translucent under the irradiation of ultraviolet light.
12. array base paltes as claimed in claim 8, it is characterized in that, described array base palte also includes that data insulating barrier, described data insulating barrier are formed on described gate insulator, cover described gate insulator, source electrode, drain electrode and channel layer, and covered by described insulating cover.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510261908.2A CN106298797B (en) | 2015-05-21 | 2015-05-21 | The production method and the array substrate as made from this method of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510261908.2A CN106298797B (en) | 2015-05-21 | 2015-05-21 | The production method and the array substrate as made from this method of array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298797A true CN106298797A (en) | 2017-01-04 |
| CN106298797B CN106298797B (en) | 2019-06-18 |
Family
ID=57633923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510261908.2A Active CN106298797B (en) | 2015-05-21 | 2015-05-21 | The production method and the array substrate as made from this method of array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298797B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737294B1 (en) * | 2003-04-04 | 2004-05-18 | Au Optronics Corp. | Method of reducing surface leakage currents of a thin-film transistor substrate |
| CN1781057A (en) * | 2003-04-30 | 2006-05-31 | 韩商.Adms技术股份有限公司 | Negative resist composition for organic insulator of high aperture LCD |
| CN101964309A (en) * | 2010-09-01 | 2011-02-02 | 友达光电股份有限公司 | Manufacturing method of thin film transistor |
-
2015
- 2015-05-21 CN CN201510261908.2A patent/CN106298797B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737294B1 (en) * | 2003-04-04 | 2004-05-18 | Au Optronics Corp. | Method of reducing surface leakage currents of a thin-film transistor substrate |
| CN1781057A (en) * | 2003-04-30 | 2006-05-31 | 韩商.Adms技术股份有限公司 | Negative resist composition for organic insulator of high aperture LCD |
| CN101964309A (en) * | 2010-09-01 | 2011-02-02 | 友达光电股份有限公司 | Manufacturing method of thin film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106298797B (en) | 2019-06-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9911762B2 (en) | Display device | |
| US11003012B2 (en) | Liquid crystal display device and manufacturing method thereof | |
| US9711542B2 (en) | Method for fabricating display panel | |
| CN103988288B (en) | Semiconductor device | |
| CN104538307B (en) | A kind of method for making polycrystalline SiTFT | |
| CN104377247B (en) | The manufacture method of thin film transistor (TFT), display device and thin film transistor (TFT) | |
| US9685466B2 (en) | Thin film transistor, array substrate and display device | |
| CN105247408B (en) | The groove portion forming method of liquid crystal panel and dielectric film | |
| CN103149760A (en) | Thin film transistor array substrate, manufacturing method and display device | |
| US10054814B2 (en) | Array substrate, manufacturing method thereof, and display apparatus | |
| CN104460147A (en) | Thin film transistor array substrate, manufacturing method and display device | |
| KR20120039947A (en) | Display device and method for manufacturing the same | |
| US9166097B2 (en) | Thin film transistor substrate and manufacturing method thereof, display | |
| TWI577000B (en) | Display device | |
| CN104377208B (en) | Display base plate and its manufacture method and display device | |
| CN105785684A (en) | Thin film transistor substrate and manufacturing method thereof and liquid crystal display panel adopting thin film transistor substrate | |
| CN106292100A (en) | Array base palte and there is the display panels of this array base palte | |
| CN106298797A (en) | The manufacture method of array base palte and the array base palte prepared by the method | |
| KR20110002405A (en) | Method for manufacturing self-aligned thin-film transistor and structure thereof | |
| CN106292171A (en) | The manufacture method of electric connection structure, array base palte and insulating cover | |
| US9383608B2 (en) | Array substrate and manufacturing method thereof | |
| CN110085600A (en) | Electric connection structure and preparation method thereof, tft array substrate and preparation method thereof | |
| WO2020232926A1 (en) | Array substrate and method for manufacturing array substrate | |
| KR102596074B1 (en) | Display substrate and method of manufacturing the same | |
| CN106292043A (en) | Electric connection structure and array base palte |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |