CN106298795A - Improve memory cell and the method for high tension apparatus electric leakage in storage arrangement - Google Patents
Improve memory cell and the method for high tension apparatus electric leakage in storage arrangement Download PDFInfo
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- CN106298795A CN106298795A CN201610885991.5A CN201610885991A CN106298795A CN 106298795 A CN106298795 A CN 106298795A CN 201610885991 A CN201610885991 A CN 201610885991A CN 106298795 A CN106298795 A CN 106298795A
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- memory cell
- sidepiece
- voltage device
- grid structure
- gate isolation
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000002955 isolation Methods 0.000 claims abstract description 66
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides and a kind of improve the method for memory cell and high tension apparatus electric leakage in storage arrangement, including: first step: forming grid structure, wherein grid structure includes low-voltage device grid structure, high-voltage device grate structure and memory cell grid structure；Second step: the sidepiece at sidepiece, the sidepiece of high-voltage device grate structure and the memory cell grid structure of low-voltage device grid structure forms first gate isolation side wall respectively；Third step: coating photoresist layer, and photoresist layer is carried out photoetching to expose low-voltage device grid structure；4th step: utilize the photoresist layer after photoetching, removes the first gate isolation side wall of low-voltage device grid structure sidepiece；5th step: remove photoresist layer；6th step: the sidepiece at sidepiece, the sidepiece of described high-voltage device grate structure and the described memory cell grid structure of described low-voltage device grid structure forms second gate isolation side wall the most further.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and the invention still further relates to reservoir designs and manufacture field, more specifically
Ground is said, the present invention relates to a kind of improve the method that in storage arrangement, memory cell and high tension apparatus leak electricity.
Background technology
The advantages such as flash memory is convenient with it, and memory density is high, good reliability become the focus of research in non-volatility memorizer.
Since first flash memory products appearance 1980s, along with developing with each electronic product storage of technology
Demand, flash memory is widely used in mobile phone, notebook, and palm PC and USB flash disk etc. move and in communication apparatus.
Flash memory is a kind of nonvolatile memorizer, and its operation principles is by changing the critical of transistor or memory cell
Voltage controls the switch of gate pole passage to reach to store the purpose of data, makes the storage data in memory will not be because of power supply
Interrupt and disappear, and a kind of special construction that flash memory is electrically erasable and programmable read only memory.Nowadays flash memory has accounted for
According to most of market share of non-volatile semiconductor memory, become non-volatile semiconductor memory with fastest developing speed.
Embedded flash memory (embedded flash, e-flash) is the one of SOC(system on a chip) (System on Chip, SOC)
Kind, integrated logic circuit module and flash memory circuit module while of in a piece of integrated circuit, at the product such as smart card, microcontroller
In have been widely used.
When embedded flash memory technology develops towards the direction that size is the least, the low pressure (low relevant to placement rule
Voltage) size of device is more and more less, but the size of the high pressure relevant to placement rule (high voltage) device is then
It is not intended to change.
On the other hand, when embedded flash memory technology develops towards the direction that size is the least, along with placement rule
The size of relevant low-voltage device is more and more less, and the gate isolation side wall of device is more and more less.But, high tension apparatus and
The leakage of memory cell is also affected by the reduction of the critical size of gate isolation side wall.
When the injection of source electrode and/or drain electrode is close to grid, less gate isolation side wall result in bigger grid induction
Drain leakage current (gated-induce drain leakage, GIDL) or raceway groove are revealed.Increase gate isolation side wall
Critical size is limited by low-voltage device placement rule, because the low-voltage device space between grid is necessarily less than high-voltage device
Part.
For above-mentioned situation, it is desirable to be able to provide one to improve memory cell and high tension apparatus electric leakage in storage arrangement
Method.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one can be improved
Memory cell and the method for high tension apparatus electric leakage in storage arrangement.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that one improves memory cell in storage arrangement
The method leaked electricity with high tension apparatus, including:
First step: forming grid structure, wherein grid structure includes that low-voltage device grid structure, high-voltage device grate are tied
Structure and memory cell grid structure；
Second step: at sidepiece, the sidepiece of high-voltage device grate structure and the memory body list of low-voltage device grid structure
The sidepiece of unit's grid structure forms first gate isolation side wall respectively；
Third step: coating photoresist layer, and photoresist layer is carried out photoetching to expose low-voltage device grid structure；
4th step: utilize the photoresist layer after photoetching, remove the first grid of low-voltage device grid structure sidepiece every
From side wall；
5th step: remove photoresist layer；
6th step: the sidepiece of described low-voltage device grid structure, the sidepiece of described high-voltage device grate structure and
The sidepiece of described memory cell grid structure forms second gate isolation side wall the most further.
Preferably, described storage arrangement is embedded flash memory.
Preferably, described memory cell grid structure is the memory cell grid structure of point grid form.
Preferably, in the second step, by deposition gate isolation spacer material layer and to gate isolation spacer material
Layer performs etching, at sidepiece, the sidepiece of high-voltage device grate structure and the memory cell grid of low-voltage device grid structure
The sidepiece of structure forms first gate isolation side wall respectively.
Preferably, the material of described first gate isolation side wall is silicon dioxide.
Preferably, in the 4th step, utilize the photoresist layer after photoetching, low-voltage device grid structure is carried out ion note
Enter to be formed the shallow doped source drain electrode of low-voltage device.
Preferably, in the 6th step, by deposition gate isolation spacer material layer and to gate isolation spacer material
Layer performs etching, at sidepiece, the sidepiece of high-voltage device grate structure and the memory cell grid of low-voltage device grid structure
The sidepiece of structure forms second gate isolation side wall respectively.
Preferably, the material of described second gate isolation side wall is silicon dioxide or silicon dioxide, silicon nitride and oxygen
SiClx (ONO) three-layer composite structure.
Preferably, the sidepiece at described low-voltage device grid structure is only simply formed with described second gate isolation side wall,
And there is no described first gate isolation side wall.
Preferably, at sidepiece and the sidepiece of described memory cell grid structure of described high-voltage device grate structure
It is sequentially formed with described first gate isolation side wall and described second gate isolation side wall.
The present invention increases skew isolation side walls to improve high tension apparatus isolation side walls and the pass of memory cell isolation side walls
Key size；And, the present invention removed low-voltage device isolation side walls before deposition gate isolation side wall；Thus, the present invention improves
Memory cell and high tension apparatus electric leakage in embedded flash memory.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding
And its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows and improves memory cell and height in storage arrangement according to the preferred embodiment of the invention
The flow chart of the method for voltage device electric leakage.
Fig. 2 schematically shows and improves memory cell and height in storage arrangement according to the preferred embodiment of the invention
The first step of the method for voltage device electric leakage.
Fig. 3 schematically shows and improves memory cell and height in storage arrangement according to the preferred embodiment of the invention
The second step of the method for voltage device electric leakage.
Fig. 4 schematically shows and improves memory cell and height in storage arrangement according to the preferred embodiment of the invention
The third step of the method for voltage device electric leakage.
Fig. 5 schematically shows and improves memory cell and height in storage arrangement according to the preferred embodiment of the invention
4th step of the method for voltage device electric leakage.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings in the present invention
Appearance is described in detail.
The present invention increases skew isolation side walls to improve high tension apparatus isolation side walls and the pass of memory cell isolation side walls
Key size；And, the present invention removed low-voltage device isolation side walls before deposition gate isolation side wall；Thus, the present invention improves
Memory cell and high tension apparatus electric leakage in embedded flash memory.
Fig. 1 schematically shows and improves memory cell and height in storage arrangement according to the preferred embodiment of the invention
The flow chart of the method for voltage device electric leakage；And Fig. 2 to Fig. 5 schematically shows and improves according to the preferred embodiment of the invention
The first step of the method for memory cell and high tension apparatus electric leakage in storage arrangement.
Typically, described storage arrangement refers to embedded flash memory；But, it is suitable for the storage of similar structures
Device device.
Specifically, as shown in Fig. 1 and Fig. 2 to Fig. 5, improve according to the preferred embodiment of the invention in storage arrangement and remember
The method recalling body unit and high tension apparatus electric leakage includes:
First step S1: forming grid structure, wherein grid structure includes low-voltage device grid structure 10, high tension apparatus grid
Electrode structure 20 and memory cell grid structure 30；
Preferably, such as, described memory cell grid structure 30 is the memory cell grid structure 30 of point grid form；
Second step S2: at the sidepiece of low-voltage device grid structure 10, the sidepiece of high-voltage device grate structure 20, Yi Jiji
The sidepiece recalling body unit grid structure 30 forms first gate isolation side wall 40 respectively；
Preferably, such as, in second step S2, by deposition gate isolation spacer material layer and to gate isolation side
The walling bed of material performs etching, in sidepiece, the sidepiece of high-voltage device grate structure 20 and the memory of low-voltage device grid structure 10
The sidepiece of body unit grid structure 30 forms first gate isolation side wall 40 respectively.
Preferably, the material of described first gate isolation side wall 40 is silicon dioxide.
Third step S3: coating photoresist layer 50, and photoresist layer 50 is carried out photoetching to expose low-voltage device grid
Electrode structure 10；
4th step S4: utilize the photoresist layer after photoetching 50, removes the first of low-voltage device grid structure 10 sidepiece
Gate isolation side wall 40；
Preferably, in the fourth step s 4, utilize the photoresist layer after photoetching 50, low-voltage device grid structure 10 is carried out
Ion implanting is to form the shallow doped source drain electrode of low-voltage device.
5th step S5: remove photoresist layer 50；
6th step S6: in sidepiece, the side of described high-voltage device grate structure 20 of described low-voltage device grid structure 10
The sidepiece of portion and described memory cell grid structure 30 forms second gate isolation side wall 60 the most further.
Preferably, such as, in the 6th step S6, by deposition gate isolation spacer material layer and to gate isolation side
The walling bed of material performs etching, in sidepiece, the sidepiece of high-voltage device grate structure 20 and the memory of low-voltage device grid structure 10
The sidepiece of body unit grid structure 30 forms second gate isolation side wall 60 respectively.
Preferably, also, the material of described second gate isolation side wall 60 is silicon dioxide or silicon dioxide, nitridation
Silicon and silicon oxide (ONO) three-layer composite structure.
Thus, the sidepiece at described low-voltage device grid structure 10 is only simply formed with described second gate isolation side wall
60, and there is no described first gate isolation side wall 40.Sidepiece and described memory in described high-voltage device grate structure 20
The sidepiece of body unit grid structure 30 is sequentially formed with described first gate isolation side wall 40 and described second gate isolation
Side wall 60.
According to another preferred embodiment of the invention, present invention also offers sampling as shown in Fig. 1 and Fig. 2 to Fig. 5
That improves that the method for memory cell and high tension apparatus electric leakage in storage arrangement makes according to the preferred embodiment of the invention deposits
Reservoir device, the most described storage arrangement is embedded flash memory.
Thus, the present invention increases skew isolation side walls to improve high tension apparatus isolation side walls and memory cell isolation side walls
Critical size；And, the present invention removed low-voltage device isolation side walls before deposition gate isolation side wall；Thus, the present invention
Improve memory cell and high tension apparatus electric leakage in embedded flash memory.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc. rather than for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
In.
But also it should be understood that the present invention is not limited to specific method described herein, compound, material, system
Making technology, usage and application, they can change.Should also be understood that term described herein is used merely to describe specific
Embodiment rather than be used for limit the scope of the present invention.Must be noted that herein and in claims use
Singulative " one ", " a kind of " and " being somebody's turn to do " include complex reference, unless context explicitly indicates that contrary.Therefore, example
As, the citation to " element " means the citation to one or more elements, and includes known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
Multiple steps or the citation of device, and potentially include secondary step and second unit.Should manage with broadest implication
Solve all conjunctions used.Therefore, word "or" should be understood that definition rather than the logical exclusive-OR with logical "or"
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as also quoting from the function of this structure
Equivalent.Can be interpreted that the language of approximation should be understood, like that unless context explicitly indicates that contrary.
Claims (10)
1. one kind is improved memory cell and the method for high tension apparatus electric leakage in storage arrangement, it is characterised in that including:
First step: formed grid structure, wherein grid structure include low-voltage device grid structure, high-voltage device grate structure,
And memory cell grid structure；
Second step: at sidepiece, the sidepiece of high-voltage device grate structure and the memory cell grid of low-voltage device grid structure
The sidepiece of electrode structure forms first gate isolation side wall respectively；
Third step: coating photoresist layer, and photoresist layer is carried out photoetching to expose low-voltage device grid structure；
4th step: utilize the photoresist layer after photoetching, removes the first gate isolation side of low-voltage device grid structure sidepiece
Wall；
5th step: remove photoresist layer；
6th step: at the sidepiece of described low-voltage device grid structure, the sidepiece of described high-voltage device grate structure and described
The sidepiece of memory cell grid structure forms second gate isolation side wall the most further.
The most according to claim 1 improving the method for memory cell and high tension apparatus electric leakage in storage arrangement, it is special
Levying and be, described storage arrangement is embedded flash memory.
The most according to claim 1 and 2 improve the method for memory cell and high tension apparatus electric leakage in storage arrangement, its
Being characterised by, described memory cell grid structure is the memory cell grid structure of point grid form.
The most according to claim 1 and 2 improve the method for memory cell and high tension apparatus electric leakage in storage arrangement, its
It is characterised by, in the second step, by deposition gate isolation spacer material layer and gate isolation spacer material layer is carried out
Etching, at sidepiece, the sidepiece of high-voltage device grate structure and the memory cell grid structure of low-voltage device grid structure
Sidepiece forms first gate isolation side wall respectively.
The most according to claim 1 and 2 improve the method for memory cell and high tension apparatus electric leakage in storage arrangement, its
Being characterised by, the material of described first gate isolation side wall is silicon dioxide.
The most according to claim 1 and 2 improve the method for memory cell and high tension apparatus electric leakage in storage arrangement, its
It is characterised by, in the 4th step, utilizes the photoresist layer after photoetching, low-voltage device grid structure is carried out ion implanting with shape
Become the shallow doped source drain electrode of low-voltage device.
The most according to claim 1 and 2 improve the method for memory cell and high tension apparatus electric leakage in storage arrangement, its
It is characterised by, in the 6th step, by deposition gate isolation spacer material layer and gate isolation spacer material layer is carried out
Etching, at sidepiece, the sidepiece of high-voltage device grate structure and the memory cell grid structure of low-voltage device grid structure
Sidepiece forms second gate isolation side wall respectively.
The most according to claim 1 and 2 improve the method for memory cell and high tension apparatus electric leakage in storage arrangement, its
Being characterised by, the material of described second gate isolation side wall is silicon dioxide or silicon dioxide, silicon nitride and silicon oxide
(ONO) three-layer composite structure.
The most according to claim 1 and 2 improve the method for memory cell and high tension apparatus electric leakage in storage arrangement, its
Being characterised by, the sidepiece at described low-voltage device grid structure is only simply formed with described second gate isolation side wall, and does not has
Described first gate isolation side wall.
The most according to claim 1 and 2 improve the method for memory cell and high tension apparatus electric leakage in storage arrangement,
It is characterized in that, the sidepiece of described high-voltage device grate structure and described memory cell grid structure sidepiece successively
It is formed with described first gate isolation side wall and described second gate isolation side wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610885991.5A CN106298795A (en) | 2016-10-10 | 2016-10-10 | Improve memory cell and the method for high tension apparatus electric leakage in storage arrangement |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610885991.5A CN106298795A (en) | 2016-10-10 | 2016-10-10 | Improve memory cell and the method for high tension apparatus electric leakage in storage arrangement |
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| CN201610885991.5A Pending CN106298795A (en) | 2016-10-10 | 2016-10-10 | Improve memory cell and the method for high tension apparatus electric leakage in storage arrangement |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354522A (en) * | 2000-10-11 | 2002-06-19 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| US20020123180A1 (en) * | 2001-03-01 | 2002-09-05 | Peter Rabkin | Transistor and memory cell with ultra-short gate feature and method of fabricating the same |
| CN1542974A (en) * | 2003-04-28 | 2004-11-03 | ��ʽ���������Ƽ� | Semiconductor device and a method of manufacturing the same |
| CN104916591A (en) * | 2014-03-11 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
-
2016
- 2016-10-10 CN CN201610885991.5A patent/CN106298795A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354522A (en) * | 2000-10-11 | 2002-06-19 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| US20020123180A1 (en) * | 2001-03-01 | 2002-09-05 | Peter Rabkin | Transistor and memory cell with ultra-short gate feature and method of fabricating the same |
| CN1542974A (en) * | 2003-04-28 | 2004-11-03 | ��ʽ���������Ƽ� | Semiconductor device and a method of manufacturing the same |
| CN104916591A (en) * | 2014-03-11 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
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Application publication date: 20170104 |