CN106298738A - CMOS memory unit is without wire stealth method of supplying power to - Google Patents
CMOS memory unit is without wire stealth method of supplying power to Download PDFInfo
- Publication number
- CN106298738A CN106298738A CN201610760187.4A CN201610760187A CN106298738A CN 106298738 A CN106298738 A CN 106298738A CN 201610760187 A CN201610760187 A CN 201610760187A CN 106298738 A CN106298738 A CN 106298738A
- Authority
- CN
- China
- Prior art keywords
- wire
- supplying power
- well
- cmos memory
- stealth method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
Abstract
The present invention relates to design and the layout method of a kind of CMOS SRAM circuit, the unit in array, without wire stealth method of supplying power to, is utilized N well to power PMOS thus reaches to save wiring and save the purpose of area by proposition CMOS memory unit.
Description
Technical field
The present invention is for the design of CMOS SRAM chip, stealthy without wire in particular to a kind of CMOS SRAM memory cell
Method of supplying power to saves wiring, improves area efficiency.
Background technology
Storage class chip is extremely sensitive to price and chip area, and common SRAM has VCC, VSS, WL, BL, BLB five
Port, these need to be connected with plain conductor in array.Plus the wiring requirements in unit, metal wire occupied area is the most straight
Connect and affect array area and chip cost, or at least the utilization rate of wire is had a negative impact.
Summary of the invention
Present invention aim at providing a kind of CMOS memory cell without wire stealth method of supplying power to, reduce the gold of each unit
Belong to line to connect,
Realize the object of the invention and the technical scheme is that in a certain size array, the unit in array is utilized N well
PMOS is powered.The S pole of PMOS is connected by the N+ of N well, and the N well under silicon face realizes connecting.Outside array, logical
The N+ crossed in N well is connected to positive supply,
Accompanying drawing illustrates:
Fig. 1 is the CMOS memory unit of the present invention schematic diagram without SRAM unit main in wire stealth method of supplying power to,
Fig. 2 is the silicon chip schematic layout pattern meeting CMOS memory unit of the present invention without wire stealth method of supplying power to,
Fig. 2 .1 is the structural representation in corresponding diagram 2 C district,
Fig. 3 is to use CMOS memory unit of the present invention without the metal line of tradition method of supplying power to before wire stealth method of supplying power to
Schematic diagram,
Fig. 4 is the use CMOS memory cell of the present invention metal line schematic diagram without wire stealth method of supplying power to,
Fig. 5 use CMOS memory cell of the present invention without the breadboardin schematic diagram of wire stealth method of supplying power to,
Fig. 6 use CMOS memory cell of the present invention without the PMOS wiring construction figure of wire stealth method of supplying power to,
Detailed description of the invention:
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings
As it is shown in figure 1, traditional CMOS sram cell, including five ports of VCC, VSS, BL, BLB, WL,
In traditional design, these five ports all connect with plain conductor, form SRAM kernel array,
Fig. 2 is given the silicon chip schematic layout pattern meeting CMOS memory unit of the present invention without wire stealth method of supplying power to
In figure, A is N well,
B is P wellblock,
N well in array is not connected with VCC,
C is that the N well outside array is connected with VCC,
Fig. 2 .1 is the structural representation in corresponding diagram 2 C district, and N well is connected by N+ with VCC,
Fig. 3 provides the layout example of tradition SRAM array.Based on interlacing mirrored arrangement, each unit VCC and VSS to be divided
In one,
Fig. 4 is to use CMOS memory unit of the present invention without the metal line schematic diagram of wire stealth method of supplying power to, each two
Unit divides VSS mono-,
Use CMOS memory unit of the present invention without wire stealth method of supplying power to it is noted that net is made in the pressure drop bringing N well resistance
Network is analyzed, to determine the size of " stealthy power supply " array.Fig. 5 provides this equivalent circuit analyzed,
Fig. 6 is to use CMOS memory unit of the present invention without PMOS supplier of electricity in a kind of unit of wire stealth method of supplying power to
Method,
In figure, C is N well,
A is P+ D pole,
J is G pole,
D is P+,
E is the B pole that N+ contact N well constitutes PMOS,
F is silicide layer, forms low resistance connection, remove metal wire and via from, can save metal connecting line and via accounts between D, E
Area,
Above example is all for BL/BLB framework, and as used single BL framework instead, the present invention is equally applicable.
Claims (3)
1.CMOS memory cell is characterized in that without wire stealth method of supplying power to, and the unit in array is utilized N well pair
PMOS powers to save metal line, improves area utilization.
2.CMOS memory cell is characterized in that without wire stealth method of supplying power to: the S pole of PMOS is connected by the N+ of N well, warp
Cross the N well under silicon face to realize connecting, outside array, be connected to positive supply by the N+ in N well.
3.CMOS memory cell is characterized in that without wire stealth method of supplying power to: the S pole of PMOS connects through with the N+ of N well
Silicide layer is formed, and removes the metal wire in unit and via from.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610760187.4A CN106298738A (en) | 2016-08-30 | 2016-08-30 | CMOS memory unit is without wire stealth method of supplying power to |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610760187.4A CN106298738A (en) | 2016-08-30 | 2016-08-30 | CMOS memory unit is without wire stealth method of supplying power to |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106298738A true CN106298738A (en) | 2017-01-04 |
Family
ID=57675359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610760187.4A Pending CN106298738A (en) | 2016-08-30 | 2016-08-30 | CMOS memory unit is without wire stealth method of supplying power to |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298738A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192233A (en) * | 2018-09-21 | 2019-01-11 | 宁波奇巧电器科技有限公司 | CMOS memory unit is without conducting wire method of supplying power to |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640187A (en) * | 2009-06-09 | 2010-02-03 | 上海宏力半导体制造有限公司 | Four layer transistor SRAM unit manufacturing method |
| US20130235640A1 (en) * | 2012-03-06 | 2013-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory and method of making the same |
| CN103515389A (en) * | 2012-06-25 | 2014-01-15 | 上海摩晶电子科技有限公司 | Wiring-saving design method for SRAM cell |
-
2016
- 2016-08-30 CN CN201610760187.4A patent/CN106298738A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640187A (en) * | 2009-06-09 | 2010-02-03 | 上海宏力半导体制造有限公司 | Four layer transistor SRAM unit manufacturing method |
| US20130235640A1 (en) * | 2012-03-06 | 2013-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory and method of making the same |
| CN103515389A (en) * | 2012-06-25 | 2014-01-15 | 上海摩晶电子科技有限公司 | Wiring-saving design method for SRAM cell |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192233A (en) * | 2018-09-21 | 2019-01-11 | 宁波奇巧电器科技有限公司 | CMOS memory unit is without conducting wire method of supplying power to |
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| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170104 |