CN106298521A - A kind of semiconductor device and preparation method thereof, electronic installation - Google Patents
A kind of semiconductor device and preparation method thereof, electronic installation Download PDFInfo
- Publication number
- CN106298521A CN106298521A CN201510258284.9A CN201510258284A CN106298521A CN 106298521 A CN106298521 A CN 106298521A CN 201510258284 A CN201510258284 A CN 201510258284A CN 106298521 A CN106298521 A CN 106298521A
- Authority
- CN
- China
- Prior art keywords
- material layer
- semiconductor material
- stressor layers
- groove
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 238000009434 installation Methods 0.000 title claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 9
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 230000008569 process Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
Abstract
The present invention relates to a kind of semiconductor device and preparation method thereof, electronic installation.Described method includes step S1: provides Semiconductor substrate, is formed with semiconductor material layer and the stressor layers of undoped on the semiconductor substrate；Step S2: perform source and drain in described stressor layers and inject, to form source-drain area；Step S3: pattern described stressor layers, to form opening, exposes described semiconductor material layer；Step S4: form clearance wall on the sidewall of described opening；Step S5: with described opening as mask, etches described semiconductor material layer, to form the size groove more than described opening in described semiconductor material layer；Step S6: select grid material to fill described groove and described opening, to form grid structure.The method of the invention reduce further as OXIDATION ENHANCED DIFFUSION, and the transfer electrical benefits (TED) that thus causes and short-channel effect, improves the mobility of transistor channel, junction capacity and drain junction, improves yield and the performance of device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular it relates to a kind of semiconductor device and
Preparation method, electronic installation.
Background technology
Along with the increase day by day of the semiconductor storage demand for high power capacity, these semiconductor storage fill
The integration density put is by more concerns of people, in order to increase the integration density of semiconductor storage,
Prior art have employed many different methods, such as by reducing memory cell size and/or changing knot
Structure unit and on single wafer, form more memory element.
Some foreign atom existed in thermal oxidation process Central Plains in silicon shows higher diffusibility, is referred to as
OXIDATION ENHANCED DIFFUSION (Oxidation-Enhanced Diffusion, OED), continuous along with grid length
Reduce, the impact of described OED effect become that boron or phosphorus extends in NMOS and PMOS main because of
Element.The reallocation of transfer electrical benefits (TED) not only determines the short-channel effect of transistor, equally
Also affect the mobility of transistor channel, junction capacity and drain junction.
In order to improve the performance of semiconductor device in prior art, it will usually use various stress technique, example
As formed SiGe stressor layers, in the case of there is no thermal oxide, Si and Si in PMOS0.8Ge0.2?
In the case of identical ion implanting, stressor layers is the least on the impact of ion doping, and both are almost without difference,
But in rapid thermal annealing process, have in the device of stressor layers due to its ion of effect diffusion of stress
It is well controlled, the Si do not have stressor layers then produces substantial amounts of diffusion.
Therefore form higher channel stress and become a kind of effective technology hands solving current OXIDATION ENHANCED DIFFUSION
How section, form higher channel stress and become crucial.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be in detailed description of the invention
Part further describes.The Summary of the present invention is not meant to attempt to limit institute
The key feature of claimed technical scheme and essential features, more do not mean that and attempt to determine and wanted
Seek the protection domain of the technical scheme of protection.
For the problem existed in the prior art described in solving, it is provided that the preparation of a kind of semiconductor device
Method, including:
Step S1: Semiconductor substrate is provided, is formed with the quasiconductor of undoped on the semiconductor substrate
Material layer and stressor layers；
Step S2: perform source and drain in described stressor layers and inject, to form source-drain area；
Step S3: pattern described stressor layers, to form opening, exposes described semiconductor material layer；
Step S4: form clearance wall on the sidewall of described opening；
Step S5: with described opening as mask, etches described semiconductor material layer, with at described quasiconductor
Material layer is formed the size groove more than described opening；
Step S6: select grid material to fill described groove and described opening, to form grid structure.
Alternatively, in described step S5, described groove is oval-shaped groove.
Alternatively, between described step S5 and described step S6, still further comprise selection H2Or Ar
The step processing described groove, so that described groove profile smooths.
Alternatively, in described step S1, described semiconductor material layer selects III-V compounds of group partly to lead
Body material or silicon materials.
Alternatively, in described step S1, the lower section of described semiconductor material layer is also formed with threshold voltage
Regulating course.
Alternatively, described semiconductor material layer and described threshold voltage adjustments layer are all by epitaxially grown side
Method is formed.
Alternatively, in described step S1, it is also formed with oxidation in the lower section of described threshold voltage adjustments layer
Nitride layer.
Alternatively, in described step S1, described stressor layers is formed with low-doped LDD or anti-source and drain
That injects is lightly doped.
Alternatively, described step S2 includes:
Step S21: form pad oxide skin(coating) in described stressor layers；
Step S22: perform source and drain and inject, to form source-drain area at the top of described stressor layers.
Alternatively, in described step S5, select semiconductor material layer described in wet etching, described wet method
Tetramethylammonium hydroxide is selected in etching.
Alternatively, in described step S6, deposition of gate material lamination in described groove and described opening
And planarize, to form described grid structure.
Alternatively, described method may further include and formed certainly on described grid structure and described source-drain area
The step of alignment silicide.
The invention still further relates to a kind of semiconductor device prepared based on above-mentioned method.
The invention still further relates to a kind of electronic installation, including above-mentioned semiconductor device.
The present invention is to solve problems of the prior art, it is provided that the preparation of a kind of semiconductor device
Method, the most on a semiconductor substrate undoped semiconductor material layer and at described quasiconductor
Form stressor layers on material layer, and in described stressor layers, form the doping that anti-source and drain is injected, to prevent
During dopant ion enters described semiconductor material layer in source and drain injection process, then pattern described stressor layers
And semiconductor material layer, to form up-narrow and down-wide grid knot in described stressor layers and semiconductor material layer
Structure, by the setting of described stressor layers, further increases the stress of described raceway groove, and described raceway groove
For undoped, reduce further into OXIDATION ENHANCED DIFFUSION (Oxidation-Enhanced Diffusion,
OED), and the transfer electrical benefits (TED) that thus causes and short-channel effect, improve transistor
The mobility of raceway groove, junction capacity and drain junction, improve yield and the performance of device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Accompanying drawing shows
Go out embodiments of the invention and description thereof, be used for explaining assembly of the invention and principle.In the accompanying drawings,
Fig. 1 a-1j is the preparation process schematic diagram of heretofore described semiconductor device；
Fig. 2 is the process chart that in the embodiment of the present invention prepared by semiconductor device.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention the most thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without one
Or multiple these details and be carried out.In other example, in order to avoid obscuring with the present invention,
Technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to this
In propose embodiment.On the contrary, it is open thoroughly with complete to provide these embodiments to make, and incite somebody to action this
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He district
Size and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " coupling
Conjunction is arrived " other element or during layer, its can directly on other element or layer, adjacent thereto, connect
Or be coupled to other element or layer, or element between two parties or layer can be there is.On the contrary, claimed when element
For " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other yuan
When part or layer, the most there is not element between two parties or layer.Although it should be understood that can use term first,
Two, the various element of third description, parts, district, floor and/or part, these elements, parts, district,
Layer and/or part should not be limited by these terms.These terms be used merely to distinguish an element, parts,
District, floor or part and another element, parts, district, floor or part.Therefore, without departing from the present invention
Under teaching, the first element discussed below, parts, district, floor or part be represented by the second element,
Parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... under ", " ...
On ", " above " etc., here can describe for convenience and be used thus shown in description figure
One element or feature and other element or the relation of feature.It should be understood that except the orientation shown in figure
In addition, spatial relationship term is intended to also include the different orientation of the device in using and operating.Such as, as
Really the device in accompanying drawing upset, then, be described as " below other element " or " under it " or
" under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term
" ... below " and " ... under " upper and lower two orientations can be included.Device can additionally be orientated (rotation
Turn 90 degrees or other orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and the limit not as the present invention
System.When using at this, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to include plural number
Form, unless context is expressly noted that other mode.It is also to be understood that term " forms " and/or " including ",
When using in this specification, determine described feature, integer, step, operation, element and/or parts
Existence, but be not excluded for one or more other feature, integer, step, operation, element, parts
And/or group existence or interpolation.When using at this, term "and/or" includes any of relevant Listed Items
And all combinations.
In order to thoroughly understand the present invention, detailed step and detailed knot will be proposed in following description
Structure, in order to explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but
In addition to these describe in detail, the present invention can also have other embodiments.
Embodiment 1
The present invention is to solve problems of the prior art, the preparation technology to described semiconductor device
Parameter in step and described step is improved, in order to eliminate the problems referred to above, below in conjunction with the accompanying drawings
The preparation method of semiconductor device of the present invention is further described by 1a-1j.
First, step 101 is performed, it is provided that Semiconductor substrate 101, the most successively shape
Become semiconductor material layer 102, lightly doped stressor layers 103.
Specifically, as illustrated by figures 1 a-1 c, wherein, described Semiconductor substrate 101 can be following being carried
To material at least one: stacking silicon (SSOI) on silicon, silicon-on-insulator (SOI), insulator,
On insulator on stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and insulator
Germanium (GeOI) etc..
Alternatively, wherein said Semiconductor substrate is N-type semiconductor substrate.
Wherein, described semiconductor material layer 102 is N-type drift region, and described semiconductor material layer is by outward
The method prolonged is formed, such as selective epitaxial method, described selective epitaxial selected from LPCVD, VLPCVD,
One in PECVD, UHVCVD, RTCVD, APCVD and MBE.
Wherein, described semiconductor material layer 102 selects group Ⅲ-Ⅴ compound semiconductor material or silicon materials.
Further, described group Ⅲ-Ⅴ compound semiconductor material is by the periodic table of elements III A race and V A race element group
The based semiconductor material become, such as GaAs, GaP etc., but is not limited to this example.
Further, described semiconductor material layer 102 is undoped semiconductor material layer, the most any from
The doping of son.
Alternatively, the channel region of described undoped is between gate oxide and described Semiconductor substrate.
Alternatively, the lower section at the channel region of described undoped is also formed with threshold voltage adjustments layer (figure
Not shown in), for adjusting threshold voltage.
Alternatively, described threshold voltage adjustments layer is all formed by epitaxially grown method.
Being also formed with oxide skin(coating), (not shown) in the lower section of described threshold voltage adjustments layer, it can
To be formed by conventional deposition method.
Being also formed with stressor layers 103 on described semiconductor material layer, wherein, described stressor layers is SiC
Or SiGe etc., but be not limited to that this material.
Wherein, it is lightly doped described in described stressor layers 103 as LDD or anti-source and drain injection light is lightly doped
Doping, to prevent ion doping from entering described semiconductor material layer in subsequent steps.
Perform step 102, described stressor layers 103 performs source and drain and injects, to form source-drain area and non-
The semiconductor material layer of doping.
Specifically, as shown in Figure 1 d, in described stressor layers 103, pad oxide skin(coating) is formed in this step；
Then perform source and drain to inject, to form source-drain area 104 at the top of described stressor layers 103.
In this step due to described stressor layers has be lightly doped LDD or anti-source and drain inject be lightly doped,
It is prevented from ion doping and enters described semiconductor material layer.
Further, described source and drain implantation step can select method commonly used in the art, it is not limited to certain
A kind of.
Perform step 103, pattern described stressor layers 103, to form opening, expose described quasiconductor material
The bed of material 102.
Specifically, as shown in fig. le, mask layer is formed the most on the semiconductor substrate, and
And patterning, stressor layers 103 described in then with the mask layer of described patterning as mask etch, to be formed
Opening, to define grid structure.
Dry etching or wet etching, in one embodiment, Ke Yixuan can be selected in this step
Select N2In conduct etching atmosphere, it is also possible to be simultaneously introduced other a small amount of gas such as CF4、CO2、
O2, described etching pressure can be 2-200mTorr, is chosen as 2-30mTorr, and power is
500-900W, the most described etching period is 5-80s, is chosen as 10-60s, simultaneously at this
Invention is selected bigger gas flow, at N of the present invention2Flow be 30-300sccm, can
Elect 50-100sccm as.
Perform step 104, the sidewall of described opening is formed clearance wall 105.
Specifically, as shown in Figure 1 f, the most described clearance wall 105 can use silicon nitride,
The material of carborundum, silicon oxynitride or a combination thereof.First can be deposited in stressor layers and described opening
Silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer, then use engraving method to form gap
Wall, described clearance wall can have the thickness of 10-30NM.
Perform step 105, with described opening as mask, etch described semiconductor material layer, with described
Semiconductor material layer is formed groove.
Specifically, as shown in Figure 1 g, semiconductor material layer described in wet etching, institute are selected in this step
State wet etching and select Tetramethylammonium hydroxide.
Wherein, described groove is the oval-shaped groove that critical size is more than described opening, due to described groove
Size relatively big, the short-channel effect of grid structure can be reduced after the gate formation further.
Further, after forming described groove, described method still further comprises selection H2Or Ar pair
Described groove processes, so that described groove profile smooths, alternatively, it is also possible to expand described simultaneously
The critical size of groove, as shown in figure 1h.
Perform step 106, select grid material to fill described groove and described opening, to form grid knot
Structure 106.
Specifically, as shown in figure 1i, wherein, the institute above described stressor layers is first removed
State oxygen pad layer.
Then the gate stack such as deposited interfacial layer, diffusion impervious layer, work-function layer and conductive layer smooth
Change, to form grid structure 106.
Perform step 107, stars self-alignment silicide layer on described grid structure and described source-drain area
107。
Specifically, as shown in fig. ij, the forming method of the most described self-aligned silicide is: in
Described grid structure and described source-drain area surface sputtered metal layer, such as nickel metal layer, then carry out fast
Speed intensification annealing (RTA) technique, makes the partial reaction that metal level contacts with grid and regions and source/drain
Become metal silicide layer, complete self-alignment metal silicide technique (salicide).
So far, the introduction of correlation step prepared by the semiconductor device of the embodiment of the present invention is completed.Upper
After stating step, it is also possible to including other correlation step, here is omitted.Further, except above-mentioned step
Outside Zhou, the preparation method of the present embodiment can also be among each step above-mentioned or between different step
Including other steps, these steps all can be realized, the most not by various techniques of the prior art
Repeat again.
The present invention is to solve problems of the prior art, it is provided that the preparation of a kind of semiconductor device
Method, the most on a semiconductor substrate undoped semiconductor material layer and at described quasiconductor
Form stressor layers on material layer, and in described stressor layers, form the doping that anti-source and drain is injected, to prevent
During dopant ion enters described semiconductor material layer in source and drain injection process, then pattern described stressor layers
And semiconductor material layer, to form up-narrow and down-wide grid knot in described stressor layers and semiconductor material layer
Structure, by the setting of described stressor layers, further increases the stress of described raceway groove, and described raceway groove
For undoped, reduce further into OXIDATION ENHANCED DIFFUSION (Oxidation-Enhanced Diffusion,
OED), and the transfer electrical benefits (TED) that thus causes and short-channel effect, improve transistor
The mobility of raceway groove, junction capacity and drain junction, improve yield and the performance of device.
Wherein, Fig. 2 is the process chart that in the embodiment of the present invention prepared by semiconductor device, specifically,
Comprise the following steps:
Step S1: Semiconductor substrate is provided, is formed with the quasiconductor of undoped on the semiconductor substrate
Material layer and stressor layers；
Step S2: perform source and drain in described stressor layers and inject, to form source-drain area；
Step S3: pattern described stressor layers, to form opening, exposes described semiconductor material layer；
Step S4: form clearance wall on the sidewall of described opening；
Step S5: with described opening as mask, etches described semiconductor material layer, with at described quasiconductor
Material layer is formed the size groove more than described opening；
Step S6: select grid material to fill described groove and described opening, to form grid structure.
Embodiment 2
Present invention also offers a kind of semiconductor device, described semiconductor device is selected described in embodiment 1
Prepared by method.It is undoped by raceway groove described in the semiconductor device that the method for the invention prepares
Raceway groove and be formed above stressor layers, further increases the stress of raceway groove, reduces and strengthens into oxidation
Diffusion (Oxidation-Enhanced Diffusion, OED), and the transfer electrical benefits thus caused
And short-channel effect (TED), improve the mobility of transistor channel, junction capacity and drain junction, improve
The yield of device and performance.
Embodiment 3
Present invention also offers a kind of electronic installation, including the semiconductor device described in embodiment 2.Wherein,
Semiconductor device is the semiconductor device described in embodiment 2, or according to the preparation method described in embodiment 1
The semiconductor device obtained.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book,
Game machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen, MP3,
Any electronic product such as MP4, PSP or equipment, it is possible to for any centre including described semiconductor device
Product.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has
Better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
It is only intended to citing and descriptive purpose, and is not intended to limit the invention to described scope of embodiments
In.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, root
Can also make more kinds of variants and modifications according to the teachings of the present invention, these variants and modifications all fall within this
Within inventing scope required for protection.Protection scope of the present invention by the appended claims and etc.
Effect scope is defined.
Claims (14)
1. a preparation method for semiconductor device, including:
Step S1: Semiconductor substrate is provided, is formed with the quasiconductor of undoped on the semiconductor substrate
Material layer and stressor layers；
Step S2: perform source and drain in described stressor layers and inject, to form source-drain area；
Step S3: pattern described stressor layers, to form opening, exposes described semiconductor material layer；
Step S4: form clearance wall on the sidewall of described opening；
Step S5: with described opening as mask, etches described semiconductor material layer, with at described quasiconductor
Material layer is formed the size groove more than described opening；
Step S6: select grid material to fill described groove and described opening, to form grid structure.
Method the most according to claim 1, it is characterised in that in described step S5, described
Groove is oval-shaped groove.
Method the most according to claim 1, it is characterised in that in described step S5 and described step
Still further comprise, between rapid S6, the step selecting H2 or Ar that described groove is processed, so that described
Groove profile smooths.
Method the most according to claim 1, it is characterised in that in described step S1, described
Semiconductor material layer selects group Ⅲ-Ⅴ compound semiconductor material or silicon materials.
Method the most according to claim 1, it is characterised in that in described step S1, described
The lower section of semiconductor material layer is also formed with threshold voltage adjustments layer.
Method the most according to claim 5, it is characterised in that described semiconductor material layer and described
Threshold voltage adjustments layer is all formed by epitaxially grown method.
Method the most according to claim 5, it is characterised in that in described step S1, in institute
The lower section stating threshold voltage adjustments layer is also formed with oxide skin(coating).
Method the most according to claim 1, it is characterised in that in described step S1, described
Stressor layers is formed being lightly doped of low-doped LDD or anti-source and drain injection.
Method the most according to claim 1, it is characterised in that described step S2 includes:
Step S21: form pad oxide skin(coating) in described stressor layers；
Step S22: perform source and drain and inject, to form source-drain area at the top of described stressor layers.
Method the most according to claim 1, it is characterised in that in described step S5, selects
Semiconductor material layer described in wet etching, described wet etching selects Tetramethylammonium hydroxide.
11. methods according to claim 1, it is characterised in that in described step S6, in institute
State in groove and described opening deposition of gate material lamination and planarize, to form described grid structure.
12. methods according to claim 1, it is characterised in that described method still further comprises
Described grid structure and described source-drain area are formed the step of self-aligned silicide.
13. 1 kinds of semiconductor device prepared based on the method one of claim 1 to 12 Suo Shu.
14. 1 kinds of electronic installations, including the semiconductor device described in claim 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510258284.9A CN106298521B (en) | 2015-05-20 | 2015-05-20 | A kind of semiconductor devices and preparation method thereof, electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510258284.9A CN106298521B (en) | 2015-05-20 | 2015-05-20 | A kind of semiconductor devices and preparation method thereof, electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298521A true CN106298521A (en) | 2017-01-04 |
| CN106298521B CN106298521B (en) | 2019-05-17 |
Family
ID=57632832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510258284.9A Active CN106298521B (en) | 2015-05-20 | 2015-05-20 | A kind of semiconductor devices and preparation method thereof, electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298521B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720250B1 (en) * | 2005-10-26 | 2007-05-22 | 주식회사 하이닉스반도체 | Method for forming recess gate of semiconductor device |
| US20080233758A1 (en) * | 2007-03-19 | 2008-09-25 | Hynix Semiconductor Inc. | Method for forming trench and method for fabricating semiconductor device using the same |
| CN101663761A (en) * | 2006-12-15 | 2010-03-03 | 先进微装置公司 | Stress enhanced transistor and methods for its fabrication |
-
2015
- 2015-05-20 CN CN201510258284.9A patent/CN106298521B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720250B1 (en) * | 2005-10-26 | 2007-05-22 | 주식회사 하이닉스반도체 | Method for forming recess gate of semiconductor device |
| CN101663761A (en) * | 2006-12-15 | 2010-03-03 | 先进微装置公司 | Stress enhanced transistor and methods for its fabrication |
| US20080233758A1 (en) * | 2007-03-19 | 2008-09-25 | Hynix Semiconductor Inc. | Method for forming trench and method for fabricating semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106298521B (en) | 2019-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103311185B (en) | Method of hybrid high-k/metal-gate stack fabrication | |
| US8994072B2 (en) | Reduced resistance SiGe FinFET devices and method of forming same | |
| JP4299736B2 (en) | Super-scalable high-speed heterojunction vertical N-channel MISFET and method | |
| US10325817B2 (en) | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors | |
| US8993395B2 (en) | Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers | |
| US7888194B2 (en) | Method of fabricating semiconductor device | |
| US20130149830A1 (en) | Methods of forming field effect transistors having silicon-germanium source/drain regions therein | |
| US10867862B2 (en) | Semiconductor method and device | |
| KR20090019693A (en) | Strained semiconductor device and method of making same | |
| CN105762068A (en) | Semiconductor element and manufacture method thereof | |
| CN103928518A (en) | Finfet Device And Method Of Fabricating Same | |
| WO2011079596A1 (en) | Mosfet structure and the manufactring method thereof | |
| WO2013095750A1 (en) | Contact structures for semiconductor transistors | |
| US7135365B2 (en) | Method of manufacturing MOS transistors | |
| CN105428238A (en) | FinFET device, manufacturing method thereof, and electronic device | |
| CN105448834A (en) | Semiconductor structures with different strain states of transistor channels, and method for fabricating the same | |
| CN104465760A (en) | Semiconductor device | |
| CN106601677A (en) | Semiconductor device and manufacturing method thereof, and electronic device | |
| US8541847B2 (en) | Semiconductor device and method for fabricating the same | |
| CN102655094B (en) | A kind of semiconductor structure and manufacture method thereof | |
| WO2012071814A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN106298521A (en) | A kind of semiconductor device and preparation method thereof, electronic installation | |
| CN108447823A (en) | A kind of semiconductor devices and its manufacturing method and electronic device | |
| CN106981424A (en) | A kind of semiconductor devices and its manufacture method, electronic installation | |
| CN107919368B (en) | Semiconductor device, manufacturing method thereof and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |