CN106294226A - SSD controller chip based on embedded STT MRAM, solid state hard disc - Google Patents
SSD controller chip based on embedded STT MRAM, solid state hard disc Download PDFInfo
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- CN106294226A CN106294226A CN201610605956.3A CN201610605956A CN106294226A CN 106294226 A CN106294226 A CN 106294226A CN 201610605956 A CN201610605956 A CN 201610605956A CN 106294226 A CN106294226 A CN 106294226A
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- ftl
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- interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The invention discloses a kind of SSD controller chip based on embedded STT MRAM, solid state hard disc, including font end protocols interface, flash interface and flash translation layer (FTL) FTL, described SSD controller chip also includes the nonvolatile memory STT MRAM embedded, described STT MRAM is connected by data/address bus with font end protocols interface, flash interface, flash translation layer (FTL) FTL, the data that described STT MRAM issues for receiving front-end protocol interface cache, and store flash translation layer (FTL) FTL mapping item.The solid state hard disc of the present invention includes described controller chip.The present invention greatly simplifies the controller architecture design of SSD, can leave and take bigger space and can support the placement of more flash chip, reach jumbo design requirement on pcb board.
Description
Technical field
The invention belongs to chip design art field, particularly relate to a kind of SSD controller based on embedded STT-MRAM
Chip, solid state hard disc.
Background technology
Solid-state hard disk SSD (Solid State Drives) is by controller and memory element (FLASH chip, dram chip)
Composition.Along with the decline of SSD cost based on NAND Flash medium, along with cloud computing and the development of data center, add
The progress of NAND Flash technique, in recent years, enterprise-level SSD is at server, and the application in data center field is more and more extensive.
The internal structure of the SSD of prior art as it is shown in figure 1, in one piece of substrate P CB, mainly include controller chip,
Cache chip (DRAM) and flash chip (NAND Flash).Wherein controller chip is as in figure 2 it is shown, include font end protocols interface
(Interface Protocol IP), flash interface (NAND Flash Interface) and DDR physical interface (DDR
And DDR controller (DDR Controller), flash translation layer (FTL) FTL (Flash translation layer) PHY).Currently,
In the controller architecture design of enterprise-level SSD, in order to support jumbo demand, flash translation layer (FTL) FTL (Flash
Translation layer) amount of storage more and more huger, such as in order to support the demand of Large Copacity such as 16T, SSD controller
The capacity of corresponding DRAM needs at least more than 16GB.Such jumbo DRAM, causes SSD to occur following asking in design
Topic:
The limited space of the PCB of SSD, in order to place jumbo dram chip, pcb board is used for paste the sky of flash chip
Between will tail off, inherently govern the jumbo design requirement of SSD；
Owing to DRAM stores the most crucial content (FTL list item) of SSD controller, therefore meet with power down extremely
Time, need brushing under the FTL table of DRAM to NAND FLASH, therefore in standby electricity design, need quantity consumed huge
SMD tantalum electric capacity standby electric flux is provided, cause the free space on PCB to reduce further, the most also govern SSD
Large Copacity design requirement.
Scheme commonly used in the trade is to store FTL list item with external DRAM granule, uses plug-in DRAM, needs at chip internal
Want extra DDRPHY and DDR controller IP to carry out adaptation, on design on board level, need extra PCB space to paste
DRAM granule, therefore very big for the consumption of cost and the difficulty impact of design, especially for consumer level SSD field, this
Scheme is substantially difficult to meet the demand of low cost.
Summary of the invention
It is an object of the invention to provide a kind of SSD controller chip based on embedded STT-MRAM, solid state hard disc, to keep away
Exempt from the technical problem brought because of external DRAM in background technology, greatly simplify the controller architecture design of SSD.
To achieve these goals, technical solution of the present invention is as follows:
A kind of SSD controller chip based on embedded STT-MRAM, including font end protocols interface, flash interface and flash memory
Conversion layer FTL, described SSD controller chip also include embed nonvolatile memory STT-MRAM, described STT-MRAM with
Font end protocols interface, flash interface, flash translation layer (FTL) FTL are connected by data/address bus, and described STT-MRAM is used for receiving front-end
The data that protocol interface issues cache, and store flash translation layer (FTL) FTL mapping item.
Further, described STT-MRAM is additionally operable to store firmware Firmware, supports firmware Firmware online upgrading.
The invention allows for a kind of solid state hard disc, described solid state hard disc includes pcb board and is positioned on described pcb board
Flash chip, it is characterised in that be additionally provided with above-mentioned SSD controller core based on embedded STT-MRAM on described pcb board
Sheet.
A kind of based on embedded STT-MRAM SSD controller chip of present invention proposition, solid state hard disc, in SSD control
Device chip embeds STT-MRAM, utilizes embedded STT-MRAM to store FTL list item, substitute in conventional art external
DRAM, greatly simplifies the controller architecture design of SSD.Further, since eliminate SMD tantalum electric capacity, can on pcb board
Leave and take bigger space and can support more NAND FLASH placement, reach jumbo design requirement.In addition, simplify
Ddr interface within controller chip is correlated with IP design, utilizes the internal bus interface of embedded STT-MRAM, both simplified
Design difficulty, can improve again the impact for DDR high speed signal that plate upward wiring time delay brings.
Accompanying drawing explanation
Fig. 1 is prior art solid state hard disc board structure of circuit schematic diagram；
Fig. 2 is that prior art SSD controller connects block schematic illustration；
Fig. 3 is the structural representation of SSD controller chip of the present invention.
Detailed description of the invention
Being described in further details technical solution of the present invention with embodiment below in conjunction with the accompanying drawings, following example are not constituted
Limitation of the invention.
Prior art as in figure 2 it is shown, controller chip include font end protocols interface (Interface Protocol IP),
Flash interface (NAND Flash Interface) and DDR physical interface (DDR PHY) and DDR controller (DDR
Controller), flash translation layer (FTL) FTL (Flash translation layer).Font end protocols interface mainly be responsible for receive and
Process the read write command that issues of host computer side and get off to be stored in DRAM by data receiver, the scene that performance requirement is high is substantially selected
With the interface of PCIe GEN3 based on NVMe agreement, in addition, SAS 12G and SATA interface are also current SSD font end protocols
The popular protocol of interface.Flash interface is mainly responsible for processing the data with flash chip and order exchange, is responsible for host computer side
Read write command changes into the standard NAND Interface order of compatible ONFI and Toggle, and does data between flash chip and DRAM
Read-write mutual.Controller chip is communicated with external dram chip by DDR controller, DDR physical interface, plug-in
Dram chip mainly has two aspects, on the one hand as the caching of read-write data, is on the other hand access FTL mapping table.Read-write
The caching of data and this amount of capacity sum of two pieces of FTL mapping table, in enterprise-level SSD field generally more than more than 4GB, and band
Wide requirement is the highest, more than 4GB/s.In order to meet this type of design requirement, for adaptive DDR agreement in chip design, need exploitation
DDR Controller and DDR PHY carries out adaptation, on PCB additional space to be reserved carry out dram chip arrangement and
High speed signal placement-and-routing.
FTL in prior art controller chip mainly processes logical block addresses LBA that main frame issues to flash chip
In storage physical block address PBA between mapping table, be allow flash memory simulate completely conventional hard operation software layer, have
FTL layer, flash memory device could use, and the efficiency of FTL layer directly affects the performance of equipment.The Main Function bag of FTL at present
Include these points:
The logically and physically mapping (Mapping) of address；The process (GC) of garbage reclamation；The supply (OP) in increment space；
The exchange of cold heat data processes；Plane, chip, interchannel parallel processing；The sequence of task requests；The management of relief area；
The management of bad block；The process of abrasion equilibration；The process of power loss recovery；The process of ECC.
Meanwhile, on the pcb board of solid-state hard disk SSD, in addition to controller chip and substantial amounts of flash chip, also include
Standby electricity electric capacity (Electrical Capacity), its effect is able to the situation in unexpected power down, it is possible in time
The FTL list item of storage in dram chip, under the support of standby electricity electric capacity electricity, it is possible to safety lower brush in time is to non-volatile Jie
Matter (NAND FLASH), prevents FTL list item from losing the event of data loss caused.
The general thought of the present invention is embedding STT-MRAM in controller chip, is used for substituting plug-in dram chip,
Thus eliminate the DDR PHY in controller chip and the layout of DDR Controller, and save DRAM and take solid-state
The space of hard disk PCB, is conducive to arranging more flash chip on pcb board, expands the capacity of SSD.
As it is shown on figure 3, a kind of SSD controller chip based on embedded STT-MRAM of the present embodiment, including font end protocols
Interface (Interface Protocol IP), flash interface (NAND Flash Interface), flash translation layer (FTL) FTL
(Flash translation layer) and nonvolatile memory STT-MRAM, STT-MRAM and font end protocols interface,
Flash interface, flash translation layer (FTL) FTL are connected by data/address bus (bus).
Visible, the present embodiment SSD controller chip, compared with the prior art of Fig. 2, has lacked DDR physical interface (DDR
PHY) and DDR controller (DDR Controller), many STT-MRAM.
Owing to STT-MRAM has the read or write speed close to SRAM, extremely low static state and dynamic power consumption, and possess
The characteristic that electricity is the most volatile, is as the born excellent medium storing FTL list item in SSD controller.The present embodiment STT-MRAM
As Embedded Memory, use the data address bus interface of internal SRAM-like, be directly integrated in the controller of SSD
Chip internal, replacing external DRAM becomes data and the storage medium of FTL list item.
STT-MRAM is the EBI form being similar to SRAM (SRAM-like) at the data/address bus that chip internal uses,
Selecting CS including sheet, write enable WE, read to enable RE, output enables signal OE, reset RST, clock CLK, address wire Ax, data wire
Dx.The present embodiment STT-MRAM uses data/address bus and controller internal other modules such as font end protocols interface, flash interface, sudden strain of a muscle
Deposit conversion layer FTL to interact, it is possible to greatly reduce signal transmission delay and external interface protocol expense.
The effect following points of the present embodiment STT-MRAM:
1. the data that receiving front-end protocol interface issues, as the data buffer storage mutual with rear end flash interface；
2. storage flash translation layer (FTL) (FTL) mapping item；
3. storage metadata, such as active page number, bad block management etc.；
4. deposit Firmware with the segment space of STT-MRAM, the online upgrading of Firmware firmware can be supported,
Save NOR Flash resource.
In sum, the design of the present embodiment controller chip, have the advantages that
1, save the internal extra DDR controller of controller chip and the expense of PHY IP, save development cost.
2, STT-MRAM directly embeds controller chip with SRAM-like data/address bus, it is possible to use the height of STT-MRAM
Read or write speed 5ns/10ns, and the high speed signal interface of the DDR wiring delay on pcb board can be reduced, improve read-write efficiency.
3, can utilize that STT-MRAM's is non-volatile, storage RTL list item and log sheet, Firmware etc., save significantly
The difficulty of system design and data protection during powered-off fault and system reconstructing flow process are saved.
4, owing to simplifying standby electricity design and flow process, it is possible to the task of simplifying design team in the design process becomes with manpower
This.
To this end, the invention allows for a kind of solid state hard disc, this solid state hard disc use as shown in Figure 3 based on embedded
The SSD controller chip of STT-MRAM.
It is easily understood that use the controller chip of the present invention, the pcb board of SSD is no longer necessary to dram chip, because of
This can simplify the hardware designs of PCB of SSD disc, saves substantial amounts of SMD tantalum electric capacity, thus increases flash chip.According to
The design of certain enterprise-level SSD, in the hardware designs of disc PCB, in order to meet the energy requirement of standby electricity, places altogether
About more than 500 tantalum electric capacity, if these tantalum electric capacity are all removed, is used for pasting the die of NAND FLASH, at least can support
SSD dish capacity boost more than 20%.
Above example is only limited in order to technical scheme to be described, without departing substantially from present invention essence
In the case of god and essence thereof, those of ordinary skill in the art are when making various corresponding change and change according to the present invention
Shape, but these change accordingly and deform the protection domain that all should belong to appended claims of the invention.
Claims (3)
1. a SSD controller chip based on embedded STT-MRAM, turns including font end protocols interface, flash interface and flash memory
Change a layer FTL, it is characterised in that described SSD controller chip also includes the nonvolatile memory STT-MRAM embedded, described
STT-MRAM is connected by data/address bus with font end protocols interface, flash interface, flash translation layer (FTL) FTL, and described STT-MRAM uses
The data issued in receiving front-end protocol interface cache, and store flash translation layer (FTL) FTL mapping item.
SSD controller chip based on embedded STT-MRAM the most according to claim 1, it is characterised in that described
STT-MRAM is additionally operable to store firmware Firmware, supports firmware Firmware online upgrading.
3. a solid state hard disc, described solid state hard disc includes pcb board and is positioned at the flash chip on described pcb board, its feature
It is, described pcb board is additionally provided with SSD controller core based on embedded STT-MRAM as claimed in claim 1 or 2
Sheet.
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| CN201610605956.3A CN106294226A (en) | 2016-07-27 | 2016-07-27 | SSD controller chip based on embedded STT MRAM, solid state hard disc |
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| CN201610605956.3A CN106294226A (en) | 2016-07-27 | 2016-07-27 | SSD controller chip based on embedded STT MRAM, solid state hard disc |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107220001A (en) * | 2017-05-18 | 2017-09-29 | 记忆科技(深圳)有限公司 | A kind of solid state hard disc cache implementing method and solid state hard disc |
| CN107678686A (en) * | 2017-09-19 | 2018-02-09 | 山东存储之翼电子科技有限公司 | The method and its data storage device of the FTL functions of flash memory are realized based on hardware |
| CN108959589A (en) * | 2018-07-11 | 2018-12-07 | 中电海康集团有限公司 | Accelerate the method for solid-state memory journal file saving/restoring based on STT-MRAM |
| CN109240870A (en) * | 2018-09-25 | 2019-01-18 | 浪潮电子信息产业股份有限公司 | A kind of solid state hard disk Fault Locating Method and relevant apparatus |
| CN109284070A (en) * | 2018-08-24 | 2019-01-29 | 中电海康集团有限公司 | One kind being based on STT-MRAM solid-state memory power interruption recovering method |
| CN110196817A (en) * | 2018-02-27 | 2019-09-03 | 爱思开海力士有限公司 | The operating method of data storage device and the data storage device |
| CN111506255A (en) * | 2019-01-31 | 2020-08-07 | 山东存储之翼电子科技有限公司 | NVM-based solid state hard disk metadata management method and system |
| CN115291814A (en) * | 2022-10-09 | 2022-11-04 | 深圳市安信达存储技术有限公司 | Embedded memory core data storage method, embedded memory chip and memory system |
| CN116881179A (en) * | 2023-09-06 | 2023-10-13 | 苏州浪潮智能科技有限公司 | Solid state disk configuration method, solid state disk and server |
| CN117453632A (en) * | 2023-12-25 | 2024-01-26 | 杭州计算机外部设备研究所(中国电子科技集团公司第五十二研究所) | Data storage method and device |
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| CN109284070A (en) * | 2018-08-24 | 2019-01-29 | 中电海康集团有限公司 | One kind being based on STT-MRAM solid-state memory power interruption recovering method |
| CN109284070B (en) * | 2018-08-24 | 2021-12-10 | 中电海康集团有限公司 | Solid-state storage device power-off recovery method based on STT-MRAM |
| CN109240870A (en) * | 2018-09-25 | 2019-01-18 | 浪潮电子信息产业股份有限公司 | A kind of solid state hard disk Fault Locating Method and relevant apparatus |
| CN111506255A (en) * | 2019-01-31 | 2020-08-07 | 山东存储之翼电子科技有限公司 | NVM-based solid state hard disk metadata management method and system |
| CN111506255B (en) * | 2019-01-31 | 2023-09-26 | 山东存储之翼电子科技有限公司 | NVM-based solid-state hard disk metadata management method and system |
| CN115291814A (en) * | 2022-10-09 | 2022-11-04 | 深圳市安信达存储技术有限公司 | Embedded memory core data storage method, embedded memory chip and memory system |
| CN116881179A (en) * | 2023-09-06 | 2023-10-13 | 苏州浪潮智能科技有限公司 | Solid state disk configuration method, solid state disk and server |
| CN116881179B (en) * | 2023-09-06 | 2024-01-23 | 苏州浪潮智能科技有限公司 | Solid state disk configuration method, solid state disk and server |
| CN117453632A (en) * | 2023-12-25 | 2024-01-26 | 杭州计算机外部设备研究所(中国电子科技集团公司第五十二研究所) | Data storage method and device |
| CN117453632B (en) * | 2023-12-25 | 2024-04-12 | 杭州计算机外部设备研究所(中国电子科技集团公司第五十二研究所) | Data storage method and device |
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