CN106252218A - Trench MOSFET grid etch process - Google Patents
Trench MOSFET grid etch process Download PDFInfo
- Publication number
- CN106252218A CN106252218A CN201610874740.7A CN201610874740A CN106252218A CN 106252218 A CN106252218 A CN 106252218A CN 201610874740 A CN201610874740 A CN 201610874740A CN 106252218 A CN106252218 A CN 106252218A
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- Prior art keywords
- etching
- polysilicon
- trench mosfet
- height
- etch process
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 230000008569 process Effects 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a kind of trench MOSFET grid etch process, described grid is polysilicon material, after completing polysilicon deposit filling in groove, its etching technics comprises two steps: first first step etching uses isotropic etching, reducing shoulder height, the etch amount of the first step accounts for the 25%～75% of total etch amount；Carrying out the anisotropic etching of second step the most again, the height of step keeps constant.The present invention passes through isotropism and anisotropy two step etching technics, first passes through the isotropic etching of the first step and reduces the height of step, and isotropic etching makes shoulder height remain unchanged the most again, improves the flatness of silicon chip surface.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of trench MOSFET grid etch process.
Background technology
Groove type power MOS FET, as a kind of vertical structure device, has that switching speed is fast, frequency performance good, input resistance
Anti-height, drive that power is little, good temp characteristic, without advantages such as second breakdown problems, at manostat, power management module, machine
The fields such as electric control, display control, automotive electronics are widely used.Its grid structure of groove type power MOS FET is not
Parallel with substrate surface plane but build and be perpendicular to surface in the trench, the less and electric current flowing that therefore takes up room is real
Vertically, energy minimization cellar area, in same space can integrated more unit thus reduce the conducting resistance of device also
And maintain electric capacity constant.
For part of trench type MOSFET product, owing to groove width is relatively big, as it is shown in figure 1, formed after polysilicon deposit
Depression relatively big, as in figure 2 it is shown, further, due to traditional handicraft polysilicon return carve board such as DPS, the DPS+ used or
LAM board, belongs to anisotropic etching, and the step being etched back to be formed afterwards at polysilicon is relatively big, and then follow-up inter-level dielectric forms sediment
After Ji, surface step is relatively big, and the shoulder height before and after etching has almost no change, as shown in Figure 3.Fig. 4 is the groove-shaped of formation
The profile of MOSFET, Fig. 5 is partial enlarged drawing, and display is obviously caved in publishing picture.These depressions are susceptible to contact
It is susceptible to the series of problems such as metal residual in hole lithographic defocus, and inter-level dielectric groove.
Summary of the invention
The technical problem to be solved is to provide a kind of trench MOSFET grid etch process, to reduce
Shoulder height after etching polysilicon, thus improve the flatness of silicon chip surface.
For solving the problems referred to above, trench MOSFET grid etch process of the present invention, described grid is many
Crystal silicon, its etching technics comprises two steps: first first step etching uses isotropic etching；Carry out the most again second step each to
Anisotropic etch.
Further, described first step isotropic etching reduces shoulder height, and the etch amount of the first step accounts for total etch amount
25%～75%.
Further, after described second step anisotropic etching, the height of step keeps constant.
Trench MOSFET grid etch process of the present invention, by two step etching technics, first passes through
The isotropic etching of one step reduces the height of step, and anisotropic etching makes shoulder height remain unchanged the most again, changes
It is apt to the flatness of silicon chip surface.
Accompanying drawing explanation
Fig. 1 is that etching groove completes schematic diagram.
Fig. 2 is trench fill complete polysilicon schematic diagram.
Fig. 3 is the schematic diagram after etching polysilicon.
Fig. 4 is the generalized section of the trench MOSFET that Conventional processing methods is formed.
Fig. 5 is the close-up schematic view of Fig. 4.
Fig. 6 is the schematic diagram after the inventive method first step polysilicon isotropic etching.
Fig. 7 is the schematic diagram after the inventive method second step polysilicon anisotropic etching.
Fig. 8 is the micro-schematic diagram of section after the deposit of embodiment of the present invention polysilicon.
Fig. 9 is the step that after embodiment polysilicon deposits, traditional handicraft etching is formed.
Figure 10 is the generalized section after embodiment of the present invention polysilicon first step etching.
Figure 11 is the generalized section after embodiment of the present invention polysilicon second step etching.
Figure 12 is the inventive method flow chart of steps.
Detailed description of the invention
Trench MOSFET grid etch process of the present invention, described grid is polysilicon material, at groove
After inside completing polysilicon deposit filling, its etching technics comprises two steps: first first step etching uses isotropic etching, fall
Low shoulder height, the etch amount of the first step accounts for the 25%～75% of total etch amount；The anisotropy carrying out second step the most again is carved
Erosion, the height of step keeps constant.
By way of example, it will be assumed that a groove width is 1.6 μm, in groove, deposit filling polysilicon is to form grid, deposit
Polysilicon thickness be 1.2 μm, after deposit formed shoulder height be aboutAs shown in Figure 8.
After using traditional technique to etching polysilicon, the step of formation is aboutAs shown in Figure 9.
Present invention process, the first first step is used to use canon 8220 board, utilize isotropism to carve polysilicon
Erosion, etch amount is aboutAfter etching, polysilicon shoulder height is reduced toLeft and right, as shown in Figure 10.
Carrying out second step anisotropic etching again, continue etches polycrystalline silicon, after having etched, shoulder height is through measuring about
ForLeft and right, actual is measured asAs shown in figure 11.
Trench MOSFET grid etch process of the present invention, by two step isotropism etching technics,
First passing through the isotropic etching of the first step and reduce the height of step, anisotropic etching makes shoulder height tie up the most again
Hold constant, improve the flatness of silicon chip surface.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.Those skilled in the art is come
Saying, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of being made, equivalent
Replacement, improvement etc., should be included within the scope of the present invention.
Claims (3)
1. a trench MOSFET grid etch process, described grid is polysilicon, fills full polysilicon in groove, its
Being characterised by: after polysilicon has been filled, the etching technics of described polysilicon comprises two steps: first first step etching use each to
The same sex etches；Carry out the anisotropic etching of second step the most again.
2. trench MOSFET grid etch process as claimed in claim 1, it is characterised in that: the described first step respectively to
Same sex etching reduces shoulder height, and the isotropic etch amount of the first step accounts for the 25%～75% of total etch amount.
3. trench MOSFET grid etch process as claimed in claim 1, it is characterised in that: described second step respectively to
After anisotropic etch, the height of step keeps constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874740.7A CN106252218A (en) | 2016-09-30 | 2016-09-30 | Trench MOSFET grid etch process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874740.7A CN106252218A (en) | 2016-09-30 | 2016-09-30 | Trench MOSFET grid etch process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106252218A true CN106252218A (en) | 2016-12-21 |
Family
ID=57612548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610874740.7A Pending CN106252218A (en) | 2016-09-30 | 2016-09-30 | Trench MOSFET grid etch process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106252218A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231544A (en) * | 2018-01-11 | 2018-06-29 | 上海华虹宏力半导体制造有限公司 | Improve the method for polysilicon step side metal residual |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050142867A1 (en) * | 2003-12-24 | 2005-06-30 | Hynix Semiconductor Inc. | Method for forming polysilicon plug of semiconductor device |
| US20060141696A1 (en) * | 2004-12-28 | 2006-06-29 | Ik-Soo Choi | Method for forming landing plug contact in semiconductor device |
| KR100936805B1 (en) * | 2007-05-04 | 2010-01-14 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device for prevent not open and punch |
| CN103094087A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Method of etching groove polycrystalline silicon gate |
-
2016
- 2016-09-30 CN CN201610874740.7A patent/CN106252218A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050142867A1 (en) * | 2003-12-24 | 2005-06-30 | Hynix Semiconductor Inc. | Method for forming polysilicon plug of semiconductor device |
| US20060141696A1 (en) * | 2004-12-28 | 2006-06-29 | Ik-Soo Choi | Method for forming landing plug contact in semiconductor device |
| KR100936805B1 (en) * | 2007-05-04 | 2010-01-14 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device for prevent not open and punch |
| CN103094087A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Method of etching groove polycrystalline silicon gate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231544A (en) * | 2018-01-11 | 2018-06-29 | 上海华虹宏力半导体制造有限公司 | Improve the method for polysilicon step side metal residual |
| CN108231544B (en) * | 2018-01-11 | 2020-06-09 | 上海华虹宏力半导体制造有限公司 | Method for improving metal residue on side surface of polycrystalline silicon step |
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| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20161221 |