CN106249660B - The conflation unit and method of compatible to IEC 61850-9-2 and IEC60044-8 specification - Google Patents
The conflation unit and method of compatible to IEC 61850-9-2 and IEC60044-8 specification Download PDFInfo
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- CN106249660B CN106249660B CN201610767469.7A CN201610767469A CN106249660B CN 106249660 B CN106249660 B CN 106249660B CN 201610767469 A CN201610767469 A CN 201610767469A CN 106249660 B CN106249660 B CN 106249660B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
- G05B19/0425—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2604—Test of external equipment
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2612—Data acquisition interface
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Abstract
The invention discloses the conflation units of a kind of compatible to IEC 61850-9-2 and IEC60044-8 collector specification comprising for providing opening into module, DIO (input and output module) module, the CPU module for providing intelligent acess and signal-data processing and for each plug-in unit providing the power module of working power for intake access；The CPU module receives the message that IEC61850-9-2 acquires standard and IEC60044-8 acquires standard by grafting, and is unified format synchronization process by the processing of received packet parsing.The present invention supports IEC61850-9-2 and IEC60044-8256 point sampling rate, the input of IEC61850-9-2 and IEC60044-880 point sampling rate；80 point IEC61850-9-2 sampling value messages of output and 256 point IEC61850-9-2 sampling value messages are supported simultaneously；It is compatible on device collector input interface hardware, it is only necessary to replace optical module i.e. and different types of collector input can be switched, the input of compatible various collector specifications can be maximized using this kind of device.
Description
Technical field
The present invention relates to the numbers of a kind of compatible to IEC 61850-9-2 collector specification and IEC60044-8 collector specification
Combining unit and its compatibility method belong to intelligent substation automatic safety device field.
Background technique
Since at the end of the 20th century, intelligence is directly adopted by there is original protective device to pass through traditional mutual inductor in substation secondary side
Change substation and is sent to protection, then the direct number to a new generation's station electronic mutual inductor at digital quantity by combining unit sample conversion
The output of word amount, substation just step into digital area.The features such as digitizing technique has interference resistance strong, and wiring is simple,
Substation's rugged environment can be preferably adapted to traditional wired mode ratio.Electronic mutual inductor is as the significant of digitizing station
The importance of equipment, matched digital combining unit also shows one spot.
Although each electronic mutual inductor is with IEC61850-9-2(SV) and privately owned IEC60044-8(FT3) based on format,
But the message format of output is not fixed, therefore matched digital combining unit is often used according to electronic mutual inductor
The message format of output carry out the received mode of customizing device and researched and developed.The mode of this " one-to-one " customization greatly limits
The compatibility of device is made.
In addition, this customization mode also adds the cost of production cost and substation's O&M.Therefore, the urgent need in market
A kind of digital combining unit is wanted, not only can compatible to IEC 61850-9-2(SV) message, while being also compatible with the IEC60044- of mainstream
8(FT3) specification, to solve the problems, such as digital combining unit poor compatibility, the O&M difficulty and cost at the scene of reducing.
Summary of the invention
It is an object of the invention to overcome deficiency in the prior art, and provide a kind of compatible to IEC 61850-9-2 and
The conflation unit and its working method of IEC60044-8 collector specification, to solve digital combining unit poor compatibility
Problem, the O&M difficulty and cost at the scene of reducing.
In order to achieve the above objectives, the technical scheme adopted by the invention is that:
A kind of conflation unit of compatible to IEC 61850-9-2 and IEC60044-8 collector specification, it is characterised in that:
It include for provide intake access open into module, DIO(input and output module) module, for providing intelligent acess and letter
The CPU module and provide the power module of working power for each plug-in unit that number is handled；The CPU module passes through grafting
The message of IEC61850-9-2 acquisition standard and IEC60044-8 acquisition standard is received, and is system by the processing of received packet parsing
One format synchronization process.
Plug-in unit is equipped with 2 tunnels cascade Ethernet interface (0,1 mouthful), 6 road electronic mutual inductor data access mouths (2-7 mouthfuls), all the way
Ethernet debugging mouth (PPC mouthfuls) and all the way clock synchronization signal port (SYNC).In addition, the function such as dissection process of device docking receiving text
It can also be completed on plug-in unit.
A kind of compatibility method using above-mentioned conflation unit, method include the following:
(1) buffer area of FPGA is expanded, carries out division region by mouth on memory；
(2) FPGA and CPU uses the data interaction of CPU inquiry mode, and CPU inquires the reception of FPGA at regular intervals
With send buffer area BD, when CPU inquires reception buffering BD non-empty, be responsible for reading appointed buffer data and by BD by CPU
Non-empty mark clear 0；Other messages are no longer received if reception buffering is full up until the CPU non-empty that will receive buffering BD identifies clearly
0；
When CPU needs to send message, it is necessary first to which inquiry sends the mark of occupancy of buffering BD, if having occupied mark
It is 1, then there are no transmissions to terminate for the transmission buffer data, and CPU must not write data toward the buffer area；
It is identified as 0 if occupied, which does not have data to be sent, and CPU can write number toward the buffer area
According to by CPU having occupied mark after writing and set 1 and sent data by FPGA.
(3) type expansion is carried out to configuration file, in configuration message type, distributes access port first, secondly define light
The every 256 point sampling rate of cycle of the type IEC61850-9-2 and IEC60044-8 of Ethernet interface, IEC61850-9-2 and
The every 80 point sampling rate of cycle of IEC60044-8, the channel type and number of last opposed inlet are configured, the type of configuration, number
Mesh and electronic mutual inductor state consistency, to guarantee the accuracy of outgoing message after digital combining unit handles data.
In the step (1), each mouth carries out division region by function and is divided into cascade area, 256 memory blocks point SV, and FT3 is deposited
Storage area is synchronized to time zone.
In the step (2), the certain time is 0.5ms.
Combining unit device support simultaneously 80 collector sample rates of the every cycle of IEC61850-9-2 and IEC60044-8,
The input of IEC61850-9-2 and IEC60044-8 256 collector sample rate messages of every cycle, while supporting to export
The every 80 point sampling value message of cycle of IEC61850-9-2 and IEC60044-8 and IEC61850-9-2256 point IEC61850-9-2
Sampling value message.
It is compatible on combining unit device collector input interface hardware, it is only necessary to replace optical module i.e. and can be switched and is different types of
Collector input.
Compared with prior art, the beneficial effects obtained by the present invention are as follows being:
The present invention has digital output, digital output, and voltage switching, clock is synchronous, the functions such as voltage switching, can be square
Just access is various using IEC61850-9-2 specification or IEC60044-8 specification as the electronic mutual inductor of source, has very strong
Compatibility solves the problems, such as that " one-to-one " the customization compatibility of digital combining unit is not strong at present.
Detailed description of the invention
Fig. 1 is systematic schematic diagram of the invention.
Fig. 2 is flow chart of the invention.
Specific embodiment
The following examples are only intended to illustrate the technical solution of the present invention more clearly, and cannot be used as a limitation the limitation present invention
Protection scope.
Referring to Fig. 1 and Fig. 2, the number of compatible to IEC 61850-9-2 and IEC60044-8 the collector specification of the present embodiment is closed
And unit comprising for provide intake access open into module, DIO(input and output) module, for providing intelligent acess
The power module of working power is provided with the CPU module of signal-data processing and for each plug-in unit；The CPU module passes through
Grafting receives the message of IEC61850-9-2 acquisition standard and IEC60044-8 acquisition standard, and received packet parsing is handled
For unified format synchronization process.
The present embodiment uses unified platform technology, and all plug-in units are researched and developed using unified hardware platform, female
Plate is located at cabinet front, and all plug-in units use rear plug mode, presses modularized design convenient for plug-in unit.Device is specific on hardware
It is divided into CPU module, power module is opened into (DI) module, DIO() module.
CPU module is the core of device, main to provide intelligent acess and signal-data processing function, and plug-in unit has 2 tunnels grade
Join Ethernet interface (0,1 mouthful), 6 road electronic mutual inductor data access mouths (2-7 mouthfuls), all the way Ethernet debugging mouth (PPC mouthfuls) with
And clock synchronization signal port (SYNC) all the way.In addition, the functions such as dissection process of device docking receiving text are also completed on plug-in unit.
DI module provides traditional intake access, including maintenance, disconnecting link position etc. for device.
Power module provides working power for each plug-in unit of device, and alternating current-direct current is adaptive.DIO module provides for device
2 groups of tripping alarming nodes.
Clock synchronization synchronization is completed in the data interaction of FPGA and CPU, FT3 data receiver, FT3 data are sent, temporal interpolation is same
The work such as step, IEC61850-9-2 SV message receive, IEC61850-9-2 SV message is sent, GOOSE message forwarding.The present invention
Data compatibility method it is as follows:
1. couple FPGA(Field-Programmable Gate Array, i.e. field programmable gate array) buffer area into
Row expands, and is divided on memory by mouth, and each mouth is divided by function cascades area, 256 memory blocks point SV, the memory block FT3, together
Step is to time zone etc..
2. the data interaction of FPGA and CPU no longer uses interrupt mode, and is changed to CPU inquiry mode.CPU is every 0.5ms
Inquiry FPGA's sends and receivees buffer area BD.When CPU inquires reception buffering BD non-empty, it is responsible for reading to walk to specify delaying by CPU
It rushes area's data and BD non-empty is identified clear 0, other messages are no longer received if reception buffering is full up and are buffered until CPU will be received
The non-empty mark clear 0 of BD.The occupancy for sending buffering BD firstly the need of inquiry when CPU needs to send message identifies, if
Occupancy is identified as the 1 explanation transmission buffer data, and there are no transmissions to terminate, and CPU must not write data toward the buffer area, if
Occupancy, which is identified as the 0 explanation transmission buffer area, does not have a data to be sent, and CPU can write data toward the buffer area, after writing by
CPU, which will occupy mark and set 1, is sent data by FPGA.
3. pair configuration file carries out a type expansion, in configuration message type, distribution access port first, secondly define light with
The too type 9-2LE(SV electronic mutual inductor of network interface), 9-2(SV cascade), FT3(FT3 electronic mutual inductor), finally to access
Mouthful channel type and number configured, type and number must with electronic mutual inductor state consistency, it is digital to guarantee
Combining unit handles the accuracy of outgoing message after data.
A kind of number of the compatible to IEC 61850-9-2 collector specification and IEC60044-8 collector specification of the present embodiment
Combining unit has digital output, digital output, and voltage switching, clock is synchronous, and the functions such as voltage switching can easily connect
Enter it is various using IEC61850-9-2 specification or IEC60044-8 specification as the electronic mutual inductor of source, have very strong compatibility
Property.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (4)
1. the compatibility method of a kind of compatible to IEC 61850-9-2 and the conflation unit of IEC60044-8 collector specification,
It is characterized in that, conflation unit includes for providing opening into module, opening into module out, for providing optical fiber for intake access
It accesses the CPU module with signal-data processing and provides the power module of working power for each plug-in unit；The CPU module
IEC61850-9-2 is received by grafting and acquires the message that standard and IEC60044-8 acquire standard, and by received packet parsing
Processing is unified format synchronization process；Compatibility method includes the following: that (1) expands the buffer area of FPGA, is pressed on memory
Mouth carries out division region；(2) FPGA and CPU uses the data interaction of CPU inquiry mode, and CPU inquires FPGA at regular intervals
Send and receive buffer area BD, when CPU inquire reception buffering BD non-empty when, by CPU be responsible for read walk appointed buffer data
And BD non-empty is identified clear 0；Other messages are no longer received if reception buffering is full up until CPU will receive the non-empty of buffering BD
Identify clear 0；When CPU needs to send message, it is necessary first to which inquiry sends the mark of occupancy of buffering BD, if having occupied mark
It is 1, then there are no transmissions to terminate for the transmission buffer data, and CPU must not write data toward the buffer area；It is identified as if occupied
0, then the transmission buffer area does not have data to be sent, and CPU can write data toward the buffer area, will occupy mark by CPU after writing
Knowledge sets 1 and is sent data by FPGA；(3) type expansion is carried out to configuration file to distribute first in configuration message type
Access port, the every 256 point sampling rate of cycle of type IEC61850-9-2 and IEC60044-8 of next definition luminiferous ether network interface,
The every 80 point sampling rate of cycle of IEC61850-9-2 and IEC60044-8, the channel type and number of last opposed inlet are matched
It sets, type, number and the electronic mutual inductor state consistency of configuration, to guarantee output report after digital combining unit processing data
The accuracy of text.
2. compatibility method according to claim 1, which is characterized in that in the step (1), each mouth is drawn by function
Subregion is divided into cascade area, 256 memory blocks point SV, and the memory block FT3 is synchronized to time zone.
3. compatibility method according to claim 1, which is characterized in that in the step (2), the certain time is
0.5ms。
4. compatibility method according to claim 1, which is characterized in that the plug-in unit is equipped with 2 tunnels and cascades Ethernet interface, six
Road electronic mutual inductor data access mouth, all the way Ethernet debugging mouth and all the way clock synchronization signal port.
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| CN201610767469.7A CN106249660B (en) | 2016-08-30 | 2016-08-30 | The conflation unit and method of compatible to IEC 61850-9-2 and IEC60044-8 specification |
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| CN201610767469.7A CN106249660B (en) | 2016-08-30 | 2016-08-30 | The conflation unit and method of compatible to IEC 61850-9-2 and IEC60044-8 specification |
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| CN107300651A (en) * | 2017-07-24 | 2017-10-27 | 中国电力科学研究院 | A kind of digital quantity input type standard combining unit |
| CN114095797B (en) * | 2021-10-15 | 2024-06-18 | 南京南瑞继保电气有限公司 | Fault recording module and fault recording circuit |
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| CN103200280A (en) * | 2013-02-20 | 2013-07-10 | 中国电力科学研究院 | Process level interface device of intelligent substation |
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| CN102231568B (en) * | 2011-07-05 | 2014-01-29 | 国电南瑞科技股份有限公司 | Multifunctional intelligent data collecting device |
| WO2014188507A1 (en) * | 2013-05-21 | 2014-11-27 | 三菱電機株式会社 | Protection control system for process bus, merging unit, and computation device |
| JP2015070769A (en) * | 2013-09-30 | 2015-04-13 | 株式会社東芝 | Protection control system and merging unit |
| CN103995193B (en) * | 2014-04-30 | 2016-09-07 | 贵州电力试验研究院 | Digital transformer substation is stood electric energy quality on-line monitoring device entirely |
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| CN103200280A (en) * | 2013-02-20 | 2013-07-10 | 中国电力科学研究院 | Process level interface device of intelligent substation |
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