CN106249453A - A kind of low power source drive circuit - Google Patents
A kind of low power source drive circuit Download PDFInfo
- Publication number
- CN106249453A CN106249453A CN201610176426.1A CN201610176426A CN106249453A CN 106249453 A CN106249453 A CN 106249453A CN 201610176426 A CN201610176426 A CN 201610176426A CN 106249453 A CN106249453 A CN 106249453A
- Authority
- CN
- China
- Prior art keywords
- switch
- control signal
- current
- pull
- output stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A kind of low power source drive circuit comprises: one first output stage, one second output stage.First output stage is controlled to decide whether to produce the first pull-up current, and the second output stage is controlled to decide whether to produce the second pull-up current.When charging for the first time, the first output stage produces the first pull-up current, and the second output stage produces the second pull-up current, and load is charged by the some of first and second pull-up current as charging current；When second time charging, the second output stage does not produce the second pull-up current, but the first output stage produces the first pull-up current, and load is charged by the some of the first pull-up current as charging current.Design by the output stage of two-part, during second time charging, only by the first output stage to load charging, it is possible to effectively reduce charging current and reach the effect of power saving.
Description
Technical field
The present invention is a kind of source electrode drive circuit, particularly relates to a kind of low power source drive circuit.
Background technology
In recent years, along with the development of information technology, liquid crystal display owing to external form is frivolous, power consumption is low, radiationless pollution,
And can be compatible with semiconductor fabrication etc. advantage, be widely used in the industry such as computer system, mobile device.Liquid crystal display
Device is to utilize source driving chip and grid drive chip to drive the pixel on panel with show image, it is however generally that, source electrode
Driving chip consumes more power, and along with liquid crystal display resolution improves constantly, needs the source electrode of more and more to drive
Dynamic chip, and this conflicts mutually with energy-conservation target.
Refering to Fig. 1, Fig. 2 and Fig. 3, existing source driving chip utilizes AB class cmos amplifier as the circuit of output stage
Framework, Fig. 1 represents the operation that a load capacitance 100 is charged by the amplifier of source driving chip output stage, now when controlling letter
Number=1 (inverted control signal=0) when, switch conduction and phase-veversal switch be not turned on, pull-up (Pull up) electricity of amplifier
Stream as it is shown on figure 3, add the charging current flowing to load capacitance 100 for 4I.It addition, the amplifier that Fig. 2 represents output stage makes this
Operation when load capacitance 100 is discharged, when control signal=1 (inverted control signal=0) when, amplifier drop-down
(Pull down) electric current is as it is shown on figure 3, add the discharge current from this load capacitance 100 for 4I.And shown in Fig. 1 and Fig. 2
Charging and discharging operation in, when control signal=0 (inverted control signal=1) when, switch be not turned on and phase-veversal switch
Conducting, pull-up and the pull-down current of amplifier are 0, to reduce the effect of power consumption.Source electrode shown in Fig. 1 drives at present
Its low power consumption of output-stage circuit of dynamic chip has arrived at the bottleneck in design, therefore, the most effectively reduces single source
The power consumption of level driving chip, becomes as related researcher's problem to be broken through.
Summary of the invention
Therefore, the purpose of the present invention, it is to provide a kind of low power source drive circuit.
Low power source drive circuit of the present invention, electrical connection one load, and comprise one first output stage, and one second is defeated
Go out level.
First output stage is controlled to decide whether to produce one first pull-up current.
Second output stage is controlled to decide whether to produce one second pull-up current.
When charging for the first time, the first output stage produces the first pull-up current and the second output stage produces the second pull-up electricity
Flow, and load is charged as a charging current by the some of first and second pull-up current.
When second time charging, the second output stage does not produce the second pull-up current, and the first output stage produces the first pull-up
Electric current, and the some of the first pull-up current as this charging current to load charging.
Effect of the present invention is: low power source drive circuit designs by the output stage of two-part, fills for the first time
During electricity, first and second output stage is jointly to load charging, and when second time charging, is only filled load by this first output stage
Electricity, it is possible to effectively reduce charging current and reach the effect of power saving.
Accompanying drawing explanation
Other features of the present invention and effect, will clearly present, wherein in reference to graphic embodiment:
Fig. 1 is a block chart, and the operation that a load capacitance is charged by a kind of existing source electrode drive circuit is described；
Fig. 2 is a block chart, and the operation that a kind of existing source electrode drive circuit makes load capacitance discharge is described；
Fig. 3 is an oscillogram, the operation of the source electrode drive circuit shown in explanatory diagram 1 and Fig. 2；
Fig. 4 is a block chart, and the embodiment that a load capacitance is charged by low power source drive circuit of the present invention is described；
Fig. 5 is a block chart, and the embodiment that low power source drive circuit of the present invention makes load capacitance discharge is described；And
Fig. 6 is an oscillogram, the operation of the embodiment shown in explanatory diagram 4 and Fig. 5.
Reference numeral explanation
100 load capacitances
200 load capacitances
1 first output stage
11 first switch elements
111 first switches
112 second switches
113 first phase-veversal switches
114 second phase-veversal switches
12 first buffer cells
121 the first transistors
122 transistor secondses
2 second output stages
21 second switch unit
211 the 3rd switches
212 the 4th switches
213 the 3rd phase-veversal switches
214 the 4th phase-veversal switches
22 second buffer cells
221 third transistor
222 the 4th transistors
3 computing circuits
Vo ' output voltage
Detailed description of the invention
Refering to Fig. 4, low power source drive circuit of the present invention, electrical connection one load, and comprise one first output stage 1,
One second output stage 2, computing circuit 3 and a control circuit (figure does not marks).In the present embodiment, load is a load capacitance
200。
Control circuit (figure does not marks) produces one first control signal, one first inverted control signal, one second control letter
Number and one second inverted control signal, the reverse-phase of this first control signal in the phase place of this first inverted control signal, should
The reverse-phase of the second control signal is in the phase place of this second inverted control signal.
This computing circuit 3 receives one first working bias voltage and one second working bias voltage, and produces one first enable voltage
And one second enable voltage.Second working bias voltage is a ground voltage.The current potential of the first working bias voltage is more than this first enable voltage
A current potential at least critical voltage (threshold voltage), first enable voltage current potential more than second enable voltage, should
Second enables the current potential of voltage more than a second working bias voltage at least critical voltage.This computing circuit 3 can be according to liquid crystal display
Update a subframe every a scheduled time, and update first and second and enable voltage once, make this low power source drive electricity
Road enables voltage according to first and second received, and drives load capacitance 200 to be in charging operations or discharge operation.Citing
For, the picture update rate (frame rate) of liquid crystal display is one second display 60 frame picture, namely at interval of 60 points
One of second when showing a picture, then this computing circuit 3 updates once first and second at interval of the sixtieth second and enables voltage,
This low power source drive circuit drives load capacitance 200 the most accordingly, and making load capacitance 200 should be black, white or chess because of picture
Dish lattice etc., and it is in charging operations or discharge operation.
First output stage 1 is controlled to decide whether that producing one first pull-up (Pull up) electric current fills load capacitance 200
Electricity, and draw high the voltage of this load capacitance 200, and include one first switch element 11, and one first buffer cell 12.
First switch element 11 is controlled to be enabled or the first charging control signal of non-enable with output one instruction.In this example
In, the first switch element 11 includes one first switch 111, one second switch 112,1 first phase-veversal switch 113, and one second is anti-
Switch 114 mutually.
First switch 111 has one and enables the first end of voltage, the second end for receiving the first of this computing circuit 3, and
One for receiving the control end of the first control signal, and the first switch 111 in conducting and is not turned on two according to the first control signal
Switch between the state of kind.Such as, when the first control signal is logic 1, the first switch 111 conducting；When the second control signal is for patrolling
When collecting 0, the first switch 111 is not turned on.
Second switch 112 has one and enables the first end of voltage, the second end for receiving the second of this computing circuit 3, and
One for receiving the control end of this first control signal, and second switch 112 is turning on according to the first control signal and is being not turned on
Switch between two states.Such as, when the first control signal is logic 1, second switch 112 turns on；When this second control signal
During for logical zero, second switch 112 is not turned on.
First phase-veversal switch 113 has one for receiving the first end of the first working bias voltage, opening for electrical connection first
Close the second end of second end of 111, and one is used for receiving the control end of the first inverted control signal, and the first phase-veversal switch 113
In conducting and switching it is not turned between two states according to the first inverted control signal.It should be noted that when the first control signal is
During logic 1, the first inverted control signal is logical zero, and the first phase-veversal switch 113 is not turned on；When the first control signal is logical zero
Time, the first inverted control signal is logic 1, and the first phase-veversal switch 113 turns on.
Second phase-veversal switch 114 has one for receiving the first end of the second working bias voltage, opening for electrical connection second
Close the second end of second end of 112, and one is used for receiving the control end of the first inverted control signal, and the second phase-veversal switch 114
In conducting and switching it is not turned between two states according to the first inverted control signal.Such as, when the first inverted control signal is for patrolling
Collecting 0, the second phase-veversal switch 114 is not turned on；When the first inverted control signal is logic 1, and the second phase-veversal switch 114 turns on.
Therefore, when the first switch 111 and second switch 112 turn on, the first phase-veversal switch 113 and the second phase-veversal switch
114 are not turned on, now, by second end output the first enable voltage of the first switch 111, and by the second end of second switch 112
Output the second enable voltage, to form the first charging control signal that instruction enables.And when the first phase-veversal switch 113 and second is anti-
Mutually during switch 114 conducting, the first switch 111 and second switch 112 are not turned on, now, by the second end of the first phase-veversal switch 113
Export the first working bias voltage, the second end of the second phase-veversal switch 114 export the second working bias voltage, to form the non-enable of this instruction
The first charging control signal.
Between the first buffer cell 12 electrical connected load electric capacity 200 and the first switch element 11, the first buffer cell 12
Enable non-enable or non-enable according to the first charging control signal instruction and produce accordingly or do not produce the first pull-up current.
In this example, the first buffer cell 12 includes a first transistor 121, and a transistor seconds 122.Hereinafter first is illustrated one by one
The each thin parts of buffer cell 12.
The first transistor 121 has an electrical connection first to switch the second end and second end of the first phase-veversal switch 113 of 111
Control end, one for receiving the first end of the first working bias voltage, and the second end of an electrical connected load electric capacity 200.At this
In embodiment, the first transistor 121 is a P-type mos field-effect transistor (hereinafter referred to as PMOS), and this control
End processed be its grid, the first end be its source electrode, the second end be its drain electrode.
Transistor seconds 122 has second end and the second of the second phase-veversal switch 114 of an electrical connection second switch 112
End control end, one for receive the second working bias voltage the first end, and one electrical connection load capacitance 200 the second end.At this
In embodiment, transistor seconds 122 is a N-type metal oxide semiconductcor field effect transistor (hereinafter referred to as NMOS), and controls
End be its grid, the first end be its source electrode, the second end be its drain electrode.
When the end that controls of the first transistor 121 receives the first enable voltage from the first switch 111, and when the second crystal
When controlling the second enable voltage that end receives from second switch 112 of pipe 122, by the second end output of the first transistor 121
First pull-up current.And when the end that controls of the first transistor 121 receives the first working bias voltage from the first switch 111, and work as
When controlling the second working bias voltage that end receives from second switch 112 of transistor seconds 122, the second of the first transistor 121
End does not the most export the first pull-up current.
Second output stage 2 is controlled to decide whether that producing one second pull-up current charges to load capacitance 200, and includes
One second switch unit 21, and one second buffer cell 22.
Second switch unit 21 is controlled to be enabled or the second charging control signal of non-enable with output one instruction.In this example
In, second switch unit 21 includes one the 3rd switch 211, the 4th switch 212,1 the 3rd phase-veversal switch 213, and one the 4th is anti-
Switch 214 mutually.The each thin parts of second switch unit 21 is below described one by one.
3rd switch 211 has the second end of this first switch 111 of an electrical connection to receive the first of the first enable voltage
End, one second end, and one for receiving the control end of the second control signal, and the 3rd switch 211 exists according to the second control signal
Turn on and be not turned between two states switching.Such as, when the second control signal is logic 1, the 3rd switch 211 conducting；When
When two control signals are logical zero, the 3rd switch 211 is not turned on.
4th switch 212 have the second end of an electrical connection second switch 112 with receive the second enable voltage the first end,
Second end, and one for receive the second control signal control end, and the 4th switch 212 according to this second control signal conducting
And it is not turned between two states switching.Such as, when the second control signal is logic 1, the 4th switch 212 conducting；When the second control
When signal processed is logical zero, the 4th switch 212 is not turned on.
3rd phase-veversal switch 213 has one for receiving the first end of the first working bias voltage, one the 3rd opening for electrical connection
Close the second end of second end of 212, and one is used for receiving the control end of the second inverted control signal, and the 3rd phase-veversal switch 213
In conducting and switching it is not turned between two states according to the second inverted control signal.It should be noted that when the second control signal is
During logic 1, the second inverted control signal is logical zero, and the 3rd phase-veversal switch 213 is not turned on；When the second control signal is logical zero
Time, the second inverted control signal is logic 1, and the 3rd phase-veversal switch 213 turns on.
4th phase-veversal switch 214 has one for receiving the first end of this second working bias voltage, one for being electrically connected
Second end of the second end of the 4th switch 212, and one for receiving the control end of the second inverted control signal, and the 4th anti-phase open
Close 214 and in conducting and be not turned between two states switching according to the second inverted control signal.Such as, when the second inverted control signal
For logical zero, the 4th phase-veversal switch 214 is not turned on；When the second inverted control signal is logic 1, and the 4th phase-veversal switch 214 turns on.
Therefore, when the 3rd switch 211 and the 4th switch 212 conducting, the 3rd phase-veversal switch 213 and the 4th phase-veversal switch
214 are not turned on, now, by second end output the first enable voltage of the 3rd switch 211, and by the second end of the 4th switch 212
Output the second enable voltage, to form the second charging control signal that instruction enables.And when the 3rd phase-veversal switch 213 and the 4th is anti-
Mutually during switch 214 conducting, the 3rd switch 211 and the 4th switch 212 are not turned on, now, by the second end of the 3rd phase-veversal switch 213
Export the first working bias voltage, the second end of the 4th phase-veversal switch 214 export the second working bias voltage, indicate non-enable to be formed
Second charging control signal.
Between the second buffer cell 22 electrical connected load electric capacity 200 and second switch unit 21, the second buffer cell 22
Produce accordingly according to the second charging control signal instruction enable or non-enable or do not produce the second pull-up current.In this example,
Second buffer cell 22 includes a third transistor 221, and one the 4th transistor 222.Second buffer cell is below described one by one
The each thin parts of 22.
Third transistor 221 has second end and the second of the 3rd phase-veversal switch 213 of electrical connection the 3rd switch 211
End control end, one for receiving the first end of the first working bias voltage, and the second end of an electrical connected load electric capacity 200.
4th transistor 222 has second end and the second of the 4th phase-veversal switch 214 of electrical connection the 4th switch 212
End control end, one for receiving the first end of the second working bias voltage, and the second end of an electrical connected load electric capacity 200.
When the end that controls of third transistor 221 receives the first enable voltage from the 3rd switch 211, and when the 4th crystal
When controlling the second enable voltage that end receives from the 4th switch 212 of pipe 222, by the second end output of third transistor 221
Second pull-up current.And when the end that controls of third transistor 221 receives the first working bias voltage from the 3rd switch 211, and work as
The end that controls of the 4th transistor 222 receives the second working bias voltage from the 4th switch 212, and the second of third transistor 221
End does not the most export the second pull-up current.
Refering to Fig. 4 and coordinate Fig. 6, in the present embodiment, it is in instantaneous charging behaviour when being relevant to load capacitance 200 one
During the first charge period made, the second charging that output controlled with second switch unit 21 instruction of the first switch element 11 enables
Control signal, so that the first output stage 1 produces the first pull-up current and the second output stage 2 produces the second pull-up current, wherein
A first pull-up current part flows to load capacitance 200, and a part flows to transistor seconds 122, and the second pull-up current is a part of
Flowing to load capacitance 200, a part flows to the 4th transistor 222, and in first and second pull-up current, common flow direction loads electricity
Load capacitance 200 is i.e. charged by the part holding 200 as a charging current.And when load capacitance 200 is in the charging behaviour of stable state
During the second charge period made, the controlled output of second switch unit 21 indicates the second charging control signal of non-enable, makes the
Two output stages 2 do not produce the second pull-up current, and the first output stage 1 produces the first pull-up current, and the one of the first pull-up current
Load capacitance 200 is charged by part as charging current, and some flows to transistor seconds 122.
Concrete implementation mode and associated component working method are further described below: when at the first charge period, the
One control signal is logic 1 (the first inverted control signal is logical zero), and the second control signal is that logic 1 (believe by the second anti-phase control
Number it is logical zero), now, the first switch 111 of the first switch element 11 and second switch 112 all turn on (the first phase-veversal switch
113 and second phase-veversal switch 114 be all not turned on), and the 3rd switch 211 of second switch unit 21 and the 4th switch 212 all lead
Logical (the 3rd phase-veversal switch 213 and the 4th phase-veversal switch 214 are all not turned on), now, the control end of the first transistor 121 is received
Being the first enable voltage, the control end of transistor seconds 122 is received as the second enable voltage, the control of third transistor 221
End is received as the first enable voltage, and the control end of the 4th transistor 222 is received as this second enable voltage.
So, at the first charge period, the first transistor 121, transistor seconds 122, third transistor 221 and the 4th are brilliant
Body pipe 222 is all enabled, and wherein, the first end of the first transistor 121 produces the first pull-up current and accordingly via the first crystalline substance
Second end output of body pipe 121, some flows to load capacitance 200 as charging current, and another part flows to transistor seconds
Second end of 122.First end of third transistor 221 produces the second pull-up current and accordingly via third transistor 221
Second end output, a part of flows to load capacitance 200 as charging current, and another part flows to the as one second pull-down current
Second end of four transistors 222.Therefore, as shown in Figure 6, precipitous and need rapid electric current at load capacitance 200 charging ramp
First charge period, the first output stage 1 and the second output stage 2 export of the first pull-up current and the second pull-up current respectively
Part load capacitance 200 is charged as charging current simultaneously, and 4I be first and second output stage 1,2 flowed to NMOS by PMOS
Current value sum, and the current value being flowed to NMOS by PMOS that I is the only first output stage 1.
When at the second charge period, the first control signal is logic 1 (the first inverted control signal is logical zero), second
Control signal is logical zero (the second inverted control signal is logic 1), now, and the first switch 111 and the of the first switch element 11
The all conductings (the first phase-veversal switch 113 and the second phase-veversal switch 114 are all not turned on) of two switches 112, and second switch unit 21
3rd phase-veversal switch 213 and the 4th phase-veversal switch 214 all turn on (the 3rd switch 211 and the 4th switch 212 are all not turned on), this
Time, the control end of the first transistor 121 is received as the first enable voltage, and the control end of transistor seconds 122 is received as
Two enable voltage, and the control end of third transistor 221 is received as the first working bias voltage, and the control end of the 4th transistor 222
It is received as the second working bias voltage.So, at the second charge period, only the first transistor 121 is made with transistor seconds 122
Can, third transistor 221 and the 4th transistor 222 are all by non-enable, therefore, relax at load capacitance 200 charging ramp and reach
To the second charge period of stable state charging, the second output stage 2 is closed, and load capacitance 200 is charged by the only first output stage 1,
And thereby reach the effect of power saving.
Further, low power source drive circuit of the present invention can be by the first transistor 121 controlling the first output stage 1
Relative to the first number of parallel ratio of transistor seconds 122, less than the third transistor 221 of the second output stage 2 relative to the 4th
Second number of parallel ratio of transistor 222, controls when the second charge period further, the first pull-up current and the second pull-up electricity
Stream accounts for total ratio exporting electric current of the first output stage 1 and the second output stage 2 respectively.For example, in parallel by design first
Number ratio is 2: 1, and when the second number of parallel ratio is 6: 3, the first pull-up current can be made to account for the first output stage 1 and the second output
The total of level 2 exports about 1/4th of electric current, and the second pull-up current accounts for about 3/4ths, the most as shown in Figure 6, second
Charge period, the only first output stage 11 produces the first pull-up current, is the most only left the current drain of about 1/4th, the most just
Being to say, the driving force of source electrode drive circuit only needs 25%, in such manner, it is possible to the electric current being effectively reduced source electrode drive circuit exceedes
50%.
Refering to Fig. 5 and coordinate Fig. 6, additionally it is noted that when being in the of instantaneous discharge operation in load capacitance 200
During one electric discharge period, the first output stage 1 produce the first drop-down (Pull down) electric current and the second output stage 2 to produce second drop-down
Electric current, wherein a first pull-down current part is from the first transistor 121, and another is partly from load capacitance 200, and second time
Drawing an electric current part from third transistor 221, another is partly from load capacitance 200, and in first and second pull-down current
Part from load capacitance 200 is the discharge current of load capacitance 200 jointly.And when load capacitance 200 is in stable state
Discharge operation second electric discharge the period time, the second output stage 2 does not produce the second pull-down current, and the first output stage 1 produces first
Pull-down current, and the some of the first pull-down current is from the first transistor 121, another part is from load capacitance 200
Discharge current.Therefore, when in the first electric discharge period, the logical value of the first control signal is 1, the logical value of the second control signal
Being 0, the first switch element 11 of the first output stage 1 is all enabled with the second switch unit 21 of the second output stage 2, the first output
Some makes load electricity as discharge current respectively for first pull-down current of level 1 and the second pull-down current of the second output stage 2
Hold 200 electric discharges, and the current value totalling being flowed to NMOS by PMOS that 4I is first and second output stage 1,2.When in the second electric discharge
During the period, the second switch unit 21 of the second output stage 2 is not produced the second pull-down current by non-enable, and the first output stage 1
Produce the first pull-down current, and I i.e. represents the current value being flowed to NMOS by PMOS of the only first output stage 1.Therefore, such as Fig. 6
Shown in, discharge the period second, only about account for total electricity exporting electric current 1/4th of the first output stage 1 and the second output stage 2
Stream consumes, say, that the driving force of source electrode drive circuit the most only needs 25%, in such manner, it is possible to be effectively reduced source drive electricity
The electric current on road is more than 50%.
In sum, low power source drive circuit of the present invention, designs by the output stage of two-part, fills (putting) in first
During the electricity period, load capacitance 200 is filled (putting) electricity by the first output stage 1 and the second output stage 2 jointly, and when second fills (putting) electricity
Duan Shi, is only filled (putting) electricity by the first output stage 1, it is possible to effectively reduce the first output stage 1 and the second output stage to load capacitance 200
The driving force of 2 and reach the effect of power saving, therefore really can reach the purpose of the present invention.
The above, only embodiments of the invention, it is impossible to limit the scope that the present invention implements with this, every according to this
The simple equivalence that patent application the scope of the claims and patent specification content are made changes and modifies, and the most still belongs to patent of the present invention
Covering scope.
Claims (10)
1. a low power source drive circuit, electrical connection one load, and comprise:
One first output stage, controlled to decide whether to produce one first pull-up current；And
One second output stage, controlled to decide whether to produce one second pull-up current；
When at the first charge period, the first output stage produces the first pull-up current and the second output stage produces the second pull-up electricity
Flow, and load is charged as a charging current by the some of first and second pull-up current；
When at the second charge period, the second output stage does not produce the second pull-up current, and the first output stage produces the first pull-up
Electric current, and the some of the first pull-up current as charging current to load charging.
2. low power source drive circuit as claimed in claim 1, wherein, the first output stage includes
One first switch element, controlled with output one instruction enable or the first charging control signal of non-enable, and
One first buffer cell, between electrical connected load and the first switch element, the first buffer cell controls according to the first charging
Signal designation enable or non-enable and produce accordingly or do not produce the first pull-up current.
3. low power source drive circuit as claimed in claim 2, wherein, the first switch element of the first output stage includes:
One first switch, has one to enable the first end of voltage, the second end for receiving first, and one is used for receiving the first control letter
Number control end, and according to the first control signal conducting and between being not turned between switch, and
One second switch, has one for receiving second and enables the first end of voltage, the second end, and one controls for receiving first
The control end of signal, and according to the first control signal conducting and between being not turned between switch；
When first and second switch conduction, by second end output the first enable voltage of the first switch, and the second of second switch
End output the second enable voltage, to form the first charging control signal that instruction enables.
4. low power source drive circuit as claimed in claim 3, wherein, this first switch element of the first output stage also wraps
Include:
One first phase-veversal switch, have one for receive the first end of the first working bias voltage, one for electrical connection first switch
Second end of the second end, and one for receiving the control end of the first inverted control signal, and exists according to the first inverted control signal
Switch between turning on and being not turned on, and
One second phase-veversal switch, has one for receiving the first end of the second working bias voltage, one for being electrically connected second switch
Second end of the second end, and one for receiving the control end of the first inverted control signal, and exists according to the first inverted control signal
Switch between turning on and being not turned on；
When first and second phase-veversal switch turns on, and exported the first working bias voltage by the second end of the first phase-veversal switch, by
Second end of two phase-veversal switches exports the second working bias voltage, to form the first charging control signal indicating non-enable；
Wherein, the phase place of the first inverted control signal and the opposite in phase of the first control signal.
5. low power source drive circuit as claimed in claim 4, wherein, the first buffer cell of the first output stage includes:
One the first transistor, has the second end of electrical connection first switch and the control of the second end of the first phase-veversal switch
End, one for receive the first working bias voltage the first end, and one electrical connection load the second end, and
One transistor seconds, has the second end of an electrical connection second switch and the control of the second end of the second phase-veversal switch
End, one for receive the second working bias voltage the first end, and one electrical connection load the second end；
When the end that controls of the first transistor receives the first enable voltage from the first switch, and when the control end of transistor seconds
When receiving the second enable voltage from second switch, the second end of the first transistor export the first pull-up current；
When the end that controls of the first transistor receives the first working bias voltage from the first switch, and when the control end of transistor seconds
When receiving the second working bias voltage from second switch, the second end of the first transistor does not the most export the first pull-up current.
6. low power source drive circuit as claimed in claim 1, wherein, the second output stage includes
One second switch unit, controlled with output one instruction enable or the second charging control signal of non-enable, and
One second buffer cell, between electrical connected load and second switch unit, the second buffer cell controls according to the second charging
Signal designation enable or non-enable and produce accordingly or do not produce the second pull-up current；
When at the first charge period, the second charging control signal that the controlled output instruction of second switch unit enables；
When at the second charge period, the controlled output of second switch unit indicates the second charging control signal of non-enable.
7. low power source drive circuit as claimed in claim 6, wherein, the second switch unit of the second output stage includes:
One the 3rd switch, one for receiving the first enable the first end of voltage, the second end, and one is used for receiving the second control signal
Control end, and according to the second control signal conducting and between being not turned between switch, and
One the 4th switch, one for receiving the second enable the first end of voltage, the second end, and one is used for receiving the second control signal
Control end, and according to the second control signal conducting and between being not turned between switch；
When at the first charge period, the 3rd and the 4th switch conduction, by second end output the first enable voltage of the 3rd switch,
And by second end output the second enable voltage of the 4th switch, to form the second charging control signal that instruction enables.
8. low power source drive circuit as claimed in claim 7, wherein, the second switch unit of the second output stage also wraps
Include:
One the 3rd phase-veversal switch, one for receiving the first end of the first working bias voltage, one for the of electrical connection the 3rd switch
Second end of two ends, and one for receiving the control end of the second inverted control signal, and is leading according to the second inverted control signal
Switch between leading to and being not turned on, and
One the 4th phase-veversal switch, one for receiving the first end of the second working bias voltage, one for the of electrical connection the 4th switch
Second end of two ends, and one for receiving the control end of the second inverted control signal, and is leading according to the second inverted control signal
Switch between leading to and being not turned on；
When at the second charge period, the 3rd and the 4th phase-veversal switch conducting, by the second end output first of the 3rd phase-veversal switch
Working bias voltage, and exported the second working bias voltage by the second end of the 4th phase-veversal switch, to form the second charging indicating non-enable
Control signal；
Wherein, the phase place of the second inverted control signal and the opposite in phase of the second control signal.
9. low power source drive circuit as claimed in claim 8, wherein, the second buffer cell of the second output stage includes:
One third transistor, one electrical connection the 3rd switch the second end and the control end of the second end of the 3rd phase-veversal switch, one
For receiving the first end of the first working bias voltage, and the second end of this load of electrical connection, and
One the 4th transistor, one electrical connection the 4th switch the second end and the control end of the second end of the 4th phase-veversal switch, one
For receiving the first end of the second working bias voltage, and the second end of an electrical connection load；
When at the first charge period, third transistor control end receive from the 3rd switch first enable voltage, the 4th
The end that controls of transistor receives the second enable voltage from the 4th switch, and by the second end output second of third transistor
Draw electric current；
When at the second charge period, third transistor control end receive from the 3rd switch the first working bias voltage, the 4th
The end that controls of transistor receives the second working bias voltage from the 4th switch, and the second end of third transistor does not the most export second
Pull-up current.
10. low power source drive circuit as claimed in claim 1, wherein, the first output stage is the most controlled to decide whether
Producing one first pull-down current, the second output stage is the most controlled to decide whether one second pull-down current；
When in one first electric discharge period, the first output stage produces the first pull-down current and the second output stage produces the second drop-down electricity
Flow, and the some of first and second pull-down current makes this load discharge as a discharge current；
When in the second electric discharge period, the second output stage does not produce the second pull-down current, and the first output stage to produce first drop-down
Electric current, and the some of the first pull-down current makes load discharge as discharge current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610176426.1A CN106249453B (en) | 2016-03-25 | 2016-03-25 | Low-power source electrode driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610176426.1A CN106249453B (en) | 2016-03-25 | 2016-03-25 | Low-power source electrode driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106249453A true CN106249453A (en) | 2016-12-21 |
| CN106249453B CN106249453B (en) | 2023-08-15 |
Family
ID=57626940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610176426.1A Active CN106249453B (en) | 2016-03-25 | 2016-03-25 | Low-power source electrode driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106249453B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5537060A (en) * | 1994-10-13 | 1996-07-16 | Goldstar Electron Co., Ltd. | Output buffer circuit for memory device |
| CN101727861A (en) * | 2008-10-27 | 2010-06-09 | 奇景光电股份有限公司 | Source driving circuit with output buffer |
| CN101996552A (en) * | 2009-08-05 | 2011-03-30 | 奇景光电股份有限公司 | Output buffering circuit, amplifier device and display device |
| US20130088473A1 (en) * | 2011-10-07 | 2013-04-11 | Renesas Electronics Corporation | Output circuit, data driver, and display device |
| KR20130121389A (en) * | 2012-04-27 | 2013-11-06 | 엘지디스플레이 주식회사 | Display device |
| CN206057737U (en) * | 2016-03-25 | 2017-03-29 | 北京集创北方科技股份有限公司 | A kind of low power source drive circuit |
-
2016
- 2016-03-25 CN CN201610176426.1A patent/CN106249453B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5537060A (en) * | 1994-10-13 | 1996-07-16 | Goldstar Electron Co., Ltd. | Output buffer circuit for memory device |
| CN101727861A (en) * | 2008-10-27 | 2010-06-09 | 奇景光电股份有限公司 | Source driving circuit with output buffer |
| CN101996552A (en) * | 2009-08-05 | 2011-03-30 | 奇景光电股份有限公司 | Output buffering circuit, amplifier device and display device |
| US20130088473A1 (en) * | 2011-10-07 | 2013-04-11 | Renesas Electronics Corporation | Output circuit, data driver, and display device |
| KR20130121389A (en) * | 2012-04-27 | 2013-11-06 | 엘지디스플레이 주식회사 | Display device |
| CN206057737U (en) * | 2016-03-25 | 2017-03-29 | 北京集创北方科技股份有限公司 | A kind of low power source drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106249453B (en) | 2023-08-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103258495B (en) | Shifting deposit unit, shift register and display device | |
| KR101944640B1 (en) | Gate electrode drive circuit based on igzo process | |
| KR101944641B1 (en) | Gate electrode drive circuit based on igzo process | |
| CN103440839B (en) | Shifting deposit unit, shift register and display device | |
| CN108231030A (en) | Discharge circuit, charging method and display device | |
| CN104766575A (en) | GOA circuit and liquid crystal display | |
| EA034004B1 (en) | Forward and reverse scanning-type goa circuit | |
| CN110149111A (en) | A kind of bootstrap switch circuit and its control method | |
| CN104409055A (en) | Scanning driving circuit for oxide semiconductor thin film transistor | |
| CN103093825A (en) | Shifting register and alloy substrate electrode driving device | |
| CN106683607B (en) | A kind of shift register, gate driving circuit and display panel | |
| CN105427786A (en) | Gate driving circuit unit and gate driving circuit | |
| CN105869562A (en) | Shifting register, grid drive circuit and display panel | |
| CN108447514A (en) | Semiconductor memory, suspend mode stationary state logic circuit and its suspend mode stationary state method | |
| CN103715870B (en) | Voltage adjuster and resonant gate driver thereof | |
| CN109616041A (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN105741740B (en) | GOA unit and its driving method, GOA circuit, display device | |
| CN100553144C (en) | Shift buffer memory driving circuit and level shifter thereof | |
| CN106652869A (en) | Control circuit for display panel, driving method and display device | |
| CN101807436B (en) | Shift register | |
| CN206057737U (en) | A kind of low power source drive circuit | |
| CN207781206U (en) | Suspend mode stationary state logic circuit, semiconductor memory | |
| US9543954B2 (en) | Driver circuit with device variation compensation and operation method thereof | |
| CN106249453A (en) | A kind of low power source drive circuit | |
| CN106297726A (en) | Sampling hold circuit, discharge control method and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |