CN106206296A - A kind of integrated approach of the nanowire biosensor of vertical-channel - Google Patents
A kind of integrated approach of the nanowire biosensor of vertical-channel Download PDFInfo
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Abstract
The present invention provides the integrated approach of a kind of vertical-channel nanowire biosensor, belongs to technical field of manufacturing semiconductors.The method combines etching through hole, epi channels, the false gate layer of isotropism removal to realize the integrated of the nanowire biosensor of vertical-channel.The present invention is compared with traditional horizontal channel structure, and when biomolecule carries out Brownian movement in the solution, all directions to nanowire channel surface all produce random collision, finally produce higher modification density in nanowire surface.And present invention, avoiding the etching injury during raceway groove in existing method is formed, improve the performance of device；And ditch length can be foreshortened to below 10nm, meet the modification requirement to single protein or nucleic acid molecules.The present invention is mutually compatible with traditional integrated circuit manufacturing technology, and technique is simple, cost price is little.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, relate to that one combines etching through hole, epi channels, isotropism are gone
Except false gate layer is to realize the integrated approach of the nanowire biosensor of vertical-channel.
Background technology
Integrated circuit from invention since, by constantly reducing its characteristic size, can other micro mechanical system elements integrated,
Chip performance can be effectively improved.And in recent years, micro & nano technology causes academia and industrial quarters with the combination of biotechnology
Extensive concern.This microbiosensor be a kind of using biological activity unit (such as enzyme, antibody, nucleic acid, cell etc.) as
Sensitive primitive, is converted into the signal of telecommunication by bio information, the element being monitored the bio signal in environment with realization.Nano wire
Have the highest surface-to-volume ratio, meet the bio-sensing requirement for sensitivity, be accordingly regarded as most having development potentiality
One of biosensor part.During owing to carrying out bio-sensing, solution to be measured can be titrated in modifying window, by by solution
Biomolecule modify at channel surface and then regulation and control groove potential, solution is now equivalent to exercise the merit of grid in transistor
Can, it being commonly referred to as liquid grid, it is long that corresponding raceway groove modification length is known as liquid grid, and the channel region of solution impregnation is referred to as liquid grid region
Territory.
The research group of Harvard University Yi Cui et al. has prepared nano wire by bottom-up method, and utilizes silicon
The high sensitivity of nano-wire devices successfully have detected the change of pH value.But, this by catalyst chemical growth formed
The direction that nano wire is the most unified, it is impossible to realize the precise positioning of device, the most also with traditional ic manufacturing technology the most not
Compatible.Other research group report, can examine protein and nucleic acid by this conductance sensitivity characteristic of nano wire simultaneously
Survey, but owing to being all the nano-wire devices in horizontal channel direction, channel laterally causes the big portion of jewelry to be repaired in volumetric soiutions
Divide and only concentrate on raceway groove upper surface and trench sidewalls, the biomolecule shortcoming of raceway groove lower surface, the sensing signal of telecommunication therefore obtained
Intensity is not enough.
Summary of the invention
For problem above, the present invention provides a kind of combination etching through hole, epi channels, isotropism to remove false gate layer
The integrated approach of vertical-channel nanowire biosensor, to improve existing known technology.Comprise the steps:
A. semi-conductive substrate is provided, it is achieved device isolation；
B. heavily doped " lower active area " is formed；
C. the false gate stack of deposit；
Implement step as follows:
C1. one layer of medium of deposit makees " SDE mask layer 1 ", and its thickness defines the width of the lower active area side wall of device；
C2. one layer of medium of deposit makees " false gate layer ", and its thickness defines the raceway groove of device and modifies length (liquid grid length)；
C3. one layer of medium of deposit makees " SDE mask layer 2 ", and its thickness defines the width of the upper active area side wall of device；
Wherein, SDE mask layer 1 is identical with the material of SDE mask layer 2, different with false gate layer material.And require false gate layer
Material the isotropic etching of SDE mask layer 1 is selected ratio more than 5:1, to ensure to be removed by isotropic etching in F4
SDE mask layer 1 and SDE mask layer 2 is not damaged during false gate layer；
D. vertical channel structure is formed by etching through hole, epi channels；
Implement step as follows:
D1. by the shape of lithographic definition channels cross-section, size；
D2. forming raceway groove window by anisotropic etching, bottom of window exposes active area under the heavy doping of device, goes
Glue；
D3. the raceway groove of device is formed by graphical epitaxy technology；
D4. the deposit channel material beyond SDE mask layer 2 upper surface is removed by chemically mechanical polishing, it is achieved planarization；
E. the heavy doping " upper active area " of device is formed by deposit, etching；
Implement step as follows:
E1. one layer of active material of deposit；
E2. by the upper active area window of photoetching technique definition；
E3. form upper active area by anisotropic etching, remove photoresist；
E4. by ion implantation technique, upper active area is carried out heavy doping；
E5. source, leakage are activated by annealing process；
F. remove false grid material, form nanowire channel modified regions (i.e. liquid gate region)；
Implement step as follows:
F1. one layer of medium of deposit makees top mask layer；
F2. by lithographic definition liquid gate region；
F3. by anisotropic etching, expose the upper surface of SDE mask layer 1, remove photoresist；
F4. by isotropic etching, whole false gate layer is removed；
Wherein, top mask material described in F1 is different from false gate layer, and requires that this top is covered by false gate layer material
The isotropic etching of film layer selects ratio more than 5:1, does not damages during to ensure and to remove false gate layer by isotropic etching in F4
Hinder this top mask layer；
G. the metal contact at device source and drain two ends is formed；
Implement step as follows:
G1. top mask layer is removed；
G2. medium between anisotropy deposit from level to level, carries out chemical-mechanical planarization；
G3. formed the contact hole at device source and drain two ends by photoetching, anisotropic etching, remove photoresist；
G4. filler metal Metal 0 in each contact hole；
G5. by metal Metal 0 being carried out chemical-mechanical planarization, the metal of the upper surface beyond inter-level dielectric is removed
Metal
0, it is achieved the conductive layers apart between device；
H. metal interconnection pattern is formed；
Implement step as follows:
H1. deposit metal Metal 1；
H2. formed extraction and the probe test pad at source and drain two ends by photoetching, anisotropic etching, remove photoresist；
I. the modification window of solution titration is formed；
I1. one layer of medium of deposit is as passivation layer, and carries out chemical-mechanical planarization；
I2. modifying window by lithographic definition, when solution titrates, biomolecule to be finished is spread by this window
Through liquid gate layer, then the surface bonding diffusing to nano wire is modified；
I3. by anisotropic etching, window and liquid gate layer are modified in connection, are formed and repair to nanowire channel from substrate surface
The path on decorations surface, removes photoresist；
J. probe test window is formed；
Implement step as follows:
J1. lithographic definition probe test window；
J2. by anisotropic etching, expose probe test pad defined in interconnection metal Metal 1, remove photoresist；
K. alloy, makes metal present more preferable ohm property with the contact position of source and drain, makes dielectric material finer and close simultaneously.
When carrying out the sensor measuring of biomolecule, the solution with biomolecule and cross-linking agent is titrated and is modifying window
In, source probe and drain terminal probe are pricked on two pad corresponding in probe test window respectively, when the biology to be measured in solution
Molecule, under the effect of cross-linking agent, can modify the surface in nanowire channel, forms covalent bond, causes the electromotive force of nanowire channel
Changing, thus cause electric current to change, curent change waveform can reach probe from source and drain by metal interconnection, bio information amount thus
It is changed to electrical information amount, realizes the sensing of biomolecule with this.
Further, heretofore described structural parameters are (such as " upper active area " and the thickness of " lower active area " and adulterate dense
Degree, " SDE mask layer 1 ", " SDE mask layer 2 ", the thickness etc. of " false gate layer ") all set according to concrete device performance requirements.
Further, Semiconductor substrate described in step A, including body silicon substrate, SOI substrate, body germanium substrate, GOI substrate
Deng.
Further, described in step A isolate, for body substrate (body silicon, body germanium etc.), can use trap isolation add shallow slot every
From (Shallow Trench Isolation, STI)；For substrates such as SOI, GOI, can only use shallow-trench isolation.
Further, described in step B, lower active area can be formed by injection, it is possible to outside being adulterated by patterned original position
Prolong formation.
Further, " upper active area " described in step B, E and " lower active area ", in the two whichever make device source, what
Person makees device drain terminal, there is no a fixed pattern, can being conveniently set according to device performance and follow-up interconnection.
Further, by the device channel being epitaxially formed described in step D, its material can be identical with lower active area materials
(being epitaxially formed Si raceway groove as on active area under heavily doped Si), it is possible to different from lower active area materials (as in N+ heavy doping
GeSi under be epitaxially formed Si raceway groove on active area, under the heavily doped GeSi of P+, be epitaxially formed Ge raceway groove on active area)；Permissible
It is undoped, it is possible to by the way of original position doped epitaxial or ion implanting, form the raceway groove of doping.
Further, as the filler metal Metal 0 of conductive layer described in step G, it is desirable to possess low resistivity, good
Good through hole filling capacity, optional tungsten, copper etc..
Further, as the filler metal Metal 1 of conductive layer described in step H and J, it is desirable to possess low resistance
Rate, such as the one in aluminum, silver, platinum, copper and titanium and composition metal thereof.
Further, in step D, E, F, G, H, I and J, anisotropic etching uses such as reactive ion etching
(Reactive Ion Etching, RIE) or inductively coupled plasma (Inductively Coupled Plasma, ICP)
Deng.
Further, in step E, annealing way uses rapid thermal annealing (Rapid Thermal Annealing), point
Peak annealing (Spike Annealing), annealing of glittering (Flash Annealing) and laser annealing (Laser Annealing)
In one.
Further, in step G and H, deposit metal employing is evaporated, sputters, is electroplated and chemical vapor deposition
One in (Chemical Vapor Deposition).
Further, in step C, E, F and G, the isotropism deposition process of nonmetallic materials uses low pressure chemical gas
Deposit (Low Pressure Chemical Vapor Deposition, LPCVD), atomic layer deposition (Atomic Layer mutually
Deposition, ALD) in one, anisotropy deposition process using plasma strengthen chemical vapor deposition (Plasma
Enhanced Chemical Vapor Deposition, PECVD), inductively coupled plasma strengthen chemical vapor deposition
In (Inductively Coupled Plasma Enhance Chemical Vapor Deposition, ICPECVD) one
Kind, do not indicate when being isotropism or anisotropy with deposit, choose any one kind of them.
Further, in step K, the purpose of alloy be in order to allow the contact jaw of metal interconnection and active layer source electrode,
Drain electrode, grid form more preferable Ohmic contact, simultaneously so that dielectric material is finer and close, use the treatment temperature of alloying furnace
For 300-500 DEG C, the process time is 30min-60min, optimizes and uses 430 DEG C to process 30min.
Advantages of the present invention and good effect are as follows:
1) vertical channel structure that the present invention proposes is compared with traditional horizontal channel structure, and biomolecule is entered in the solution
During row Brownian movement, all directions to nanowire channel surface all produce random collision, will finally produce more in nanowire surface
High modification density, and in the case of channel direction level, major part biomolecule can only be modified at raceway groove upper surface and ditch
Road sidewall, raceway groove lower surface almost cannot be modified；
2) compared with the method for existing horizontal nanowire etching raceway groove, the etching through hole of present invention proposition, epi channels
Integrated approach, size and the pattern of device channel can be accurately controlled, it is to avoid raceway groove forming process in existing method
In etching injury, improve the performance of device；
3) method comparing horizontal nanowire definition ditch length, the present invention can break through conventional lithography work by the false gate layer of deposit
Skill limits, and Jiang Gouchang foreshortens to below 10nm, and the modification of single protein or nucleic acid molecules is highly profitable by this；
4) complete and mutually compatible with traditional integrated circuit manufacturing technology, technique is simple, and cost price is little.
Accompanying drawing explanation
Fig. 1-14 is the schematic diagram of each joint technique preparing vertical-channel N-type nanowire biosensor in SOI substrate.
In each figure, (a) is top view, and (b) is the profile in (a) along A-A '.
Wherein:
Fig. 1 forms the isolation of device on soi substrates；
Fig. 2 carries out N-type heavy doping to active area under device；
Fig. 3 deposits SDE mask layer 1, false gate layer material, SDE mask layer 2 successively；
Fig. 4 photoetching, etching form the raceway groove window of device；
Fig. 5 epitaxial monocrystalline silicon raceway groove also planarizes；
Fig. 6 forms the upper active area of device, and carries out N-type heavy doping；
Fig. 7 deposits top mask layer, and photoetching also etches top mask layer, defines liquid gate region；
Fig. 8 removes false gate layer；
Fig. 9 anisotropy deposit inter-level dielectric also planarizes；
Figure 10 etches source and drain contact hole, and filler metal, it is achieved planarization；
Figure 11 deposits interconnection metal, and photoetching also etches metal, defines interconnection pattern；
Figure 12 deposits passivation layer and planarizes；
Figure 13 photoetching Etch Passivation, inter-level dielectric, SDE mask layer 2, the window of definition solution titration, exposed portion
Liquid gate region；
Figure 14 photoetching Etch Passivation, the window of definition probe test, exposes metal pad；
Figure 15 is the legend of Fig. 1～Figure 14.
Detailed description of the invention
The present invention is described in detail with instantiation below in conjunction with the accompanying drawings.
Vertical-channel N-type nanowire biosensor in SOI substrate can be realized according to the following step:
1) will utilize HNA solution that top silicon surface is thinned to 20nm in (100) SOI substrate, etched by photoetching, RIE
The lower active area of definition device, removes photoresist, as shown in Figure 1；
2) As is carried out+Inject doping and form the lower active area (making the source/drain terminal of device) of device, Implantation Energy 10KeV, note
Enter dosage 5E15cm-2；
3)LPCVD SiO240nm, carries out surface planarisation by chemically mechanical polishing, exposes active area under heavy doping
Upper surface, forms STI, as shown in Figure 2；
4) 10nm SiO is deposited successively by ALD2(making SDE mask layer 1, its thickness defines the lower active area side of device
The width of wall is 10nm), 14nm Si3N4(gate layer of playing tricks, its thickness defines a length of 14nm of liquid grid of device), 10nm SiO2
(making SDE mask layer 2, the width of the upper active area side wall that its thickness defines device is 10nm), as shown in Figure 3；
5) (window is the cylinder of diameter 15nm, and bottom of window reveals to form device channel window by photoetching, ICP etching
Go out active area under the heavy doping of device), remove photoresist, as shown in Figure 4；
6) by epitaxy technique, the lower active area of device is formed undoped p single crystalline Si raceway groove, is thrown by chemical machinery
Light grinds off the single crystal silicon material beyond the deposit of SDE mask layer 2 upper surface, as shown in Figure 5；
7) LPCVD depositing polysilicon 30nm, and carry out As+Inject doping, Implantation Energy 15KeV, implantation dosage 5E15cm-2, by photoetching, ICP etches polycrystalline silicon 30nm, form active area (as the source/drain terminal of device) on N+ heavily doped polysilicon, go
Glue, as shown in Figure 6；
8) annealed 1000 DEG C by RTA, 10s, the source of activating appts, leakage；
9) LPCVD deposit 50nm carborundum is as top mask layer, and by lithographic definition liquid gate region, ICP etches carbonization
Silicon mask 50nm, removes photoresist, as shown in Figure 7；
10) ICP etching removes the 10nm SiO not covered by top mask layer2(SDE mask layer 2), 14nm Si3N4(false
Gate layer), expose the upper surface of SDE mask layer 1；By isotropic etching, remove whole Si3N4False gate layer, as shown in Figure 8；
11) remove top mask layer by RIE etching, deposit 200nm SiO by PECVD2As inter-level dielectric, and utilize
Chemically mechanical polishing realizes planarization, as shown in Figure 9；
12) form device source, the contact hole at leakage two ends by photoetching, ICP etching, remove photoresist；
13) sputtering 500nm tungsten, device source, the contact hole at leakage two ends are filled by tungsten；
14) by tungsten is chemically-mechanicapolish polished, remove beyond 200nm SiO2The upper surface of inter-level dielectric
Tungsten, it is achieved the conductive layers apart between device, as shown in Figure 10；
15) splash-proofing sputtering metal aluminum 1 μm, photoetching RIE etch metallic aluminium, form interconnection pattern, remove photoresist, as shown in figure 11；
16) PECVD deposits 2 μm SiO2As passivation layer, and chemically-mechanicapolish polish, as shown in figure 12；
17) window titrated by lithographic definition solution, RIE Etch Passivation, inter-level dielectric, SDE mask layer 2 etc. form
SiO2Lamination, etching break-through stops to liquid gate layer, removes photoresist, as shown in figure 13；
18) by the window of lithographic definition probe test, RIE Etch Passivation SiO22 μm, stop to exposing metallic aluminium pad
Only, remove photoresist；
19) 430 DEG C, alloy 30min, as shown in figure 14.
The embodiment of the present invention is not limited to the present invention.Any those of ordinary skill in the art, without departing from this
Under bright technical scheme ambit, technical solution of the present invention is made many by the method and the technology contents that all may utilize the disclosure above
Possible variation and modification, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from technical solution of the present invention
Content, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, the most still belongs to
In the range of technical solution of the present invention is protected.
Claims (12)
1. an integrated approach for the nanowire biosensor of vertical-channel, comprises the steps:
A. semi-conductive substrate is provided, it is achieved device isolation；
B. heavily doped lower active area is formed；
C. the false gate stack of deposit；
Implement step as follows:
C1. one layer of medium of deposit makees a SDE mask layer, and its thickness defines the width of the lower active area side wall of device；
C2. one layer of medium of deposit is played tricks gate layer, and its thickness defines the raceway groove of device and modifies length；
C3. one layer of medium of deposit makees the 2nd SDE mask layer, and its thickness defines the width of the upper active area side wall of device；
D. vertical channel structure is formed by etching through hole, epi channels；
Implement step as follows:
D1. by the shape of lithographic definition channels cross-section, size；
D2. forming raceway groove window by anisotropic etching, bottom of window exposes active area under the heavy doping of device, removes photoresist；
D3. the raceway groove of device is formed by graphical epitaxy technology；
D4. the deposit channel material beyond the 2nd SDE mask layer upper surface is removed by chemically mechanical polishing, it is achieved planarization；
E. the heavily doped upper active area of device is formed by deposit, etching；
Implement step as follows:
E1. one layer of active material of deposit；
E2. by the upper active area window of photoetching technique definition；
E3. form upper active area by anisotropic etching, remove photoresist；
E4. by ion implantation technique, upper active area is carried out heavy doping；
E5. source, leakage are activated by annealing process；
F. remove false grid material, form nanowire channel modified regions；
Implement step as follows:
F1. one layer of medium of deposit makees top mask layer；
F2. by lithographic definition liquid gate region；
F3. by anisotropic etching, expose the upper surface of a SDE mask layer, remove photoresist；
F4. by isotropic etching, whole false gate layer is removed；
G. the metal contact at device source and drain two ends is formed；
Implement step as follows:
G1. top mask layer is removed；
G2. medium between anisotropy deposit from level to level, carries out chemical-mechanical planarization；
G3. formed the contact hole at device source and drain two ends by photoetching, anisotropic etching, remove photoresist；
G4. filler metal Metal 0 in each contact hole；
G5. by metal Metal 0 being carried out chemical-mechanical planarization, the metal of the upper surface beyond inter-level dielectric is removed
Metal 0, it is achieved the conductive layers apart between device；
H. metal interconnection pattern is formed；
Implement step as follows:
H1. deposit metal Metal 1；
H2. formed extraction and the probe test pad at source and drain two ends by photoetching, anisotropic etching, remove photoresist；
I. the modification window of solution titration is formed；
I1. one layer of medium of deposit is as passivation layer, and carries out chemical-mechanical planarization；
I2. modifying window by lithographic definition, when solution titrates, biomolecule to be finished is spread through liquid by this window
Gate layer, then diffuse to the surface bonding modification of nano wire；
I3. by anisotropic etching, window and liquid gate layer are modified in connection, are formed and modify table from substrate surface to nanowire channel
The path in face, removes photoresist；
J. probe test window is formed；
Implement step as follows:
J1. lithographic definition probe test window；
J2. by anisotropic etching, expose probe test pad defined in interconnection metal Metal 1, remove photoresist；
K. alloy, makes metal present more preferable ohm property with the contact position of source and drain, makes dielectric material finer and close simultaneously.
2. the method for claim 1, it is characterised in that a SDE mask layer and the 2nd SDE mask layer in step C
Material is identical, different with false gate layer material, and the isotropic etching of a SDE mask layer is selected ratio to be more than by false gate layer material
5:1。
3. the method for claim 1, it is characterised in that top mask material described in step F is different from false gate layer,
The isotropic etching of this top mask layer is selected ratio more than 5:1 by false gate layer material.
4. the method for claim 1, it is characterised in that Semiconductor substrate described in step A includes body silicon substrate, SOI
Substrate, body germanium substrate and GOI substrate.
5. method as claimed in claim 4, it is characterised in that isolate described in step A, uses trap isolation to add for body substrate
Shallow-trench isolation；Shallow-trench isolation is used for SOI and GOI substrate.
6. the method for claim 1, it is characterised in that as the filler metal Metal0 of conductive layer described in step G
For tungsten or copper.
7. the method for claim 1, it is characterised in that as the filler metal of conductive layer described in step H and J
Metal 1 is the one in aluminum, silver, platinum, copper and titanium and composition metal thereof.
8. the method for claim 1, it is characterised in that in step D, E, F, G, H, I and J, anisotropic etching uses
RIE or ICP.
9. the method for claim 1, it is characterised in that in step E, annealing way uses rapid thermal annealing, spike to move back
Fire, the one glittered in annealing and laser annealing.
10. the method for claim 1, it is characterised in that in step step G and H, deposit metal use evaporation, sputtering,
One in plating and chemical vapor deposition.
11. the method for claim 1, it is characterised in that in step C, E, F and G, the isotropism of nonmetallic materials is formed sediment
Long-pending method uses the one in low-pressure chemical vapor phase deposition LPCVD, atomic layer deposition ALD, anisotropy deposition process employing etc.
Gas ions strengthens chemical vapor deposition PECVD, inductively coupled plasma strengthens chemical vapor deposition ICPECVD.
12. the method for claim 1, it is characterised in that in step K, the temperature that alloy uses is 300-500 DEG C, place
The reason time is 30min-60min.
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| US20100109101A1 (en) * | 2007-04-30 | 2010-05-06 | Kamins Theodore I | Method of Positioning Catalyst Nanoparticle and Nanowire-Based Device Employing Same |
| US20120329253A1 (en) * | 2010-03-11 | 2012-12-27 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor device |
| CN103348238A (en) * | 2010-12-03 | 2013-10-09 | 加利福尼亚大学董事会 | Nanowire field-effect transistor biosensor with improved sensitivity |
| CN105374752A (en) * | 2015-10-26 | 2016-03-02 | 北京大学 | Integration method of vertical nano-wire transistor |
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| US20100109101A1 (en) * | 2007-04-30 | 2010-05-06 | Kamins Theodore I | Method of Positioning Catalyst Nanoparticle and Nanowire-Based Device Employing Same |
| US20120329253A1 (en) * | 2010-03-11 | 2012-12-27 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor device |
| CN103348238A (en) * | 2010-12-03 | 2013-10-09 | 加利福尼亚大学董事会 | Nanowire field-effect transistor biosensor with improved sensitivity |
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