CN106201965B - A kind of interior external clock source switching device and switching method based on IRIG-B - Google Patents
A kind of interior external clock source switching device and switching method based on IRIG-B Download PDFInfo
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- CN106201965B CN106201965B CN201610553210.2A CN201610553210A CN106201965B CN 106201965 B CN106201965 B CN 106201965B CN 201610553210 A CN201610553210 A CN 201610553210A CN 106201965 B CN106201965 B CN 106201965B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The interior external clock source switching device based on IRIG-B that the invention discloses a kind of, including main website board and several substation boards, the main website board are connect with substation board by BLVDS clock synchronization bus；CPU and FPGA are provided on main website board, the FPGA of main website board includes IRIG-B decoding circuit, internal clock circuit, time setting register, clock synchronization register, IRIG-B coding circuit and the first BLVDS coding-decoding circuit；CPU and FPGA are provided on the board of substation, the FPGA of substation board includes the 2nd BLVDS coding-decoding circuit.The switching method of the device is also disclosed simultaneously.The present invention is decoded and encodes to IRIG-B signal using FPGA realization, in external clock reference lossing signal, automatically switches to internal clock source, sends signal according to IRIG-B coded format, to guarantee each fastener clock synchronization work.
Description
Technical field
The present invention relates to a kind of interior external clock source switching device and switching method based on IRIG-B, belong to network clock synchronization skill
Art field.
Background technique
When there are record the real-time and synchronism of event time when the fastener of muti-piece record event to a device
Often merit attention.IRIG-B (InterRange Instrumentation Group), abbreviation B code clock synchronization, in stability
Industrial control field is widely used in high reliablity.Using IRIG-B as external clock reference, obtained in more and more devices
Using.But when external clock reference IRIG-B dropout for some reason, how to guarantee still to have clock to these fasteners into
Row clock synchronization becomes problem.
Summary of the invention
The interior external clock source switching device that in order to solve the above-mentioned technical problems, the present invention provides a kind of based on IRIG-B and
Switching method.
In order to achieve the above object, the technical scheme adopted by the invention is that:
A kind of interior external clock source switching device based on IRIG-B, including main website board and several substation boards, the master
Board of standing is connect with substation board by BLVDS clock synchronization bus；
CPU and FPGA are provided on the main website board, when the FPGA of main website board includes IRIG-B decoding circuit, is internal
Clock circuit, time setting register, clock synchronization register, IRIG-B coding circuit and the first BLVDS coding-decoding circuit；The time
Register is arranged to connect with the CPU of main website board, the time setting register, internal clock circuit, clock synchronization register,
IRIG-B coding circuit and the first BLVDS coding-decoding circuit are sequentially connected, the external IRIG-B pin of IRIG-B decoding circuit,
The IRIG-B decoding circuit is connect with clock synchronization register, and the IRIG-B coding circuit is connect with the CPU of main website board, described
First BLVDS coding-decoding circuit is connect with BLVDS clock synchronization bus；
CPU and FPGA are provided on the substation board, the FPGA of substation board includes the 2nd BLVDS coding-decoding circuit,
The 2nd BLVDS coding-decoding circuit is connect with the CPU of substation board, the 2nd BLVDS coding-decoding circuit also with BLVDS pairs
When bus connect.
The CPU of main website board is arranged register with the time by GPMC interface and connect.
IRIG-B coding circuit is connect by IRIG-B signal wire with the CPU of main website board.
2nd BLVDS coding-decoding circuit is connect by IRIG-B signal wire with the CPU of substation board.
A kind of switching method of the interior external clock source switching device based on IRIG-B, includes the following steps,
S1, defines priority rule in clock synchronization register, i.e., the priority of external clock synchronization time is higher than inside to constantly
Between priority；
S2, when powering on, self-operating time and beginning clock synchronization instruction are sent to main website board by the CPU of main website board
FPGA；After time setting register receives the self-operating time of main website Computer card CPU and starts clock synchronization instruction, internal clocking electricity
Road is initialized according to the self-operating time of main website Computer card CPU, and as internal clock synchronization source, the internal clock synchronization time is written
In clock synchronization register；
IRIG-B decoding circuit real time parsing exterior I RIG-B pin signal, when being resolved to exterior I RIG-B signal,
The external clock synchronization time that parsing obtains is written in clock synchronization register；
S3, IRIG-B coding circuit carry out IRIG-B coding according to the clock synchronization time of clock synchronization register, and coding is obtained
IRIG-B signal pass to the CPU of the first BLVDS coding-decoding circuit and main website board；
S4, IRIG-B signal is converted into BLVDS signal by the first BLVDS coding-decoding circuit, and BLVDS signal is sent to
In BLVDS clock synchronization bus；
The CPU of main website board carries out IRIG-B decoding, and it is synchronous to reach temporal；
S5, the FPGA real-time monitoring BLVDS clock synchronization bus of substation board, the 2nd BLVDS coding-decoding circuit is by BLVDS clock synchronization
BLVDS signal in bus is converted to IRIG-B signal, and IRIG-B signal is sent to the CPU of substation board, substation board
CPU carry out IRIG-B decoding, reach substation board time synchronization.
Advantageous effects of the invention: the 1, present invention is decoded and compiles to IRIG-B signal using FPGA realization
Code, in external clock reference lossing signal, automatically switches to internal clock source, sends and believes according to IRIG-B coded format
Number, to guarantee each fastener clock synchronization work；2, the present invention sends IRIG-B encoded signal using FPGA, and precision is high, postpones small；
3, the present invention sends IRIG-B signal by BLVDS bus, can set time to muti-piece substation board, stability high reliability
By force.
Detailed description of the invention
Fig. 1 is structural block diagram of the invention.
Fig. 2 is the structural block diagram of main website board.
Fig. 3 is the structural block diagram of substation board.
Specific embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following embodiment is only used for clearly illustrating the present invention
Technical solution, and not intended to limit the protection scope of the present invention.
As shown in Figure 1, a kind of interior external clock source switching device based on IRIG-B, including main website board and several substation plates
Card, main website board connect by BLVDS clock synchronization bus with substation board
As shown in Fig. 2, be provided with CPU and FPGA on main website board, the FPGA of main website board include IRIG-B decoding circuit,
Internal clock circuit, time setting register, clock synchronization register, IRIG-B coding circuit and the first BLVDS coding-decoding circuit.
Time setting register is connect with the CPU of main website board, is generally connect with the GPMC interface of CPU, time setting is posted
Storage, internal clock circuit, clock synchronization register, IRIG-B coding circuit and the first BLVDS coding-decoding circuit are sequentially connected,
The external IRIG-B pin of IRIG-B decoding circuit, IRIG-B decoding circuit are connect with clock synchronization register, and IRIG-B coding circuit is logical
It crosses IRIG-B signal wire to connect with the CPU of main website board, the first BLVDS coding-decoding circuit is connect with BLVDS clock synchronization bus.
As shown in figure 3, being provided with CPU and FPGA on the board of substation, the FPGA of substation board includes the 2nd BLVDS encoding and decoding
Circuit, the 2nd BLVDS coding-decoding circuit are connect by IRIG-B signal wire with the CPU of substation board, the 2nd BLVDS encoding and decoding electricity
Road is also connect with BLVDS clock synchronization bus.
The switching method of above-mentioned apparatus, comprising the following steps:
S1, defines priority rule in clock synchronization register, i.e., the priority of external clock synchronization time is higher than inside to constantly
Between priority.
S2, when powering on, self-operating time and beginning clock synchronization instruction are sent to main website board by the CPU of main website board
FPGA；After time setting register receives the self-operating time of main website Computer card CPU and starts clock synchronization instruction, internal clocking electricity
Road is initialized according to the self-operating time of main website Computer card CPU, and as internal clock synchronization source, the internal clock synchronization time is written
In clock synchronization register；
IRIG-B decoding circuit real time parsing exterior I RIG-B pin signal, when being resolved to exterior I RIG-B signal,
The external clock synchronization time that parsing obtains is written in clock synchronization register.
S3, IRIG-B coding circuit according to clock synchronization time of clock synchronization register (when there is the external clock synchronization time, coding
Time is the external clock synchronization time；When not having the external clock synchronization time, the time of coding is the internal clock synchronization time) carry out IRIG-B
It encodes, and the IRIG-B signal that coding obtains is passed to the CPU of the first BLVDS coding-decoding circuit and main website board.
S4, IRIG-B signal is converted into BLVDS signal by the first BLVDS coding-decoding circuit, and BLVDS signal is sent to
In BLVDS clock synchronization bus；
The CPU of main website board carries out IRIG-B decoding, and it is synchronous to reach temporal.
S5, the FPGA real-time monitoring BLVDS clock synchronization bus of substation board, the 2nd BLVDS coding-decoding circuit is by BLVDS clock synchronization
BLVDS signal in bus is converted to IRIG-B signal, and IRIG-B signal is sent to the CPU of substation board, substation board
CPU carry out IRIG-B decoding, reach substation board time synchronization.
The present invention is decoded and encodes to IRIG-B signal using FPGA realization, in external clock reference lossing signal situation
Under, internal clock source is automatically switched to, sends signal according to IRIG-B coded format, to guarantee each fastener clock synchronization work；
IRIG-B encoded signal is sent using FPGA, precision is high, postpones small；IRIG-B signal is sent by BLVDS bus, it can be to muti-piece
Substation board is set time, and stability high reliability is strong.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (1)
1. a kind of switching method of the interior external clock source switching device based on IRIG-B, the interior external clock source based on IRIG-B
Switching device, including main website board and several substation boards, the main website board and substation board are connected by BLVDS clock synchronization bus
It connects；
CPU and FPGA are provided on the main website board, the FPGA of main website board includes IRIG-B decoding circuit, internal clocking electricity
Road, time setting register, clock synchronization register, IRIG-B coding circuit and the first BLVDS coding-decoding circuit；The time setting
Register is connect with the CPU of main website board, and the time setting register, internal clock circuit, clock synchronization register, IRIG-B are compiled
Code circuit and the first BLVDS coding-decoding circuit are sequentially connected, and the external IRIG-B pin of IRIG-B decoding circuit is described
IRIG-B decoding circuit is connect with clock synchronization register, and the IRIG-B coding circuit is connect with the CPU of main website board, and described first
BLVDS coding-decoding circuit is connect with BLVDS clock synchronization bus；
CPU and FPGA are provided on the substation board, the FPGA of substation board includes the 2nd BLVDS coding-decoding circuit, described
2nd BLVDS coding-decoding circuit is connect with the CPU of substation board, and the 2nd BLVDS coding-decoding circuit is also total with BLVDS clock synchronization
Line connection；
It is characterized by comprising following steps,
S1, defines priority rule in clock synchronization register, i.e., the priority of external clock synchronization time is higher than the internal clock synchronization time
Priority；
S2, when powering on, self-operating time and beginning clock synchronization instruction are sent to main website board by the CPU of main website board
FPGA；After time setting register receives the self-operating time of main website Computer card CPU and starts clock synchronization instruction, internal clocking electricity
Road is initialized according to the self-operating time of main website Computer card CPU, and as internal clock synchronization source, the internal clock synchronization time is written
In clock synchronization register；
IRIG-B decoding circuit real time parsing exterior I RIG-B pin signal will be solved when being resolved to exterior I RIG-B signal
The external clock synchronization time that analysis obtains is written in clock synchronization register；
S3, IRIG-B coding circuit carry out IRIG-B coding according to the clock synchronization time of clock synchronization register, and coding is obtained
IRIG-B signal passes to the CPU of the first BLVDS coding-decoding circuit and main website board；
S4, IRIG-B signal is converted into BLVDS signal by the first BLVDS coding-decoding circuit, and BLVDS signal is sent to
In BLVDS clock synchronization bus；
The CPU of main website board carries out IRIG-B decoding, and it is synchronous to reach temporal；
S5, the FPGA real-time monitoring BLVDS clock synchronization bus of substation board, the 2nd BLVDS coding-decoding circuit is by BLVDS clock synchronization bus
On BLVDS signal be converted to IRIG-B signal, and IRIG-B signal is sent to the CPU of substation board, the CPU of substation board
IRIG-B decoding is carried out, substation board time synchronization is reached.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610553210.2A CN106201965B (en) | 2016-07-14 | 2016-07-14 | A kind of interior external clock source switching device and switching method based on IRIG-B |
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| CN201610553210.2A CN106201965B (en) | 2016-07-14 | 2016-07-14 | A kind of interior external clock source switching device and switching method based on IRIG-B |
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| CN106201965A CN106201965A (en) | 2016-12-07 |
| CN106201965B true CN106201965B (en) | 2019-05-21 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109193951A (en) * | 2018-11-08 | 2019-01-11 | 南京国电南自维美德自动化有限公司 | A kind of intelligent operation box with surge suppression function |
| CN111245567B (en) * | 2020-01-10 | 2023-06-23 | 深圳市风云实业有限公司 | Decoding and encoding system and method for IRIG-B (DC) code |
| CN112328002A (en) * | 2020-10-27 | 2021-02-05 | 许继集团有限公司 | Multi-board time synchronization method and system for relay protection device |
| CN117421270A (en) * | 2023-10-12 | 2024-01-19 | 中国兵器装备集团自动化研究所有限公司 | Self-adaptive clock system |
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| CN206003087U (en) * | 2016-07-14 | 2017-03-08 | 南京国电南自美卓控制系统有限公司 | A kind of interior external clock source switching device based on IRIG B |
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