CN109193951A - A kind of intelligent operation box with surge suppression function - Google Patents
A kind of intelligent operation box with surge suppression function Download PDFInfo
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- CN109193951A CN109193951A CN201811326455.7A CN201811326455A CN109193951A CN 109193951 A CN109193951 A CN 109193951A CN 201811326455 A CN201811326455 A CN 201811326455A CN 109193951 A CN109193951 A CN 109193951A
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- 238000011022 operating instruction Methods 0.000 claims abstract description 6
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Classifications
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- H02J13/0075—
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
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- H02J13/0062—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
- Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
- Y04S40/124—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using wired telecommunication networks or data transmission busses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
- Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
- Y04S40/126—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using wireless data transmission
Abstract
The present invention discloses a kind of intelligent operation box with surge suppression function, including mainboard, of ac acquire module, open into module, output module and voltage switching module；Mainboard includes control CPU and the first FPGA, passes through BLVDS bus connection communication between the first FPGA and each module；It manages CPU to obtain of ac by the first FPGA and acquire the collected of ac data of module, and opens into the collected intake data of module；Then according to the data got, transfer bus PT operational order is transmitted to voltage switching module, with the corresponding bus PT of switching, and utilize preset surge suppression algorithm, in the movement of surge suppression criterion, accordingly to module transmission breaking-closing operating instruction is outputed, breaking-closing operating is completed so that outputing module and controlling corresponding breaker.The accuracy to the control of circuit-breaker switching on-off angle can be improved in the present invention, effectively inhibits the excitation surge current generated when transformer air-drop, while realizing the intelligence of control box, and have operation and communication capacity.
Description
Technical field
The present invention relates to power system security automatic control technology field, especially a kind of intelligence with surge suppression function
It can control box.
Background technique
Control box is suitable for having single-hop and double breaking coils, split-phase as a kind of important electric system auxiliary device
And the breaker auxiliary operation of three-phase operation, it can monitor its operating status, carry out the switching of voltage transformer output AC voltage,
And realize contacting and cooperating for protective device and breaker.Traditional operation case is by trip operation circuit, closing operation circuit, voltage
The composition such as switching circuit and pressure atresia circuit, by receiving long-range divide-shut brake order starting tripping/closing operation circuit, to disconnected
Road device carries out random divide-shut brake.
There is also following deficiencies for traditional operation case:
(1) it is unable to control circuit-breaker switching on-off angle, does not have the ability for inhibiting excitation surge current；
(2) control box is made of elements such as relay, power resistors, does not have calculation process and communication capacity
(3) control box module position and quantity are relatively fixed, can not arbitrarily extend.
Summary of the invention
It is an object of the present invention to provide a kind of intelligent operation box with surge suppression function, can be improved to breaker point
The accuracy of combined floodgate angle control, while using the intelligence of multi -CPU technology realization control box, so that it is had operation and communication energy
Power.
The technical scheme adopted by the invention is as follows: a kind of intelligent operation box with surge suppression function, including mainboard, exchange
Amount acquisition module is opened into module, outputs module and voltage switching module；
Mainboard includes control CPU and the first FPGA, the first FPGA and of ac acquisition module, opens into module, outputs module
And pass through BLVDS bus connection communication between voltage switching module；CPU is managed by the first FPGA, obtains of ac acquisition
The collected of ac data of module, and open into the collected intake data of module；Then the data that basis is got, to
Voltage switches module and transmits transfer bus PT operational order, with the corresponding bus PT of switching, and is calculated using preset surge suppression
Method, in the movement of surge suppression criterion, accordingly to module transmission breaking-closing operating instruction is outputed, so that outputing module control phase
The breaker answered completes breaking-closing operating.
The surge suppression algorithm that the present invention uses can include surge suppression criterion for existing algorithm, algorithm.The present invention passes through
Surge suppression function is dissolved into control box, it is possible to reduce the intermediate link of outlet loop, thus when reducing outlet loop movement
Between discreteness, raising circuit-breaker switching on-off angle is accurately controlled.
Preferably, the control CPU includes the control CPU and CPU management by serial ports connection communication, and control CPU passes through
GPMC interface and the first FPGA connection communication；CPU management includes man-machine interactive interface, and connects touch-control by man-machine interactive interface
Display module.The serial ports can be UART High Speed Serial.LCD can be used in touch control display module, to realize that band is true on mainboard
The man-machine interface of color liquid crystal display, the collected data letter of instantaneous operating conditions information and institute for showing current operation case
Breath.The transmission of data and operational order is acquired between control CPU and the first FPGA.
Further, CPU management further includes Ethernet interface, RS485 interface and RS232 interface.It can be used for current operation
Data communication and ethernet communication between case and other equipment, and IEC61850,103, Modbus etc. can be supported comprehensively
Electric power communication protocol.
Above-mentioned master cpu and CPU management can be used based on ARM Cortex-A8 framework, support floating-point operation
AM3352, work dominant frequency are up to 550MHz, and operational capability is powerful, can ensure the data-handling efficiency of intelligent operation box.
Preferably, the first FPGA includes IRIG-B clock synchronization unit, preamble reception unit, preposition transmission unit, the school CRC
Verification certificate member, data processing unit and the reception buffer cell and transmission buffer cell, Information Statistics list that respectively correspond each module
Member and polling system unit；
After IRIG-B clock synchronization unit receives external clock synchronous signal and parses, generates time message and send interrupt request singal
To control CPU, control CPU responds the interrupt request singal, realizes that clock is synchronous；The external clock synchronous signal is GPS
Synchronous satellite time service device issues time synchronization pulse signal；
It sends buffer cell and is used to store the manipulation instruction data that control CPU is issued, cycle wheel of the polling system unit to set
Each transmission buffer cell is ask, the data to be sent of each module of the correspondence that data processing unit is polled to polling system unit carry out
Preposition transmission unit is handled and is written, CRC check unit verifies the data to be sent that preposition transmission unit is written, preposition
Operational order data after verification are sent to corresponding module by BLVDS bus by transmission unit；Control the manipulation that CPU is issued
Director data includes acquiring module alternating voltage electric current request instruction towards of ac, towards the circuit-breaker switching on-off opened into module
Order, circuit breaker position, the instruction of each earthing switch position requests, instruct towards the breaking-closing operating for outputing module, and towards
The transfer bus PT operational order of voltage switching module；It controls CPU and passes through GPMC interface for the manipulation instruction number of each module of correspondence
It is sent in buffer cell according to write-in is corresponding；
Preamble reception unit receives the request-reply data that each module is issued by BLVDS bus, and CRC check unit is to receiving
Request-reply data verified, data processing unit to verify it is errorless after request-reply data carry out data extraction at
Reason, then by treated, the corresponding reception buffer cell of module is written for control CPU reading in data；
Information Statistics unit counts the data transmit-receive status data of preamble reception unit and preposition transmission unit, and will corresponding each mould
The statistical data write-in of part is corresponding to receive buffer cell, reads for control CPU.
Further, in the first FPGA, data processing unit includes: to add to data to be sent to the processing of data to be sent
Add the header information of including but not limited to synchronous code, module address, function code and frame length；
CRC check unit is to the generations of data to be sent and adds cyclic redundancy check；
The request-reply data that each module is issued by BLVDS bus include the header information with synchronous code；
After preposition transmission unit issues data to any module, preamble reception unit waits BLVDS total with the effective time set
The appearance of synchronous code on line, and starting receives corresponding request-reply data when synchronous code occurs；
Corresponding reception buffering is written after rejecting its header information in request-reply data after data processing unit is errorless to verification
Unit.
Preferably, of ac acquisition module includes the 2nd FPGA, AD conversion unit and of ac acquisition circuit；Of ac is adopted
Acquisition ac analog signal in collection circuit is transmitted to the 2nd FPGA after AD conversion cell translation is at digital signal；
2nd FPGA includes controlling of sampling unit, the second data processing unit, receiving unit, transmission unit and CRC check unit；
Controlling of sampling unit receives the of ac digital signal of AD conversion unit output, and fifo queue is written；
Receiving unit receives the of ac request instruction that the first FPGA is issued by BLVDS bus, and CRC check unit is to of ac
Request instruction verify it is errorless after, the second data processing unit reads the of ac in fifo queue by controlling of sampling unit
Data are as data to be sent and handled, and CRC check unit is to treated after data to be sent verify, by sending
Data after verification are passed through BLVDS bus transfer to the first FPGA by unit.
Further, the first FPGA by the manipulation instruction data that BLVDS bus is exported to each module include: synchronous code,
Module address, function code, order and cyclic redundancy check；
The receiving unit of 2nd FPGA obtains the module address in manipulation instruction data in outlet synchronous code in BLVDS bus
Information identified, is started to receive data state machine and start to receive corresponding of ac request instruction if address is consistent and (be worked as
Preceding manipulation instruction data)；
Second data processing unit includes: including but not limited to same to the addition of analog channel sampled value to the processing of data to be sent
Walk the header information of code, module address and function code；
After cyclic redundancy check generates to data to be sent and adds cyclic redundancy check, data transmission is carried out by transmission unit.
The of ac acquisition circuit can be the circuit PT/CT, and signal collected includes source side voltage, controlled side electric current
Etc. analog channels signal.Preferably, acquisition control unit control AD conversion unit believes ac analog according to 8KHz conversion ratio
Number carry out digital conversion.FIFO, that is, First Input First Output, First Input First Output.
Preferably, opening into module includes the 3rd FPGA and opening into Acquisition Circuit；It opens and acquires switching value information into Acquisition Circuit
It is transmitted to the 3rd FPGA；
3rd FPGA includes opening into acquisition unit, third data processing unit, receiving unit, transmission unit and CRC check unit；
It opens and obtains the switching value information opened into Acquisition Circuit acquisition into acquisition unit；Receiving unit receives first by BLVDS bus
The switching value request instruction that FPGA is issued, CRC check unit switch amount request instruction verify it is errorless after, at third data
Reason unit reads the switching value information opened and obtained into sampling unit, as data to be sent and is handled, CRC check unit pair
After data to be sent that treated are verified, the data after verification are passed through into BLVDS bus transfer to first by transmission unit
FPGA。
Further, the first FPGA by the manipulation instruction data that BLVDS bus is exported to each module include: synchronous code,
Module address, function code, order and cyclic redundancy check；
The receiving unit of 3rd FPGA obtains the module address in manipulation instruction data in outlet synchronous code in BLVDS bus
Information identified, is started to receive data state machine and start to receive corresponding switching value request instruction if address is consistent and (be worked as
Preceding manipulation instruction data)；
It includes but is not limited to synchronize that third data processing unit, which includes: the addition of switch amount information to the processing of data to be sent,
Code, module address and function code header information；
After cyclic redundancy check generates to data to be sent and adds cyclic redundancy check, data transmission is carried out by transmission unit.
It is above-mentioned open into Acquisition Circuit can be used it is existing open into conversion circuit, convert FPGA for intake signal and open into acquisition
The identifiable data of unit.
Preferably, module is outputed to include tripping/closing operation circuit, output and export read back circuit and the 4th FPGA；
4th FPGA includes outlet controlling unit, opens into acquisition unit, the 4th data processing unit, receiving unit, transmission unit and CRC
Verification unit；
Receiving unit receives the breaking-closing operating instruction that the first FPGA is issued by BLVDS bus, and CRC check unit is to divide-shut brake
Operational order verify it is errorless after, the 4th data processing unit instructs to outlet controlling unit according to breaking-closing operating and phase is written
The operation control command answered, outlet controlling unit according to operation control command driving output and export read back circuit starting tripping/
Closing operation circuit, to control the divide-shut brake of respective circuit breakers；It opens into sampling unit by outputing and exporting read back circuit acquisition
The switching value information for currently outputing outlet, is transmitted to the 4th data processing unit；4th data processing unit is to currently outputing out
Mouthful switching value information handled, CRC check unit, will by transmission unit to treated after data to be sent verify
Data after verification pass through BLVDS bus transfer to the first FPGA.
It includes the 5th FPGA and voltage commutation circuit that voltage, which switches module, and the 5th FPGA includes switch control unit, the 5th
Data processing unit, receiving unit, transmission unit and CRC check unit；
Receiving unit receives the transfer bus PT operational order that the first FPGA is issued by BLVDS bus, and CRC check unit is to cutting
Change bus PT operational order verify it is errorless after, the 5th data processing unit is according to transfer bus PT operational order, by cutting
Change the switching that control unit driving voltage switching circuit carries out bus PT；Then response message is written the 5th data processing unit
Transmission unit, after CRC check unit verifies response message, transmission unit starting sends data state machine will be after verification
Response message passes through BLVDS bus transfer to the first FPGA.
Specifically, mainboard, which controls CPU, determines the bus to be put into according to collected bus grounding switch location information
PT, and transfer bus PT operational order is sent out with synchronous code+module address+function code+control command+cyclic redundancy check format
It is sent to BLVDS bus；Receiving unit waits when the appearance of synchronous code in BLVDS bus, the module address in identification instruction
Information, if address effectively if start receive data state machine start receive transfer bus PT operational order；CRC check unit is corresponding
The processing for answering message includes addition cyclic redundancy check.
Existing fpga chip can be used in of the present invention first to the 5th FPGA, the integrated electricity of the various functions based on FPGA
The programming on road can refer to the prior art.
Beneficial effect
Compared with prior art, the present invention has the following advantages that and improves:
(1) by integrating surge suppression function in control box, it is possible to reduce the intermediate link of outlet loop, to reduce outlet
The discreteness of circuit behavior time, raising accurately control circuit-breaker switching on-off angle, production when reaching inhibition air-drop transformer
The purpose of raw excitation surge current；
(2) upgrading is transformed to traditional operation case using multi -CPU technology and large-scale F PGA technology, while it is total to introduce BLVDS
Line technology makes traditional operation case realize full intelligence, have powerful operation and communication capacity；
(3) a kind of intelligent modular unit with unified interface specification is designed using BLVDS bussing technique and FPGA technology, module can
It is not limited with arbitrary extension and by locational space.
Detailed description of the invention
Fig. 1 show the principle of work and power schematic block diagram of the intelligent operation box with surge suppression function；
Fig. 2 show main board function theory structure schematic block diagram；
Fig. 3 show AC module (i.e. of ac acquisition module) principle of work and power structural schematic block diagram；
Fig. 4 show DI module and (opens into module) principle of work and power structural schematic block diagram；
Fig. 5 show tripping/combined floodgate module (outputing module) principle of work and power structural schematic block diagram；
Fig. 6 show voltage switching module principle of work and power structural schematic block diagram.
Specific embodiment
It is further described below in conjunction with the drawings and specific embodiments.
Refering to what is shown in Fig. 1, the present invention has the intelligent operation box of surge suppression function, including mainboard, of ac acquire mould
Part (AC module) is opened into module (DI module), outputs module (tripping/combined floodgate module) and voltage switching module；
Mainboard includes control CPU and the first FPGA, the first FPGA and of ac acquisition module, opens into module, outputs module
And pass through BLVDS bus connection communication between voltage switching module；CPU is managed by the first FPGA, obtains of ac acquisition
The collected of ac data of module, and open into the collected divide-shut brake order data of module and intake data；Then root
According to the data got, transfer bus PT operational order is transmitted to voltage switching module, with the corresponding bus PT of switching, and is utilized
Preset surge suppression algorithm, accordingly to module transmission breaking-closing operating instruction is outputed, makes in the movement of surge suppression criterion
Module must be outputed and control corresponding breaker completion breaking-closing operating.
Embodiment
The present embodiment realizes the intellectualized reconstruction design of traditional operation case with multi -CPU technology and large-scale F PGA technology；
Realize that surge suppression algorithm completes the intelligent operation box integrated design with surge suppression function using mainboard control CPU.
As shown in Figure 1, the intelligent operation box with surge suppression function includes mainboard, the intelligence for acquiring AC voltage/current
AC module, the intelligent DI module (opening into module) of acquisition divide-shut brake order and circuit breaker position information, control breaker division
The voltage of the tripping of lock/combined floodgate module (outputing module) and transfer bus PT switch module.
Devising dual processors and FPGA on mainboard combined with Figure 1 and Figure 2, dual processors are used separately as control CPU and CPU management, and two
By High Speed Serial interactive information, FPGA is mainly used for realizing BLVDS differential bus transport protocol CPU.With reference to Fig. 3 to Fig. 6, AC
Module, DI module, tripping/combined floodgate module and voltage switching module devise for realizing the FPGA of BLVDS bus protocol, and
BLVDS bus is connected to by FPGA respectively.Mainboard controls CPU and is read by the first fpga chip from DI in BLVDS bus
The switching on and off order and circuit breaker position information of module acquisition, start surge suppression algorithm, in the movement of surge suppression criterion
Divide-shut brake order is sent to tripping/combined floodgate module by BLVDS bus, and the manipulation to breaker is completed by tripping/combined floodgate module,
To realize intelligentized design of the traditional operation case with surge suppression function.
As shown in Fig. 2, controlling CPU and CPU management on mainboard can be used based on ARM Cortex-A8 framework, supports to float
The AM3352 of point processing, work dominant frequency are up to 550MHz.It controls CPU and realizes that surge suppression algorithm controls circuit-breaker switching on-off angle
Excitation surge current of the degree to inhibit air-drop transformer to generate.CPU management for realizing the very color liquid crystal display of band man-machine interface, comprehensively
Support the electric power communication protocols such as IEC61850,103, Modbus.CPU management and control CPU pass through inner high speed serial ports exchange letter
Breath, control CPU is by GPMC interface with mainboard fpga chip EP4CE10F256(i.e. the first FPGA) connection, on mainboard FPGA
Construct front-end receiver/unit, preposition transmitter/unit, data processor/unit, Information Statistics module/unit, module
Polling system module/unit, IRIG-B clock synchronization module/unit receive buf/ buffer cell, send buf/ buffer cell and CRC
Module/verification unit, IRIG-B clock synchronization unit is for realizing synchronous satellite clock synchronization.
Mainboard works in this way:
Control CPU will control request command by GPMC interface and write corresponding module transmission buf, and polling system module is every
0.4ms poll once sends buf, and log-on data processor adds the data to be sent in the effective module being polled to and synchronizes
Preposition transmitter is written together after the header informations such as code, module address, function code, frame length, by CRC check unit to write-in before
The data for setting transmitter generate and add cyclic redundancy check, are finally started by preposition transmitter and send data state machine transmission data
To BLVDS bus；
Front-end receiver waits the appearance until synchronous code in BLVDS bus within effective time, and then starting receives data shape
State machine starts to receive the reply data from module in BLVDS bus, and CRC check unit carries out the data in front-end receiver
Verification and inspection, are picked the header information of frame data in preamble reception module by data processor after verification is errorless, then press mould
Part address is written corresponding module and receives in buf for control CPU reading；
Corresponding mould is written by Information Statistics module statistical data reiving/transmitting state information while receiving and dispatching message and by status information
Part is received in buf and is read for control CPU；
IRIG-B clock synchronization module parses the pulse signal to come from GPS synchronous satellite time service device, generates the same of time message
When to control CPU send interrupt request singal, control CPU respond interrupt requests, when reading by GPMC interface and be arranged local
The synchronization of clock realization clock.
As shown in figure 3, AC module is mainly by 8 channel parallel AD conversion chip ADS8548, PT/CT conversing circuits and FPGA
Chip M2S005(i.e. the 2nd FPGA) composition, receiver/unit, transmitter/unit, CRC module/school are constructed on M2S005
Verification certificate member, the second data processor and controlling of sampling unit.
2nd FPGA controls ADS8548 and carries out by 8KHz conversion ratio to analog channels such as source side voltage, controlled side electric currents
Number conversion, and change data is stored in local FIFO and is read for mainboard control CPU.Specific working mode are as follows:
Controlling of sampling unit controls ADS8548 and carries out analog-to-digital conversion by 8KHz frequency, and by change data write-in FIFO for data
Processor is read；
Mainboard controls CPU for of ac request instruction with synchronous code+module address+function code+order+cyclic redundancy check format
It is sent to BLVDS bus；
Receiving unit waits the appearance until synchronous code in BLVDS bus, then receives module address information, carries out address knowledge
Not, just start reception data state machine after recognizing effective address, start to receive in BLVDS bus from mainboard control CPU's
Of ac request instruction, CRC check unit are verified and are checked to the of ac request instruction in receiver；
Verify it is errorless after, data processor read FIFO in analog channel sampled value and add synchronous code, module address, function
Transmitter is written together after the header informations such as code, generated by data volume of the CRC check unit to write-in transmission unit and adds CRC
Check code finally starts transmission data state machine by generator and sends data to BLVDS bus.
As shown in Fig. 4, opens and mainly (opened into adopting by third fpga chip M2S005 and intake conversion circuit into module
Collector) composition, receiver/unit, transmitter/unit, CRC module/verification unit, third number are constructed on the 3rd FPGA
It according to processor/unit and opens into acquisition unit, the intake request command that the 3rd FPGA response mainboard control CPU comes, by counting
It opens according to processor reading into switching values information such as the collected switching on and off orders of acquisition unit and is written to transmitter by sending
Device is sent to BLVDS bus.Specific working mode are as follows:
Mainboard controls CPU for intake request command with synchronous code+module address+function code+order+cyclic redundancy check format
It is sent to BLVDS bus；
Receiver waits the appearance until synchronous code in BLVDS bus, then receives module address information, carries out Address Recognition,
Recognize after effective address just starting receive data state machine start to receive in BLVDS bus come from mainboard control CPU open into
Request command is measured, CRC check unit is verified and checked to the request command in receiver；
Verify it is errorless after, data processor reading opens into the switching values such as collected the combined floodgates order of acquisition unit, separating brake order letter
Breath, and transmitter is written together after adding the header informations such as synchronous code, module address, function code, by CRC check unit to write-in
The data of transmitter generate and add cyclic redundancy check, finally start transmission data state machine by generator and send data to BLVDS
Bus.
As shown in figure 5, tripping/combined floodgate module mainly by the 4th fpga chip M2S005, output and export read back circuit and
Tripping/closing operation circuit composition, constructs receiver/unit, transmitter/unit, CRC module/verification list on M2S005
It member, data processor/unit, outlet controlling unit and opens into acquisition unit.M2S005 responds the control that mainboard control CPU is issued
Order, is sent to outlet controlling unit for control command by data processor, is started by outlet controlling unit by digital output circuit and is jumped
Lock/closing circuit controls circuit-breaker switching on-off.Specific working mode are as follows:
Mainboard, which controls CPU, will control request command with synchronous code+module address+function code+control command+cyclic redundancy check lattice
Formula is sent to BLVDS bus；
Receiver waits the appearance until synchronous code in BLVDS bus, then receives module address information, recognizes effective address
Just starting reception data state machine starts to receive in BLVDS bus from the control request command of mainboard control CPU, the school CRC afterwards
Verification certificate member is verified and is checked to the control request command in receiver；
Verify it is errorless after, data processor executes different operations according to different orders, for control command, data processor
Control command is write into outlet controlling unit, is controlled by outlet controlling unit driving digital output circuit starting tripping/closing operation circuit
Circuit-breaker switching on-off processed；For request command, data processor reading is opened into the collected outlet readback state of acquisition unit；
Simultaneously transmitter is written in subsequent data processor assembling response message, raw by data of the CRC check unit to write-in transmitter
At and add cyclic redundancy check, finally started by generator and send data state machine and send reply data to BLVDS bus.
As shown in fig. 6, voltage switching module is made of the 5th fpga chip M2S005 and voltage commutation circuit, in M2S005
In construct receiver/unit, transmitter/unit, CRC module/verification unit, data processor/unit, switching control list
Member.The control command that M2S005 response mainboard control CPU comes, is sent to switching control list for control command by data processor
Member is carried out the switching of bus PT by switch control unit starting voltage commutation circuit.Specific working mode are as follows:
Mainboard controls CPU and determines which group PT of investment, bus PT switching command according to collected bus grounding switch location information
BLVDS bus is sent to synchronous code+module address+function code+control command+cyclic redundancy check format；
Receiver waits the appearance until synchronous code in BLVDS bus, then receives module address information, recognizes effective address
Just starting reception data state machine starts to receive in BLVDS bus from the control command of mainboard control CPU, CRC check list afterwards
Member is verified and is checked to the control command in receiver；
Verify it is errorless after, log-on data processor by control data write switch control unit, by switch control unit drive electricity
Switching circuit is pressed to realize the switching of bus PT；
Simultaneously transmitter is written in subsequent data processor assembling response message, raw by data of the CRC check unit to write-in transmitter
At and add cyclic redundancy check, finally started by generator and send data state machine and send reply data to BLVDS bus.
To sum up, the present invention realizes the integrated design of surge suppression function and operation box function.By surge suppression function
The solution for being dissolved into control box can reduce the intermediate link of outlet loop, to reduce outlet loop actuation time
Discreteness is more advantageous to raising and accurately controls to circuit-breaker switching on-off angle, keeps surge suppression effect more significant.It reduces simultaneously
On-site cable laying, favorably group screen on site, reduces operating cost, also reduces the probability of failure of device operation.
The present invention using CPU powerful data processing and is led in the design of multi -CPU technical application to control box circuit
Letter ability, making control box veritably realizes full intelligentized design.
The control box intelligent modular unit that the present invention is gone out using BLVDS bussing technique and large-scale F PGA Technology design, because of interface
It is unified to greatly facilitate the extension of operation box function without being limited by locational space, it can be neatly by increasing, reducing
The quantity of intelligent modular unit realizes the operation of single, double operation circuit and different type breaker.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (9)
1. a kind of intelligent operation box with surge suppression function, characterized in that including mainboard, of ac acquisition module, open into
Module outputs module and voltage switching module；
Mainboard includes control CPU and the first FPGA, the first FPGA and of ac acquisition module, opens into module, outputs module
And pass through BLVDS bus connection communication between voltage switching module；CPU is managed by the first FPGA, obtains of ac acquisition
The collected of ac data of module, and open into the collected intake data of module；Then the data that basis is got, to
Voltage switches module and transmits transfer bus PT operational order, with the corresponding bus PT of switching, and is calculated using preset surge suppression
Method, in the movement of surge suppression criterion, accordingly to module transmission breaking-closing operating instruction is outputed, so that outputing module control phase
The breaker answered completes breaking-closing operating.
2. the intelligent operation box according to claim 1 with surge suppression function, characterized in that the control CPU packet
The control CPU and CPU management by serial ports connection communication are included, control CPU passes through GPMC interface and the first FPGA connection communication；Pipe
Managing CPU includes man-machine interactive interface, and connects touch control display module by man-machine interactive interface.
3. the intelligent operation box according to claim 2 with surge suppression function, characterized in that CPU management further includes
Ethernet interface, RS485 interface and RS232 interface.
4. the intelligent operation box according to claim 2 with surge suppression function, characterized in that the first FPGA packet
Include IRIG-B clock synchronization unit, preamble reception unit, preposition transmission unit, CRC check unit, data processing unit and difference
The reception buffer cell and transmission buffer cell, Information Statistics unit and polling system unit of corresponding each module；
After IRIG-B clock synchronization unit receives external clock synchronous signal and parses, generates time message and send interrupt request singal
To control CPU, control CPU responds the interrupt request singal, realizes that clock is synchronous；
It sends buffer cell and is used to store the manipulation instruction data that control CPU is issued, cycle wheel of the polling system unit to set
Each transmission buffer cell is ask, the data to be sent of each module of the correspondence that data processing unit is polled to polling system unit carry out
Preposition transmission unit is handled and is written, CRC check unit verifies the data to be sent that preposition transmission unit is written, preposition
Operational order data after verification are sent to corresponding module by BLVDS bus by transmission unit；
Preamble reception unit receives the request-reply data that each module is issued by BLVDS bus, and CRC check unit is to receiving
Request-reply data verified, data processing unit to verify it is errorless after request-reply data carry out data extraction at
Reason, then by treated, the corresponding reception buffer cell of module is written for control CPU reading in data；
Information Statistics unit counts the data transmit-receive status data of preamble reception unit and preposition transmission unit, and will corresponding each mould
The statistical data write-in of part is corresponding to receive buffer cell, reads for control CPU.
5. the intelligent operation box according to claim 4 with surge suppression function, characterized in that in the first FPGA, number
According to processing unit to the processing of data to be sent include: to data to be sent addition include but is not limited to synchronous code, module address,
The header information of function code and frame length；
CRC check unit is to the generations of data to be sent and adds cyclic redundancy check；
The request-reply data that each module is issued by BLVDS bus include the header information with synchronous code；
After preposition transmission unit issues data to any module, preamble reception unit waits BLVDS total with the effective time set
The appearance of synchronous code on line, and starting receives corresponding request-reply data when synchronous code occurs；
Corresponding reception buffering is written after rejecting its header information in request-reply data after data processing unit is errorless to verification
Unit.
6. the intelligent operation box according to claim 1 with surge suppression function, characterized in that of ac acquires module
Including the 2nd FPGA, AD conversion unit and of ac acquisition circuit；Of ac acquisition circuit acquires ac analog signal, through AD
After converting unit is converted into digital signal, it is transmitted to the 2nd FPGA；
2nd FPGA includes controlling of sampling unit, the second data processing unit, receiving unit, transmission unit and CRC check unit；
Controlling of sampling unit receives the of ac digital signal of AD conversion unit output, and fifo queue is written；
Receiving unit receives the of ac request instruction that the first FPGA is issued by BLVDS bus, and CRC check unit is to of ac
Request instruction verify it is errorless after, the second data processing unit reads the of ac in fifo queue by controlling of sampling unit
Data are as data to be sent and handled, and CRC check unit is to treated after data to be sent verify, by sending
Data after verification are passed through BLVDS bus transfer to the first FPGA by unit.
7. the intelligent operation box according to claim 1 with surge suppression function, characterized in that opening into module includes the
It three FPGA and opens into Acquisition Circuit；It opens and is transmitted to the 3rd FPGA into Acquisition Circuit acquisition switching value information；
3rd FPGA includes opening into acquisition unit, third data processing unit, receiving unit, transmission unit and CRC check unit；
It opens and obtains the switching value information opened into Acquisition Circuit acquisition into acquisition unit；Receiving unit receives first by BLVDS bus
The switching value request instruction that FPGA is issued, CRC check unit switch amount request instruction verify it is errorless after, at third data
Reason unit reads the switching value information opened and obtained into sampling unit, as data to be sent and is handled, CRC check unit pair
After data to be sent that treated are verified, the data after verification are passed through into BLVDS bus transfer to first by transmission unit
FPGA。
8. the intelligent operation box according to claim 1 with surge suppression function, characterized in that outputing module includes jumping
Read back circuit and the 4th FPGA are outputed and exported to lock/closing operation circuit；4th FPGA include outlet controlling unit, open into
Acquisition unit, the 4th data processing unit, receiving unit, transmission unit and CRC check unit；
Receiving unit receives the breaking-closing operating instruction that the first FPGA is issued by BLVDS bus, and CRC check unit is to divide-shut brake
Operational order verify it is errorless after, the 4th data processing unit instructs to outlet controlling unit according to breaking-closing operating and phase is written
The operation control command answered, outlet controlling unit according to operation control command driving output and export read back circuit starting tripping/
Closing operation circuit, to control the divide-shut brake of respective circuit breakers；It opens into sampling unit by outputing and exporting read back circuit acquisition
The switching value information for currently outputing outlet, is transmitted to the 4th data processing unit；4th data processing unit is to currently outputing out
Mouthful switching value information handled, CRC check unit, will by transmission unit to treated after data to be sent verify
Data after verification pass through BLVDS bus transfer to the first FPGA.
9. the intelligent operation box according to claim 1 with surge suppression function, characterized in that voltage switches module packet
Include the 5th FPGA and voltage commutation circuit, the 5th FPGA include switch control unit, the 5th data processing unit, receiving unit,
Transmission unit and CRC check unit；
Receiving unit receives the transfer bus PT operational order that the first FPGA is issued by BLVDS bus, and CRC check unit is to cutting
Change bus PT operational order verify it is errorless after, the 5th data processing unit is according to transfer bus PT operational order, by cutting
Change the switching that control unit driving voltage switching circuit carries out bus PT；Then response message is written the 5th data processing unit
Transmission unit, after CRC check unit verifies response message, transmission unit starting sends data state machine will be after verification
Response message passes through BLVDS bus transfer to the first FPGA.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811326455.7A CN109193951A (en) | 2018-11-08 | 2018-11-08 | A kind of intelligent operation box with surge suppression function |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114280974A (en) * | 2021-11-17 | 2022-04-05 | 南京国电南自维美德自动化有限公司 | Centralized alternating current data sampling synchronization method and device based on FPGA |
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