CN106201568B

CN106201568B - Electronic device, multi-computer switcher and firmware updating method thereof

Info

Publication number: CN106201568B
Application number: CN201510382132.XA
Authority: CN
Inventors: 文洪涛; 苟云松
Original assignee: Aten International Co Ltd
Current assignee: Aten International Co Ltd
Priority date: 2014-12-23
Filing date: 2015-07-03
Publication date: 2020-04-17
Anticipated expiration: 2035-07-03
Also published as: CN106201568A; TWI545439B; TW201624290A

Abstract

The invention provides an electronic device, a multi-computer switcher and a firmware updating method thereof. The KVM switch is coupled to a plurality of target computers. The KVM switch comprises at least a processor module, a storage module, a programmable logic module and a plurality of image processing modules. The storage module is coupled to the processor module. The programmable logic module is coupled to the storage module. The processor module is used for receiving the updating information through the network and executing a writing program to the storage module so as to store the updating information in the storage module. One of the image processing modules is coupled between the programmable logic module and at least one of the target computers, and is used for reading the update information from the storage module through the programmable logic module and processing the image of the at least one target computer.

Description

Electronic device, multi-computer switcher and firmware updating method thereof

Technical Field

The present invention relates to a Keyboard-Video-Mouse Switch (KVM Switch), and more particularly, to an electronic device, a KVM Switch and a firmware update method thereof capable of saving cost and improving firmware update efficiency.

Background

Referring to FIG. 1, FIG. 1 is a diagram illustrating a conventional KVM switch (KVM over IP) with remote management function. As shown in FIG. 1, it is assumed that the KVM switch includes four sets of sampling circuits SAM 1-SAM 4, each set of sampling circuits SAM 1-SAM 4 is used for sampling one or more target computers TC, and each set of sampling circuits SAM 1-SAM 4 is provided with a programmable logic unit FPGA, a switch SW and a flash memory FM (flash memory). The Central Processing Unit (CPU) is coupled to the flash memory FM of the CPU, and is also coupled to the flash memories FM of the sampling circuits SAM 1-SAM 4.

When the CPU receives a firmware update information UG via the network N, the CPU must perform Write-In (Write-In) of the firmware update information UG on each of the five flash memories FM, which includes erasing, burning, and checking, thereby consuming a lot of time. Especially, as the number of target computers to be sampled by the KVM switch increases, the KVM switch must be provided with more sampling circuits, which results in that the time consumed by the CPU to execute the program for writing the firmware update information UG also increases, resulting in the firmware update efficiency of the conventional KVM switch and the problem of firmware version management.

In addition, each set of sampling circuits needs to be provided with one switch SW and one flash memory FM, which also results in the waste of hardware cost and volume of the KVM switch.

Disclosure of Invention

Therefore, the present invention is directed to an electronic device, a KVM switch and a firmware update method thereof, which solve the above-mentioned problems encountered in the prior art.

According to one embodiment of the present invention, a KVM switch is provided. In this embodiment, the KVM switch is coupled to a plurality of target computers. The KVM switch comprises at least a processor module, a storage module, a programmable logic module and a plurality of first image processing modules. The processor module is used for receiving the updating information through the network. The storage module is coupled to the processor module. The processor module executes a write-in procedure on the storage module to store the updated information in the storage module. The programmable logic module is coupled to the storage module. The first image processing module of the plurality of first image processing modules is coupled between the programmable logic module and at least one target computer of the plurality of target computers, and is used for reading the update information from the storage module through the programmable logic module and processing the image of the at least one target computer.

In one embodiment, the Programmable logic module is a Field-Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).

In one embodiment, the first image processing module includes an image processing circuit. The image processing circuit at least comprises a programmable logic unit. The programmable logic unit is arranged on the image processing circuit and coupled between the programmable logic module and the at least one target computer, and is used for reading the update information from the storage module through the programmable logic module and processing the image of the at least one target computer.

In one embodiment, the Programmable logic unit is a Field-Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).

In one embodiment, the Programmable logic unit is selected from the group consisting of a Field-Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).

In one embodiment, the storage module is a Flash Memory (Flash Memory).

In one embodiment, the processor module is a Central Processing Unit (CPU).

In one embodiment, the KVM switch further comprises a switching module respectively coupled to the processor module, the storage module and the programmable logic module for selectively switching the processor module or the programmable logic module coupled to the storage module.

In one embodiment, In a Write (Write-In) mode, the switching module switches the processor module to be coupled to the storage module such that the processor module can perform a Write process on the storage module to store the update information In the storage module.

In one embodiment, in a Read-Out (Read-Out) mode, the switch module switches the programmable logic module to couple to the storage module, so that the programmable logic module can Read the update information from the storage module.

In one embodiment, the switching module and the storage module transmit signals through a Serial Peripheral Interface (SPI).

In one embodiment, the update information received by the processor module via the network includes first information and second information, and the programmable logic module receives the first information and the first image processing module receives the second information during the process of the first image processing module reading the update information from the storage module via the programmable logic module.

In one embodiment, the plurality of first image processing modules respectively read the update information from the storage module through the programmable logic module.

In one embodiment, the KVM switch further comprises a plurality of second image processing modules respectively coupled to the first image processing modules and receiving the update information from the first image processing modules.

According to another embodiment of the present invention, a firmware update method for a KVM switch is provided. In this embodiment, the KVM switch comprises a processor module, a storage module, a programmable logic module, and a plurality of first image processing modules, wherein a first image processing module of the plurality of first image processing modules is coupled between the programmable logic module and at least one target computer of the plurality of target computers. The firmware updating method at least comprises the following steps: (a) receiving, by the processor module, the update information via the network; (b) executing a write-in program to the storage module by the processor module to store the updated information in the storage module; and (c) reading the updated information from the storage module by the first image processing module through the programmable logic module and performing image processing on the at least one target computer.

In one embodiment, before the step (b) and the step (c), the firmware updating method further comprises the following steps: (b') selectively switching the processor module or the programmable logic module to couple to the storage module.

In one embodiment, in a write mode, the step (b') switches to couple the processor module to the storage module so that the firmware updating method can perform the step (b).

In one embodiment, in a read mode, the step (b') switches to couple the programmable logic module to the storage module, so that the firmware updating method can perform the step (c).

In one embodiment, the update information received by the processor module via the network includes a first information and a second information, and during step (c), the programmable logic module receives the first information and the first image processing module receives the second information.

Another embodiment according to the present invention is an electronic device. In this embodiment, the electronic device at least comprises a processor module, a storage module, a first function module and a second function module. The processor module is used for receiving the updating information through the network. The storage module is coupled to the processor module. The processor module executes a write-in procedure on the storage module to store the updated information in the storage module. The first functional module has programmable logic elements capable of performing a first function, is coupled to the storage module, and is configured to perform the first function. The second functional module has at least one programmable logic element capable of executing a second function, wherein the at least one programmable logic element is coupled to the programmable logic element of the first functional module for reading the update information from the storage module through the programmable logic element of the first functional module. The programmable logic element of the first functional module and the at least one programmable logic element of the second functional module are in signal transmission via a Serial Peripheral Interface (SPI).

In one embodiment, the firmware updating method as described above further includes the following steps: (e) coupling a plurality of second image processing modules to the first image processing module respectively; and (f) receiving the updated information from the first image processing module by the plurality of second image processing modules respectively.

Compared with the prior art, the electronic device, the KVM switch and the firmware updating method thereof according to the present invention have the following advantages:

(1) because all the programmable logic units in the KVM switch share the same storage module, the programmable logic units in each group of image processing circuits do not need to be respectively matched with a switch and a storage module, and no multiplexer (multiplexer) is arranged between all the upstream programmable logic units and the downstream programmable logic units, so that the cost and the volume can be greatly saved, and the complexity of circuit design can be simplified.

(2) No matter how many sets of image processing circuits and programmable logic units are included in the KVM switch, when the processor module of the KVM switch receives an update message through the network, the processor module only needs to execute a write-in procedure of the update message to the shared storage module once, so that the time consumed by the whole write-in procedure of the update message can be greatly shortened, and the efficiency of updating the firmware of the KVM switch can be effectively improved.

(3) Because the programmable logic units on each group of image processing circuits read the updating information stored in the shared storage module at the same time, even if the number of the image processing circuits and the programmable logic units is greatly increased, the read time is not increased, so that the multi-computer switcher has very good expandability.

The advantages and spirit of the present invention will be further understood by the following detailed description and the accompanying drawings.

Drawings

FIG. 1 is a diagram illustrating a conventional KVM switch (KVM over IP) with remote management function;

FIG. 2 is a schematic diagram of a KVM switch according to an embodiment of the present invention;

FIG. 3A is a detailed functional block diagram of the KVM switch of FIG. 2;

FIG. 3B is a detailed connection of FIG. 3A;

FIG. 3C shows signals on the associated pin of FIG. 3B;

FIG. 4A is a diagram of a KVM switch according to another embodiment of the present invention;

FIG. 4B is a detailed connection of FIG. 4A;

FIG. 4C is a schematic diagram of an electronic device according to another embodiment of the invention;

fig. 5 is a flowchart illustrating a firmware update method for a kvm switch according to another embodiment of the present invention.

Description of the main Components

KVM, 1': multi-computer switcher

10. 40: processor module

11. 41: switching module

12. 42: storage module

14: programmable logic module

16: first image processing module

18: second image processing module

SAM 1-SAM 4, 160, 180: image processing circuit

FPGA: programmable logic unit

TC, 2: target computer

N: network

UG: updating information

3: central control computer

30: screen

31: keyboard with a keyboard body

32: mouse (Saggar)

4: electronic device

44: first function module

46: second function module

48: third function module

D1: the first information

D2: the second information

D3: third information

A CPU: central processing unit

SW: switch with a switch body

FM: flash memory

PROG B, DOUT, INIT B, DONE, DIN, Data, Clock: foot position

D0, D7: information

S10-S24: procedure step

Detailed Description

A preferred embodiment of the present invention is a kvm switch, but the present invention is not limited thereto. In this embodiment, the KVM switch is a KVM switch (KVM over IP) with remote management function, which allows a user to access digital video, audio and virtual media signals of a remote computer or server through a network, but is not limited thereto.

Referring to fig. 2, fig. 2 is a schematic diagram of the kvm switch according to this embodiment. As shown in fig. 2, the kvm switch 1 is respectively coupled to a plurality of target computers 2, and can receive an update information UG through a network N. The KVM switch 1 samples (Sampling), processes and compresses one or more video signals outputted from the plurality of target computers 2, and converts the sampled and compressed video signals into corresponding video data, so as to transmit the video data to the remote console computer 3 via the network N. On the other hand, the KVM switch 1 can also restore the keyboard/mouse network packet from the console computer 3 to the keyboard/mouse signal readable by the target computer 2. Thus, the console computer 3 can manage and control the target computers 2 through the network N and the KVM switch 1.

In practical applications, the number of target computers 2 coupled to the KVM switch 1 may vary according to hardware limitations and practical requirements, without specific limitations; the target computer 2 may be a general Personal Computer (PC), a Server (Server) or a Workstation (Workstation), without any specific limitation; the update information UG received by the KVM switch 1 via the network N may be a firmware update information, but not limited thereto; the type of the Network N is not particularly limited, and may be a general Ethernet (Ethernet), a Local Area Network (LAN) or the Internet.

Next, referring to fig. 3A, fig. 3A is a detailed functional block diagram of the kvm switch 1 in fig. 2. As shown in fig. 3A, the kvm switch 1 includes a processor module 10, a switching module 11, a storage module 12, a programmable logic module 14, and a plurality of first image processing modules 16. Each of the first image processing modules 16 includes an image processing circuit 160, and the image processing circuit 160 includes at least a programmable logic unit FPGA.

Wherein the processor module 10 is coupled to the switching module 11; the switching module 11 is respectively coupled to the processor module 10, the storage module 12 and the programmable logic module 14; the storage module 12 is coupled to the switching module 11. That is, the storage module 12 may be coupled to the processor module 10 or the programmable logic module 14 through the switch module 11. In addition, the programmable logic module 14 is coupled to the plurality of first image processing modules 16 in parallel. In each first image processing module 16, the programmable logic unit FPGA is disposed on the image processing circuit 160 and coupled between the programmable logic module 14 and at least one target computer 2. In addition, the number of the target computers 2 (e.g. M) is usually larger than the number of the first image processing modules 16 (e.g. N), so a switching circuit may be provided between the first image processing modules 16 and the target computers 2 for selecting the target computers (e.g. N selected from M; M is larger than N) corresponding to the number of the first image processing modules 16 from the target computers 2 for image processing. In a preferred embodiment, the switching circuit can be a matrix switch, but not limited thereto.

In this embodiment, the processor module 10 receives the update information UG via the network N. In practice, the update information UG may include at least a first information D1 and a second information D2. The first information D1 may be firmware update information corresponding to the programmable logic module 14 and the second information D2 may be firmware update information corresponding to the plurality of first image processing modules 16, but not limited thereto.

In practical applications, the processor module 10 may be a Central Processing Unit (CPU); the storage module 12 may be a Flash Memory (Flash Memory); the programmable logic module 14 and the programmable logic unit FPGA in each of the first image processing modules 16 may be Field-programmable gate arrays (FPGAs), but not limited thereto.

In addition, the signal transmission between the switching module 11 and the storage module 12 can be performed through a Serial Peripheral Interface (SPI); the programmable logic module 14 and the programmable logic unit FPGA in each first image processing module 16 can also perform signal transmission through a Serial Peripheral Interface (SPI); the signal transmission between the programmable logic module 14 and the switching module 11 can also be performed through a serial peripheral interface, but not limited thereto. In addition, other components using other communication protocols, such as a USB controller (not shown), may be further included in the kvm switch 1. The USB controller may also be coupled to the processor module 10 through the programmable logic module 14, and the programmable logic module 14 converts the relevant data from the USB controller to reduce the burden on the processor module 10 for protocol conversion.

In this embodiment, the switching module 11 is used for selectively switching the processor module 10 or the programmable logic module 14 to be coupled to the storage module 12 in different operation modes of the KVM switch 1. When the processor module 10 receives the update information UG via the network N, the KVM switch 1 operates In a Write (Write-In) mode. In the write mode of the KVM switch 1, the switching module 11 switches the processor module 10 to be coupled to the storage module 12, such that the processor module 10 can perform a write process on the storage module 12 to store the update information UG in the storage module 12.

It should be noted that, when the kvm switch 1 provided in the present invention performs the firmware update procedure, only the "write procedure of the single update information UG" needs to be executed on the "single storage module 12", and it is not necessary to execute the "write procedure of the plural firmware update information UG" on the "plural flash memories FM" as in the prior art shown in fig. 1, so the kvm switch 1 of the present invention can greatly reduce the time consumed by the entire write procedure of the update information, and effectively improve the efficiency of the kvm switch 1 for performing the firmware update.

After the entire update information writing process is completed, the KVM switch 1 operates in a Read-Out mode. In the read mode of the KVM switch 1, the switch module 11 is switched to couple the programmable logic module 14 to the storage module 12, such that the programmable logic module 14 can read the update information UG from the storage module 12 and reset according to the update information UG.

When the programmable logic module 14 reads the update information UG from the storage module 12, the programmable logic unit FPGA in each first image processing module 16 can simultaneously read the update information UG from the programmable logic module 14, and perform image processing on at least one target computer 2 coupled thereto.

Referring to fig. 3B and 3C, in more detail, the processor module 10 resets the programmable logic unit FPGAs in the plurality of first image processing modules 16 simultaneously through the PROG B pin, and then (within a specified time), each of the programmable logic unit FPGAs informs the processor module 10 that it is ready (for example, all the programmable logic unit FPGAs pull the voltage high, but not limited thereto) through the INIT B pin. Next, since the DIN pin of the programmable logic unit FPGA corresponds to the DOUT pin of the programmable logic module 14, each programmable logic unit FPGA can read all or a part of the update information UG (e.g., the second information D2) via the Data pin and the Clock pin between itself and the programmable logic module 14. Finally, each programmable logic unit FPGA will tell the processor module 10 via the DONE pin that it has closed the update information UG (e.g., all but not limited to pulling the voltage high).

In the process of resetting the programmable logic unit FPGAs, if any one of the programmable logic unit FPGAs has an error, the potential of the INIT B pin cannot be high, and the processor module 10 can know that at least one of the programmable logic unit FPGAs has an error in resetting. Similarly, in the process of reading the update information UG by the programmable logic unit FPGAs, if any programmable logic unit FPGA has an error, the potential of the DONE pin cannot be high, and the processor module 10 can know that at least one programmable logic unit FPGA has an error in reading, and then all the programmable logic unit FPGAs can read the update information UG again.

In practical applications, assuming that the first information D1 in the update information UG corresponds to the programmable logic module 14 and the second information D2 in the update information UG corresponds to the plurality of first image processing modules 16, when the programmable logic module 14 reads the update information UG from the storage module 12, the programmable logic module 14 receives the corresponding first information D1 in the update information UG and performs re-setting (firmware update) according to the first information D1; thereafter, when the programmable logic unit FPGA of each first image processing module 16 reads the update information UG from the programmable logic module 14 at the same time, the programmable logic unit FPGA of each first image processing module 16 is reset (firmware update) according to the second information D2 in the update information UG.

It should be noted that the time taken for the KVM switch 1 of FIG. 3A to perform the entire update reading procedure includes the time T1 taken by the programmable logic module 14 to read the update information UG from the storage module 12 and the time T2 taken by the programmable logic unit FPGA of each first image processing module 16 to simultaneously read the update information UG from the programmable logic module 14, which is much shorter than the time taken for the entire update writing procedure, so the entire update writing and reading procedure can be faster than the prior art shown in FIG. 1.

In addition, since the programmable logic module 14 is coupled to the plurality of first image processing modules 16 in parallel, the programmable logic unit FPGA in each first image processing module 16 "simultaneously" reads the update information UG from the programmable logic module 14, even if the number of the first image processing modules 16 and the programmable logic units FPGA is greatly increased, the overall reading time is not increased, so that the multi-computer switch 1 of the present invention has very good "vertical" expandability. That is, even if the number of the first image processing modules 16 is further increased, the time consumed for the whole update information reading process of the KVM switch 1 of FIG. 3 is not increased.

Therefore, the extensibility of the KVM switch of the present invention will be further described in another embodiment.

Referring to fig. 4A, fig. 4A is a detailed functional block diagram of a kvm switch according to another embodiment of the present invention. Comparing fig. 4A and fig. 3A, it can be seen that: the KVM switch 1' of FIG. 4A is further provided with a plurality of second image processing modules 18 than the KVM switch 1 of FIG. 3A. As shown in fig. 4A, the plurality of second image processing modules 18 are respectively coupled to the same one of the plurality of first image processing modules 16 in parallel, so that the programmable logic unit FPGA of each second image processing module 18 can simultaneously read the update information UG from the programmable logic unit FPGA of the first image processing module 16 and respectively perform image processing on the target computer 2 coupled thereto. In fact, the signal transmission between the plurality of second image processing modules 18 and the first image processing module 16 can be performed through a Serial Peripheral Interface (SPI), but is not limited thereto.

Referring to fig. 4B, in more detail, the processor module 10 resets the programmable logic unit FPGAs in the second image processing modules 18 via the PROG B pin, and then (within a predetermined period of time) each of the programmable logic unit FPGAs informs the processor module 10 that it is ready (for example, but not limited to, pulling the voltage high) via the INIT B pin. Next, since the DIN pin of the FPGA of the second image processing module 18 corresponds to the DOUT pin of the FPGA of the first image processing module 16, the FPGA of each second image processing module 18 can read all or a part of the update information UG (for example, the third information D3) via the Data pin and the Clock pin between the FPGA of the first image processing module 16 and the Data pin. Finally, the FPGA of each second image processing module 18 informs the processor module 10 that it has received the update information UG (e.g., all but not limited to pulling the voltage high) via the DONE pin.

At this time, the time taken for the kvm switch 1' in fig. 4A to perform the whole update information reading process includes the time taken for the programmable logic module 14 to read the update information UG from the storage module 12 and the time taken for the programmable logic unit FPGA in each first image processing module 16 to simultaneously read the update information UG from the programmable logic module 14, and also includes the time taken for the programmable logic unit FPGA in each second image processing module 18 to simultaneously read the update information UG from the programmable logic unit FPGA in the first image processing module 16. Although the time for the KVM switch 1' in FIG. 4 to perform the whole update reading process is longer than the time for the KVM switch 1 in FIG. 3 to perform the whole update reading process, the speed of the whole update writing and reading process is much faster than the prior art shown in FIG. 1 because the reading speed is much faster than the writing speed.

It should be noted that, it is assumed that the update information UG further includes a first information D1, a second information D2 and a third information D3, wherein the second information D2 corresponds to the plurality of first image processing modules 16, and the third information D3 corresponds to the plurality of second image processing modules 18. When the programmable logic unit FPGA of each second image processing module 18 simultaneously reads the update information UG from the programmable logic unit FPGA of the first image processing module 16, the programmable logic unit FPGA of each second image processing module 18 receives the third information D3 in the update information UG. That is, each second image processing module 18 can update the firmware through the same first image processing module 16 at the same time.

It can be inferred from fig. 3A and fig. 4A that: the KVM switch of the present invention has excellent vertical and horizontal expandability. The lateral expansion means that the KVM switch of the present invention can further sequentially expand … a plurality of third image processing modules (or other functional modules for non-image processing purposes) and a plurality of fourth image processing modules (or other functional modules for non-image processing purposes) by the above-mentioned method. Moreover, since the reading speed of the storage module is much faster than the writing speed, the speed of the KVM switch performing the whole update information writing and reading process is faster than the prior art shown in FIG. 1, which is helpful to improve the firmware update efficiency.

It should be noted that, besides the KVM switch, the above concept (including the above architecture and firmware updating method) of the present invention is also applicable to other electronic devices having a plurality of programmable logic devices (e.g. FPGA or CPLD), and the plurality of programmable logic devices can be further divided into a plurality of functional modules according to their functions, and the functions of the functional modules are not limited to the above protocol conversion or image processing. If at least one programmable logic device directly connected to the switch module 11 is considered as a "first functional module"; the remaining at least one programmable logic device not directly connected to the switching module 11 is respectively referred to as a "second functional module" (but directly connected to a programmable logic device in the first functional module) and a "third functional module" …, and when the third functional module is coupled to the first functional module through a programmable logic device of the second functional module, the third functional module can perform firmware update according to the above description through the second functional module and the second functional module can also perform firmware update according to the above description through the first functional module.

For example, as shown in fig. 4C, it is assumed that the electronic device 4 includes a processor module 40, a switching module 41, a storage module 42, a first function module 44, a second function module 46, and a third function module 48. Wherein, the storage module 42 is coupled to the processor module 40 through the switching module 41; the first functional module 44 is coupled to the storage module 42 through the switching module 41; the second functional module 46 is coupled to the first functional module 44; the third functional module 48 is coupled to the second functional module 46.

The processor module 40 is configured to receive the update information UG via the network N and perform a write procedure on the storage module 42 via the switch module 41 to store the update information UG in the storage module 42. The first functional module 44 has a programmable logic device FPGA capable of performing a first function, and is configured to perform the first function. The second functional module 46 has at least one programmable logic device FPGA capable of performing a second function. The third functional module 48 has at least one programmable logic device FPGA capable of performing the third function.

The at least one programmable logic device FPGA of the second functional module 46 is coupled to the programmable logic device FPGA of the first functional module 44, and is used for reading the update information UG from the storage module 42 through the programmable logic device FPGA of the first functional module 44 to update the firmware. In practical applications, the signal transmission between the programmable logic device FPGA of the first functional module 44 and the at least one programmable logic device FPGA of the second functional module 46 can be performed through a Serial Peripheral Interface (SPI), but not limited thereto.

Similarly, the at least one programmable logic element FPGA of the third functional module 48 is coupled to the at least one programmable logic element FPGA of the second functional module 46, and since the at least one programmable logic element FPGA of the second functional module 46 has read the update information UG from the storage module 42 through the programmable logic element FPGA of the first functional module 44, the at least one programmable logic element FPGA of the third functional module 48 can read the update information UG from the at least one programmable logic element FPGA of the second functional module 46 for firmware update. In practical applications, the signal transmission between the at least one programmable logic device FPGA of the third functional module 48 and the at least one programmable logic device FPGA of the second functional module 46 can be performed through a Serial Peripheral Interface (SPI), but is not limited thereto.

According to another embodiment of the present invention, a firmware update method for a KVM switch is provided. In this embodiment, the firmware updating method of the KVM switch is used to update the firmware of a KVM switch, and the KVM switch is a KVM over IP (KVM over IP) with a remote management function, so that a user can access the digital video, audio and virtual media signals of a remote computer or a workstation through a network, but not limited thereto.

The KVM switch comprises at least a processor module, a storage module, a programmable logic module and a plurality of first image processing modules. The first image processing module of the plurality of first image processing modules is coupled between the programmable logic module and at least one target computer of the plurality of target computers.

Referring to fig. 5, fig. 5 is a flowchart illustrating a firmware updating method of the kvm switch according to the embodiment. As shown in FIG. 5, in step S10, the processor module receives update information via the network. In step S12, the method determines whether the KVM switch is operated In a Write-In mode or a Read-Out mode.

If the KVM switch is operated in the write mode as the result of the determination in the step S12, the method proceeds to a step S14, in which the processor module is switched to be coupled to the storage module. Next, the method proceeds to step S18, where the processor module executes a write procedure on the storage module to store the updated information in the storage module.

If the KVM switch is operated in the read mode as the result of the determination in the step S12, the method proceeds to a step S16, in which the programmable logic module is switched to be coupled to the storage module. Then, the method proceeds to step S20, where the first image processing module reads the updated information from the storage module through the programmable logic module and performs image processing on the at least one target computer.

In practical applications, assuming that the update information received by the processor module via the network in step S10 includes a first information and a second information, and the first information corresponds to the programmable logic module and the second information corresponds to the plurality of first image processing modules, in step S20, the programmable logic module receives the first information and the first image processing modules receive the second information.

It should be noted that, in step S20, since each first image processing module reads the update information from the programmable logic module "at the same time", even if the number of first image processing modules is greatly increased, the overall reading time is not increased, so the kvm switch of the present invention has very good "vertical" expandability. Therefore, after step S20, the method may further include steps S22 and S24, respectively coupling the plurality of second image processing modules to the first image processing module, and respectively receiving the update information from the first image processing module by the plurality of second image processing modules.

The above detailed description of the preferred embodiments is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of the present invention by the preferred embodiments disclosed above. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the claims appended hereto.

Claims

1. A KVM switch coupled to a plurality of target computers, the KVM switch comprising:

a processor module for receiving an update message over a network;

a storage module coupled to the processor module, the processor module executing a write-in procedure to the storage module to store the updated information in the storage module;

a programmable logic module, coupled to the storage module, for reading the update information from the storage module; and

the plurality of first programmable logic units are coupled to the programmable logic module in a parallel mode and used for reading the updating information from the programmable logic module at the same time, and each first programmable logic unit is coupled between the programmable logic module and at least one target computer in the plurality of target computers and used for carrying out image processing on the at least one target computer after the updating information is read from the programmable logic module.

2. The KVM switch of claim 1, wherein the programmable logic module is selected from the group consisting of a field programmable gate array or a complex programmable logic device.

3. The KVM switch of claim 1, wherein the first programmable logic unit is selected from the group consisting of a field programmable gate array or a complex programmable logic device.

4. The KVM switch of claim 1, wherein the storage module is a flash memory.

5. The KVM switch of claim 1, wherein the processor module is a central processor.

6. The KVM switch of claim 1, further comprising:

a switching module, coupled to the processor module, the storage module and the programmable logic module, for selectively switching the processor module or the programmable logic module to be coupled to the storage module.

7. The KVM switch of claim 6, wherein in a write mode, the switching module switches the processor module to be coupled to the storage module such that the processor module can perform the write process on the storage module to store the updated information in the storage module.

8. The KVM switch of claim 6, wherein in a read mode, the switching module switches the programmable logic module to be coupled to the storage module such that the programmable logic module can read the update information from the storage module.

9. The KVM switch of claim 6, wherein the switch module and the storage module are configured for signal transmission via a serial peripheral interface.

10. The KVM switch of claim 1, wherein the update information received by the processor module via the network comprises a first information and a second information, the first information being received by the programmable logic module and the second information being received by the first programmable logic unit during the reading of the update information from the storage module by the first programmable logic unit via the programmable logic module.

11. The KVM switch of claim 1, wherein the plurality of first programmable logic units respectively read the update information from the storage module through the programmable logic module.

12. The KVM switch of claim 1, further comprising:

a plurality of second programmable logic units respectively coupled between the same one of the plurality of first programmable logic units and at least one of the plurality of target computers and receiving the update information from the first programmable logic units, wherein the plurality of second programmable logic units are coupled to the same one of the plurality of first programmable logic units in parallel.

13. A firmware updating method of a KVM switch, the KVM switch comprising a processor module, a storage module, a programmable logic module and a plurality of first programmable logic units, the plurality of first programmable logic units being coupled to the programmable logic module in parallel, each of the plurality of first programmable logic units being coupled between the programmable logic module and at least one target computer of a plurality of target computers, the firmware updating method comprising the steps of:

(a) receiving an update message from the processor module via a network;

(b) executing a write-in procedure to the storage module by the processor module to store the updated information in the storage module; and

(c) the programmable logic module reads the updating information from the storage module, and after the plurality of first programmable logic units simultaneously read the updating information from the programmable logic module, the plurality of first programmable logic units perform image processing on the at least one target computer.

14. The firmware updating method according to claim 13, wherein before the steps (b) and (c), the firmware updating method further comprises the steps of:

(b') selectively switching the processor module or the programmable logic module to couple to the storage module.

15. The firmware updating method of claim 14, wherein in a write mode, step (b') switches the processor module to be coupled to the storage module so that the firmware updating method can perform step (b).

16. The firmware updating method of claim 14, wherein in a read mode, the step (b') switches the programmable logic module to be coupled to the storage module so that the firmware updating method can perform the step (c).

17. The firmware updating method of claim 14, wherein the update information received by the processor module via the network comprises a first information and a second information, and during the step (c), the programmable logic module receives the first information and the first programmable logic unit receives the second information.

18. The firmware updating method of claim 14, wherein the plurality of first programmable logic units respectively read the update information from the storage module through the programmable logic module.

19. The firmware updating method of claim 14, further comprising the steps of:

(e) coupling a plurality of second programmable logic units between the same one of the plurality of first programmable logic units and at least one of the plurality of target computers, wherein the plurality of second programmable logic units are coupled to the same one of the plurality of first programmable logic units in a parallel manner; and

(f) the update information is received by the plurality of second programmable logic units from the first programmable logic units, respectively.