TWI545439B - Electronic apparatus, keyboard-video-mouse switch, and firmware updating method thereof - Google Patents

Description

Electronic device, KVM switch and firmware update method thereof

The present invention relates to a Keyboard-Video-Mouse Switch (KVM Switch), and more particularly to an electronic device, a KVM switch, and a firmware update method thereof that can save cost and improve firmware update efficiency.

Please refer to FIG. 1. FIG. 1 is a schematic diagram showing a conventional KVM over IP with remote management function. As shown in FIG. 1, it is assumed that the KVM switch KVM includes four sets of sampling circuits SAM1~SAM4, and each set of sampling circuits SAM1~SAM4 is used to respectively sample one or more target computers TC, and each set of sampling circuits Each of SAM1~SAM4 is provided with a programmable logic unit FPGA, a switch SW and a flash memory FM. In addition to the flash memory FM of the CPU, the CPU must also be coupled to the flash memory FM of each of the sampling circuits SAM1 to SAM4.

When the CPU of the CPU receives a firmware update information UG through the network N, the CPU must perform a Write-In program of the firmware update information UG for each of the five flash memory FMs. It involves steps such as erasing, burning, and inspection, which is very time consuming. Especially when the KVM switch KVM needs to sample more and more target computers, the KVM switch KVM must also set more sampling circuits, thus causing the CPU of the CPU to execute the firmware update information UG write. The time spent in the program will also become more and more obvious, resulting in poor firmware update efficiency of the traditional KVM switch KVM, and firmware version management issues.

In addition, each group of sampling circuits needs to be provided with a switch SW and a flash memory FM, which also causes the hardware cost and volume waste of the KVM switch. Therefore, the above problems of the conventional KVM switch have to be overcome.

Accordingly, the present invention provides an electronic device, a KVM switch, and a firmware update method thereof to solve the above problems encountered in the prior art.

A specific embodiment of the present invention is a KVM switch. In this embodiment, the KVM switch is coupled to a plurality of target computers. The KVM switch includes at least a processor module, a storage module, a programmable logic module, and a plurality of first image processing modules. The processor module is configured to receive update information via the network. The storage module is coupled to the processor module. The processor module performs a writing process on the storage module to store the update information in the storage module. The programmable logic module is coupled to the storage module. The first image processing module of the plurality of first image processing modules is coupled between the programmable logic module and at least one of the plurality of target computers for translating the programmable logic module The group reads the update information from the storage module and performs image processing on the at least one target computer.

In one embodiment, the programmable logic module is a Field-Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).

In an embodiment, the first image processing module includes an image processing circuit. The image processing circuit includes at least a programmable logic unit. The programmable logic unit is disposed on the image processing circuit and coupled between the programmable logic module and the at least one target computer for reading update information from the storage module through the programmable logic module and The at least one target computer performs image processing.

In one embodiment, the programmable logic unit is a Field-Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).

In one embodiment, the storage module is a flash memory.

In one embodiment, the processor module is a Central Processing Unit (CPU).

In an embodiment, the KVM switch further includes a switching module coupled to the processor module, the storage module, and the programmable logic module for selectively switching The processor module or the programmable logic module is coupled to the storage module.

In an embodiment, in the Write-In mode, the switching module is switched to connect the processor module to the storage module, so that the processor module can perform a writing process on the storage module to update The information is stored in the storage module.

In one embodiment, in the Read-Out mode, the switching module is switched to convert the programmable logic module to the storage module, so that the programmable logic module can read and update from the storage module. News.

In an embodiment, the switching module and the storage module transmit signals through a Serial Peripheral Interface (SPI).

In one embodiment, the update information received by the processor module through the network includes the first information and the second information, and the first image processing module reads the update information from the storage module through the programmable logic module. During the process, the programmable logic module receives the first information and the first image processing module receives the second information.

In one embodiment, the plurality of first image processing modules respectively read update information from the storage module through the programmable logic module.

In one embodiment, the KVM switch further includes a plurality of second image processing modules coupled to the first image processing module and receiving update information from the first image processing module.

Another embodiment of the present invention is a firmware update method for a KVM switch. In this embodiment, the KVM switch includes at least a processor module, a storage module, a programmable logic module, and a plurality of first image processing modules, and the first of the plurality of first image processing modules The image processing module is coupled between the programmable logic module and at least one target computer of the plurality of target computers. The firmware update method includes at least the following steps: (a) receiving, by the processor module, update information through the network; (b) executing, by the processor module, a write program to the storage module to store update information in the storage module And (c) reading, by the first image processing module, the update information from the storage module through the programmable logic module and performing image processing on the at least one target computer.

Another embodiment in accordance with the present invention is an electronic device. In this embodiment, the electronic device includes at least a processor module, a storage module, a first function module, and a second function. Capable module. The processor module is configured to receive update information via the network. The storage module is coupled to the processor module. The processor module performs a writing process on the storage module to store the update information in the storage module. The first function module has a programmable logic element that can perform the first function, is coupled to the storage module, and is configured to perform the first function. The second functional module has at least one programmable logic component capable of performing a second function, wherein the at least one programmable logic component is coupled to the programmable logic component of the first functional module for transmitting the first functional mode The group of programmable logic elements reads updated information from the storage module. The programmable logic component of the first functional module and the at least one programmable logic component of the second functional module are transmitted through a Serial Peripheral Interface (SPI).

Compared with the prior art, the electronic device, the KVM switch and the firmware updating method thereof according to the present invention have the following advantages:

(1) Since all of the programmable logic units in the KVM switch of the present invention share the same storage module, the programmable logic units on each group of image processing circuits do not need to be combined with one switch and one Storage module, and there is no multiplexer between all upstream programmable logic units and downstream programmable logic units, which can save cost and size, and simplify circuit design complexity. .

(2) Regardless of how many sets of image processing circuits and programmable logic units are included in the KVM switch of the present invention, when the processor module of the KVM switch receives an update message through the network, the processor module only It is necessary to execute a program for updating the update information to the shared storage module, so that the time required for the entire update information writing program can be greatly shortened, and the efficiency of the firmware update of the KVM switch is effectively improved.

(3) Since the programmable logic unit on each group of image processing circuits simultaneously reads the update information stored in the shared storage module, even if the number of image processing circuits and programmable logic units is greatly increased, It does not cause an increase in reading time, making the KVM switch very scalable.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

KVM, 1, 1'‧‧‧ KVM switch

10, 40‧‧‧ processor modules

11, 41‧‧‧Switch Module

12, 42‧‧‧ storage module

14‧‧‧Programmable logic module

16‧‧‧First Image Processing Module

18‧‧‧Second image processing module

SAM1~SAM4, 160, 180‧‧‧ image processing circuit

FPGA‧‧‧programmable logic unit

TC, 2‧‧‧ target computer

N‧‧‧Network

UG‧‧‧Update Information

3‧‧‧Central computer

30‧‧‧ screen

31‧‧‧ keyboard

32‧‧‧ Mouse

4‧‧‧Electronic devices

44‧‧‧First function module

46‧‧‧Second function module

48‧‧‧ third function module

D1‧‧‧ first information

D2‧‧‧Second information

D3‧‧‧ Third Information

CPU‧‧‧Central Processing Unit

SW‧‧ switch

FM‧‧‧ flash memory

PROG B, DOUT, INIT B, DONE, DIN, Data, Clock‧‧‧ feet

D0, D7‧‧‧ Information

S10~S24‧‧‧ Process steps

1 is a schematic diagram of a conventional KVM over IP with remote management function; FIG. 2 is a schematic diagram of a KVM switch according to an embodiment of the present invention; 2B is a detailed functional block diagram of the multi-computer switcher in FIG. 2; FIG. 3B is a detailed connection relationship of FIG. 3A; FIG. 3C is a signal on the relevant pin position of FIG. 3B; FIG. 4A is a diagram showing the signal according to the present invention; FIG. 4B is a schematic diagram showing the detailed connection relationship of FIG. 4A; FIG. 4C is a schematic diagram of an electronic device according to another embodiment of the present invention; A flowchart of a firmware update method of a KVM switch according to another embodiment of the present invention.

A preferred embodiment of the present invention is a KVM switch, but the invention is not limited thereto. In this embodiment, the KVM switch is a KVM over IP with remote management function, which allows the user to access the digital video, audio and virtual of the remote computer or server through the network. Media signal, but not limited to this.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of the KVM switch of this embodiment. As shown in FIG. 2, the KVM switch 1 is coupled to a plurality of target computers 2, and can receive an update information UG through the network N. The KVM switch 1 will separately sample (Sampling), image process and compress the one or more video signals outputted by the plurality of target computers 2 into corresponding image data, so as to transmit the image data through the network N. Transfer to the remote central computer 3. On the other hand, the KVM switch 1 can also restore the keyboard/mouse network packet from the central control computer 3 to the keyboard/mouse signal readable by the target computer 2. In this way, the central control computer 3 can manage and control a plurality of target computers 2 through the network N and the KVM switch 1.

In practical applications, the number of target computers 2 to which the KVM switch 1 is coupled The target may be changed according to its hardware limitation and actual needs, and there is no specific limitation; the target computer 2 may be a commonly-used personal computer (PC), a server (Server) or a workstation (Workstation), and there is no specific limitation; The update information UG received by the KVM switch 1 through the network N may be a firmware update information, but is not limited thereto; the type of the network N is not limited, and may be a common Ethernet network. Ethernet, Local Area Network (LAN), or Internet.

Next, please refer to FIG. 3A. FIG. 3A is a detailed functional block diagram of the KVM switch 1 of FIG. As shown in FIG. 3A, the KVM switch 1 includes a processor module 10, a switching module 11, a storage module 12, a programmable logic module 14, and a plurality of first image processing modules 16. Each of the first image processing modules 16 includes an image processing circuit 160 and the image processing circuit 160 includes at least a programmable logic unit FPGA.

The processor module 10 is coupled to the switch module 11; the switch module 11 is coupled to the processor module 10, the storage module 12, and the programmable logic module 14; the storage module 12 is coupled to the switch module 11 . That is, the storage module 12 can be coupled to the processor module 10 or the programmable logic module 14 through the switching module 11. In addition, the programmable logic module 14 is coupled to the plurality of first image processing modules 16 in parallel. In each of the first image processing modules 16 , the programmable logic unit FPGA is disposed on the image processing circuit 160 and coupled between the programmable logic module 14 and the at least one target computer 2 . In addition, the number of the plurality of target computers 2 (for example, M) is greater than the number of the plurality of first image processing modules 16 (for example, N), and thus the plurality of first image processing modules 16 There may be a switching circuit between the plurality of target computers 2 for selecting a target computer corresponding to the number of the first image processing modules 16 by the plurality of target computers 2 (for example, N selected from M; M Greater than N) for image processing. In a preferred embodiment, the switching circuit can be a matrix switch, but is not limited thereto.

In this embodiment, the processor module 10 receives the update information UG through the network N. In fact, the update information UG may include at least a first information D1 and a second information D2. The first information D1 may be the firmware update information corresponding to the programmable logic module 14 and the second information D2 may be the firmware update information corresponding to the plurality of first image processing modules 16, but not This is limited.

In practical applications, the processor module 10 can be a central processing unit (Central) The processing module (CPU); the storage module 12 can be a flash memory; the programmable logic module 14 and the programmable logic unit FPGA in each of the first image processing modules 16 can be on-site. A Field-Programmable Gate Array (FPGA) can be programmed, but not limited to this.

In addition, the signal transmission between the switching module 11 and the storage module 12 through a serial Peripheral Interface (SPI); the programmable logic module 14 and each of the first image processing modules 16 The programmable logic unit FPGA can also transmit signals through the serial peripheral interface (SPI); the programmable logic module 14 and the switching module 11 can also transmit signals through the serial interface of the sequence, but none of them limit. In addition, there may be other components in the KVM switch 1 that use other communication protocols, such as a USB controller (not shown). The USB controller can also be coupled to the processor module 10 through the programmable logic module 14 and the related data from the USB controller can be converted by the programmable logic module 14 to reduce the processor module 10. The burden of protocol conversion.

In this embodiment, the switching module 11 is configured to selectively switch the processor module 10 or the programmable logic module 14 to the storage module 12 in different operating modes of the KVM switch 1. When the processor module 10 receives the update information UG through the network N, the KVM switch 1 operates in a Write-In mode. In the write mode of the switch 1, the switch module 11 is switched to the processor module 10 and coupled to the storage module 12, so that the processor module 10 can execute the write process to the storage module 12. The update information UG is stored in the storage module 12.

It should be noted that, when the KVM switch 1 proposed by the present invention performs the firmware update procedure, it is only necessary to perform the "single update information UG write procedure" for the "single storage module 12". As in the prior art shown in FIG. 1, the "multiple firmware update information UG writing procedure" needs to be performed on "a plurality of flash memory FMs", so the KVM switch 1 of the present invention can greatly shorten the entire update information. The time spent writing the program effectively improves the efficiency of the PC switch 1 for firmware update.

When the entire update information writing process is completed, the KVM switch 1 operates in a Read-Out mode. In the read mode of the KVM switch 1, the switching module 11 switches to the programmable logic module 14 coupled to the storage module 12, which enables the programmable logic mode. The group 14 can read the update information UG from the storage module 12 and re-set it according to the update information UG.

When the programmable logic module 14 reads the update information UG from the storage module 12, the programmable logic unit FPGA in each of the first image processing modules 16 can simultaneously read from the programmable logic module 14. The information UG is updated, and image processing is performed on each of the at least one target computer 2 coupled to each other.

Please refer to FIG. 3B and FIG. 3C. In more detail, the processor module 10 resets the programmable logic unit FPGA in the plurality of first image processing modules 16 through the PROG B pin. For a specified period of time, each programmable logic unit FPGA will tell the processor module 10 that it is ready through the INIT B pin (for example, the potential is pulled high, but not limited to this). Next, since the DIN pin of the programmable logic cell FPGA corresponds to the DOUT pin of the programmable logic module 14, each programmable logic cell FPGA can be connected to the programmable logic module 14 The Data pin and the Clock pin read all or part of the update information UG (for example, the second information D2). Finally, each programmable logic unit FPGA will tell the processor module 10 that the update information UG has been received through the DONE pin (for example, the potential is raised, but not limited thereto).

In the process of resetting the programmable logic unit FPGA, if any of the programmable logic unit FPGAs has an error, the potential of the INIT B pin cannot be high, and the processor module 10 can know that there is At least one programmable logic unit FPGA has a reset error. Similarly, in the process of reading the update information UG by the programmable logic unit FPGA, if any of the programmable logic unit FPGAs has an error, the potential of the DONE pin cannot be high, and the processor module 10 It can be known that at least one programmable logic unit FPGA has a read error, and all the programmable logic unit FPGAs can read the update information UG again.

In the actual application, it is assumed that the first information D1 in the update information UG corresponds to the programmable logic module 14 and the second information D2 in the update information UG corresponds to the plurality of first image processing modules 16 When the programmable logic module 14 reads the update information UG from the storage module 12, the programmable logic module 14 receives the corresponding first information D1 in the update information UG and re-sets according to the first information D1. (firmware update); after that, when each When the programmable logic unit FPGA in the image processing module 16 simultaneously reads the update information UG from the programmable logic module 14, the programmable logic unit FPGA in each of the first image processing modules 16 is based on The second information D2 in the update information UG is re-set (firmware update).

It should be noted that the time taken by the computer switcher 1 of FIG. 3A to update the information reading program in total includes the time T1 and time taken by the programmable logic module 14 to read the update information UG from the storage module 12. The time T2 taken by the programmable logic unit FPGA in the first image processing module 16 to simultaneously read the update information UG from the programmable logic module 14 is still much shorter than the time taken by the entire update information writing program. Therefore, the entire update information writing and reading process will be much faster than the prior art shown in FIG.

In addition, since the programmable logic module 14 is coupled to the plurality of first image processing modules 16 in a parallel manner, the programmable logic unit FPGA in each of the first image processing modules 16 is "simultaneously" The programmable logic module 14 reads the update information UG. Even if the number of the first image processing module 16 and its programmable logic unit FPGA is greatly increased, the overall reading time is not increased, so that the multi-computer of the present invention Switch 1 has very good "longitudinal" scalability. That is, even if the number of the first image processing modules 16 is greatly increased, the time taken by the computer switcher 1 of FIG. 3 to perform the entire update information reading process is not increased.

Therefore, the expandability of the KVM switch of the present invention will be further explained in another embodiment.

Please refer to FIG. 4A. FIG. 4A is a detailed functional block diagram of a KVM switch according to another embodiment of the present invention. 4A and FIG. 3A, the KVM switch 1' of FIG. 4A is further provided with a plurality of second image processing modules 18 than the KVM switch 1 of FIG. 3A. As shown in FIG. 4A, the plurality of second image processing modules 18 are coupled to the same first image processing module 16 of the plurality of first image processing modules 16 in parallel, and thus each The programmable logic unit FPGA in the second image processing module 18 can simultaneously read the update information UG from the programmable logic unit FPGA in the first image processing module 16, and respectively connect the target computer 2 Perform image processing. In fact, the plurality of second image processing modules 18 and the first image processing module 16 can transmit signals through the serial peripheral interface (SPI), but not limited thereto.

Please also refer to FIG. 4B. In more detail, the processor module 10 is transmitted through PROG. The B pin simultaneously resets the programmable logic unit FPGA in the plurality of second image processing modules 18, and then (for a specified period of time) each programmable logic unit FPGA passes through the INIT B pin. The processor module 10 is told that it is ready (for example, the potential is pulled high, but not limited thereto). Next, since the DIN pin of the FPGA of the second image processing module 18 corresponds to the DOUT pin of the FPGA of the first image processing module 16, the FPGA of each second image processing module 18 can be connected thereto. The Data pin and the Clock pin between the FPGAs of the first image processing module 16 read all or part of the update information UG (for example, the third information D3). Finally, the FPGA of each second image processing module 18 tells the processor module 10 that the update information UG has been received through the DONE pin (for example, the potential is raised, but not limited thereto).

At this time, the time taken by the KVM switch 1 ′ in FIG. 4A to update the information reading program includes the time and time required for the programmable logic module 14 to read the update information UG from the storage module 12 . The time that the programmable logic unit FPGA in the first image processing module 16 reads the update information UG from the programmable logic module 14 also includes the second image processing module 18 The programmed logic unit FPGA simultaneously reads the time taken to update the information UG from the programmable logic unit FPGA in the first image processing module 16. Although the time taken by the multi-computer switch 1' in FIG. 4 to update the information reading program is longer than the time taken by the multi-computer switcher 1 in FIG. 3 to update the information reading program, The fetch rate is much faster than the write speed, so the entire update information is written and read at a much faster rate than the prior art shown in Figure 1.

It should be noted that, the update information UG further includes a first information D1, a second information D2, and a third information D3, wherein the second information D2 corresponds to the plurality of first image processing modules 16, and the third information D3 Corresponding to the plurality of second image processing modules 18. When the programmable logic unit FPGA in each second image processing module 18 simultaneously reads the update information UG from the programmable logic unit FPGA in the first image processing module 16, each second image processing module The programmable logic unit FPGA in group 18 receives the third information D3 in the update information UG. That is, each second image processing module 18 can perform firmware update through the same first image processing module 16 at the same time.

3A and 4A, it can be inferred that the KVM switch of the present invention has quite good longitudinal and lateral expandability. The horizontal expandability refers to the KVM switch of the present invention. A plurality of third image processing modules (or other functional modules for non-image processing processing) and a plurality of fourth image processing modules (or other functions for non-image processing purposes) may be continuously expanded in the above manner. Module).... Moreover, since the reading speed of the storage module is much larger than the writing speed, the speed of writing and reading the entire update information of the KVM switch of the present invention is still faster than that of the prior art shown in FIG. Helps improve the efficiency of firmware update.

It should be noted that in addition to the KVM switch, the above concept of the present invention (including the above architecture and firmware update method) is also applicable to other electronic devices having a plurality of programmable logic elements (such as FPGA or CPLD). The plurality of programmable logic elements can be divided into a plurality of functional modules according to different functions thereof, and the functions of the plurality of functional modules are not limited to the foregoing protocol conversion or image processing. At least one programmable logic component directly connected to the switching module 11 is regarded as a "first functional module"; and at least one programmable logic component not directly connected to the switching module 11 is regarded as " a second function module (but directly connected to one of the programmable modules in the first function module), a "third function module", and the third function module is passed through the second function module When a programmable logic component is coupled to the first functional module, the third functional module can perform firmware update according to the above description through the second functional module, and the second functional module can also pass through the first functional module. The group performs firmware update according to the above instructions.

For example, as shown in FIG. 4C, the electronic device 4 includes a processor module 40, a switching module 41, a storage module 42, a first function module 44, a second function module 46, and a third function module. 48. The storage module 42 is coupled to the processor module 40 through the switching module 41. The first function module 44 is coupled to the storage module 42 through the switching module 41. The second function module 46 is coupled to the first function module. The third function module 48 is coupled to the second function module 46.

The processor module 40 is configured to receive the update information UG through the network N and execute a writing process on the storage module 42 through the switching module 41 to store the update information UG in the storage module 42. The first function module 44 has a programmable logic element FPGA that can perform the first function and is used to perform the first function. The second function module 46 has at least one programmable logic element FPGA that can perform the second function. The third function module 48 has at least one programmable logic element FPGA that can perform the third function.

At least one programmable logic element FPGA of the second function module 46 is coupled The programmable logic component FPGA to the first functional module 44 is configured to read the update information UG from the storage module 42 through the programmable logic component FPGA of the first functional module 44 for firmware update. In a practical application, the programmable logic component FPGA of the first functional module 44 and the at least one programmable logic component FPGA of the second functional module 46 can transmit signals through the serial peripheral interface (SPI), but This is limited.

Similarly, at least one programmable logic element FPGA of the third function module 48 is coupled to at least one programmable logic element FPGA of the second function module 46, and at least one programmable program of the second function module 46 The logic element FPGA has read the update information UG from the storage module 42 through the programmable logic element FPGA of the first function module 44. Therefore, at least one programmable logic element FPGA of the third function module 48 can be self- At least one programmable logic element FPGA of the second function module 46 reads the update information UG for firmware update. In practical applications, at least one programmable logic element FPGA of the third function module 48 and at least one programmable logic element FPGA of the second function module 46 can transmit signals through a serial peripheral interface (SPI), but Not limited to this.

Another embodiment of the present invention is a firmware update method for a KVM switch. In this embodiment, the firmware update method of the KVM switch is used to update a firmware of a KVM switch, and the KVM switch is a KVM switch with remote management function ( KVM over IP) allows users to access digital video, audio and virtual media signals from remote computers or workstations via the Internet, but not limited to them.

The KVM switch includes at least a processor module, a storage module, a programmable logic module, and a plurality of first image processing modules. The first image processing module of the plurality of first image processing modules is coupled between the programmable logic module and at least one of the plurality of target computers.

Please refer to FIG. 5. FIG. 5 is a flow chart showing a method for updating the firmware of the KVM switch of this embodiment. As shown in FIG. 5, in step S10, the processor module receives the update information through the network. In step S12, the method determines that the KVM switch is operating in a Write-In mode or a Read-Out mode.

If the result of the determination in step S12 is that the KVM switch is operating in the write mode, the method proceeds to step S14, where the processor module is coupled to the storage module. Then, the The method performs step S18, and the processor module executes a writing process on the storage module to store the update information in the storage module.

If the result of the determination in step S12 is that the KVM switch is operating in the read mode, the method performs step S16 to switch the programmable logic module to the storage module. Then, the method performs step S20, and the first image processing module reads the update information from the storage module through the programmable logic module and performs image processing on the at least one target computer.

In the actual application, it is assumed that the update information received by the processor module through the network in step S10 includes a first information and a second information, and the first information corresponds to the programmable logic module and the second information Corresponding to the plurality of first image processing modules, in step S20, the programmable logic module receives the first information and the first image processing module receives the second information.

It should be noted that, in step S20, since each first image processing module reads the update information from the programmable logic module "simultaneously", even if the number of the first image processing module is greatly increased, This results in an increase in the overall reading time, so the KVM switch of the present invention has very good "longitudinal" scalability. Therefore, after the step S20, the method may further include steps S22 and S24, respectively coupling the plurality of second image processing modules to the first image processing module, and respectively, the plurality of second image processing modules respectively Receiving update information from the first image processing module.

Compared with the prior art, the electronic device, the KVM switch and the firmware updating method thereof according to the present invention have the following advantages:

(1) Since all of the programmable logic units in the KVM switch of the present invention share the same storage module, the programmable logic units on each group of image processing circuits do not need to be combined with one switch and one Storage module, and there is no multiplexer between all upstream programmable logic units and downstream programmable logic units, which can save cost and size, and simplify circuit design complexity. .

(2) Regardless of how many sets of image processing circuits and programmable logic units are included in the KVM switch of the present invention, when the processor module of the KVM switch receives an update message through the network, the processor module only It is necessary to execute a write program for updating the information of the shared storage module, so that the time required for the entire update information writing program can be greatly shortened. Improve the efficiency of the PC updater for firmware update.

(3) Since the programmable logic unit on each group of image processing circuits simultaneously reads the update information stored in the shared storage module, even if the number of image processing circuits and programmable logic units is greatly increased, It does not cause an increase in reading time, making the KVM switch very scalable.

The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

1‧‧‧Multicomputer switcher

10‧‧‧Processor Module

11‧‧‧Switch Module

12‧‧‧ Storage Module

14‧‧‧Programmable logic module

16‧‧‧First Image Processing Module

160‧‧‧Image Processing Circuit

FPGA‧‧‧programmable logic unit

2‧‧‧Target computer

N‧‧‧Network

UG‧‧‧Update Information

D1‧‧‧ first information

D2‧‧‧Second information

Claims (19)

A KVM switch coupled to a plurality of target computers, the KVM switch comprising: at least one processor module for receiving an update information through a network; a storage module coupled to the processor The module is configured to execute a writing process on the storage module to store the update information in the storage module; a plurality of programmable logic modules are coupled to the storage module and shared The storage module and the plurality of first image processing modules are coupled to the plurality of programmable logic modules and simultaneously read the update stored by the storage module through the plurality of programmable logic modules Information for image processing of at least one target computer of the plurality of target computers. The KVM switch of claim 1, wherein the plurality of programmable logic modules are Field-Programmable Gate Arrays (FPGAs) or complex programmable logic Selected from the group consisting of Complex Programmable Logic Device (CPLD). The multi-computer switcher of claim 1, wherein the first image processing module of the plurality of first image processing modules comprises: an image processing circuit, and at least: a programmable logic The unit is disposed on the image processing circuit, and the programmable logic unit is coupled between the programmable logic module and the at least one target computer for transmitting the programmable mode from the storage module The group reads the update information and performs image processing on the at least one target computer. The KVM switch of claim 3, wherein the programmable logic unit is a Field-Programmable Gate Array (Field-Programmable Gate Array; FPGA) or Complex Programmable Logic Device (CPLD) is selected from the group consisting of. The KVM switch of claim 1, wherein the storage module is a flash memory. The KVM switch of claim 1, wherein the processor module is a Central Processing Unit (CPU). The multi-computer switcher of claim 1, further comprising: a switching module coupled to the processor module, the storage module and the plurality of programmable logic modules for Optionally, the processor module or one of the plurality of programmable logic modules is coupled to the storage module. The KVM switch of claim 7, wherein in the write-in mode, the switching module is switched to connect the processor module to the storage module, so that the processing is performed. The module can execute the writing process on the storage module to store the update information in the storage module. The KVM switch of claim 7, wherein in the Read-Out mode, the switching module is switched to the programmable logic module coupled to the storage module, such that The programmable logic module can read the update information from the storage module. The KVM switch of claim 7, wherein the switching module and the storage module transmit signals through a serial Peripheral Interface (SPI). The multi-computer switcher of claim 1, wherein the update information received by the processor module through the network includes a first information and a second information in the plurality of first images. The plurality of programmable logic modules are processed by the processing module through the plurality of programmable logic modules simultaneously reading the update information from the storage module Receiving the first information and the plurality of first image processing modules receive the second information. The multi-computer switcher of claim 1, further comprising: a plurality of second image processing modules respectively coupled to the plurality of first image processing modules and from the plurality of first image processing modules The group receives the update information. A method for updating a firmware of a KVM switch, the KVM switch comprising at least a processor module, a storage module, a plurality of programmable logic modules, and a plurality of first image processing modules, the plurality of The plurality of first image processing modules are respectively coupled to the plurality of programmable logic modules, and the firmware update method includes at least a plurality of programmable logic modules. The following steps are: (a) receiving, by the processor module, an update information through a network; (b) executing, by the processor module, a writing process on the storage module to store the update information in the storage module And (c) simultaneously reading the update information stored by the storage module by the plurality of first image processing modules through the plurality of programmable logic modules, and in the plurality of target computers At least one target computer performs image processing. The firmware updating method according to claim 13, wherein before the step (b) and the step (c), the firmware updating method further comprises the following steps: (b') selectively switching the processor module One or a plurality of programmable logic modules of the plurality of programmable logic modules are coupled to the storage module. The firmware update method of claim 14, wherein in the write-in mode, the step (b') is switched to the processor module coupled to the storage module, This firmware update method enables step (b) to be performed. The firmware update method of claim 14, wherein in a read-out mode, the step (b') is switched to the programmable logic module coupled to the storage module. So that the firmware update method can perform step (c). The firmware update method of claim 14, wherein the update information received by the processor module through the network includes a first information and a second information, and the process in step (c) The plurality of programmable logic modules receive the first information and the plurality of first image processing modules receive the second information. The firmware update method of claim 14, further comprising the steps of: (e) coupling a plurality of second image processing modules to the plurality of first image processing modules; and (f) Receiving the update information from the plurality of first image processing modules by the plurality of second image processing modules. An electronic device includes: a processor module for receiving an update information through a network; a storage module coupled to the processor module, the processor module executing the storage module Writing a program to store the update information in the storage module; a first function module having a plurality of first programmable logic elements capable of performing a first function, respectively coupled to the storage module Sharing the storage module for performing a first function; and a second function module having a plurality of second programmable logic elements for performing a second function, wherein the plurality of second programmable The plurality of first programmable logic elements of the first functional module are coupled to the storage module by the plurality of first programmable logic elements of the first functional module The update information stored by the group; wherein the plurality of first programmable logic elements of the first function module and the plurality of second programmable logic elements of the second function module are transmitted through a Sequence periphery Surface (Serial Peripheral Interface; SPI) for signal transmission.