CN106201325B

CN106201325B - Data access method, memorizer control circuit unit and memory storage apparatus

Info

Publication number: CN106201325B
Application number: CN201510211809.3A
Authority: CN
Inventors: 叶志刚; 林昌广
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2015-04-29
Filing date: 2015-04-29
Publication date: 2019-04-23
Anticipated expiration: 2035-04-29
Also published as: CN106201325A

Abstract

The present invention provides a kind of data access method, memorizer control circuit unit and memory storage apparatus.This method includes generating to correspond to the first check code of the first serial data and generate the first data acquisition system with the first check code of this corresponding the first serial data according to this first serial data using the first check code circuit.This method further includes the first check code for obtaining the first serial data with corresponding first serial data from the first data acquisition system using the second check code circuit, and verifies the first serial data using the first check code of corresponding first serial data.This method also includes generating according to checked first serial data the second check code using third check code circuit and generating data frame according to checked first serial data and the second check code, with write-in to entity program unit.The data access method that exemplary embodiment of the present invention is proposed can effectively ensure that the correctness of the data in transmission process in memorizer control circuit unit.

Description

Data access method, memorizer control circuit unit and memory storage apparatus

Technical field

The invention relates to a kind of data access methods, and in particular to for duplicative non-volatile memories A kind of data access method, memorizer control circuit unit and the memory storage apparatus of device.

Background technique

Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data non-volatile It is property, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built into above-mentioned illustrated various portable In multimedia device.

In general, be written to reproducible nonvolatile memorizer module data all can according to an error checking with Correcting code is to encode, and read data will also pass through corresponding program from reproducible nonvolatile memorizer module To decode.However, from host system receive data to write data into reproducible nonvolatile memorizer module it It can also happen that data bit-errors in the transmission process between (that is, inside memorizer control circuit unit), therefore, in order to ensure number It is the target that this field technical staff is endeavoured according to the correctness inside memorizer control circuit unit.

Summary of the invention

The present invention provides a kind of data access method, memorizer control circuit unit and memory storage apparatus, can The effectively correctness of verify data.

One example of the present invention embodiment provides a kind of data access method for memory storage apparatus.This memory Storage device has reproducible nonvolatile memorizer module, and reproducible nonvolatile memorizer module has multiple entities Erased cell, and each entity erased cell has multiple entity program units.Notebook data access method includes receiving first Serial data generates the first check code of this corresponding the first serial data using the first check code circuit and according to this first serial data The first data acquisition system is generated with the first check code of this corresponding the first serial data.Notebook data access method further includes using second Check code circuit obtains the first check code of the first serial data with corresponding first serial data from the first data acquisition system, and uses The first check code of the first serial data is corresponded to verify the first serial data.Notebook data access method also includes having verified according to correspondence The information of the first serial data the second check code is generated using third check code circuit, use error checking and correcting circuit Error checking and correcting code are generated, and according to checked first serial data, the second check code and error checking and correcting code To generate data frame.Notebook data access method further includes this data frame being written to first among those entity program units Entity program unit, wherein above-mentioned wherein the first check code circuit is to be different from third check code circuit.

In one example of the present invention embodiment, the length of the first check code is not less than the length of the second check code.

In one example of the present invention embodiment, above-mentioned data access method further include: receive the second serial data, use the One check code circuit generates the first check code of this corresponding the second serial data and according to the second serial data and corresponding second data First check code of string generates the second data set；And is obtained from the second data set using the second check code circuit First check code of two serial datas and corresponding second serial data, and verified using the first check code of corresponding second serial data Second serial data.Also, the above-mentioned information according to corresponding checked first serial data is generated using third check code circuit The step of second check code includes: to use third check code according to checked first serial data and checked second serial data Circuit generates the second check code.In addition, above-mentioned error checking and the correcting code of being generated using error checking and correcting circuit Step includes: to generate mistake using error checking and correcting circuit according to checked first data and checked second data Erroneous detection is looked into and correcting code.Furthermore it is above-mentioned to come according to checked first serial data, the second check code and error checking and correcting code The step of generating data frame includes: according to checked first serial data, checked second serial data, the second check code and mistake Erroneous detection is looked into correcting code and generates data frame.

In one example of the present invention embodiment, the size of the first check code of above-mentioned the first serial data of correspondence and corresponding The summation of the size of first check code of two serial datas is greater than the size of the second check code.

In one example of the present invention embodiment, the above-mentioned information according to corresponding checked first serial data uses third Check code circuit is including: according to checked first serial data and first instance sequencing list the step of generating the second check code The address information of member generates the second check code using third check code circuit.

In one example of the present invention embodiment, above-mentioned data access method further includes checked first serial data of compression To generate the first compressed data string.Also, the above-mentioned information according to corresponding checked first serial data is checked using third Code circuit is including: the first compressed data string according to corresponding checked first serial data the step of generating the second check code The second check code is generated using third check code circuit.In addition, above-mentioned generate mistake using error checking and correcting circuit Checking should with the first compressed data string use that the step of correcting code includes: corresponding checked first serial data of foundation Error checking generates the error checking and correcting code with correcting circuit.Furthermore it is above-mentioned according to checked first serial data, Two check codes include: according to corresponding checked first serial data the step of generating data frame with error checking and correcting code First compressed data string, the second check code and error checking and correcting code generate the data frame.

In one example of the present invention embodiment, above-mentioned data access method further includes checked first serial data of compression To generate the first compressed data string.Also, the above-mentioned information according to corresponding checked first serial data is checked using third Code circuit is including: the first compressed data string according to corresponding checked first serial data the step of generating the second check code The second check code is generated using third check code circuit with the address information of first instance programmed cell.In addition, above-mentioned make The step of error checking and correcting code are generated with correcting circuit with error checking includes: according to corresponding checked first number According to string this first compressed data string generate the error checking and correcting code using the error checking and correcting circuit.Again Person, it is above-mentioned according to checked first serial data, the second check code and error checking and correcting code come the step of generating data frame It include: the first compressed data string, the second check code and the error checking and correction according to corresponding checked first serial data Code generates the data frame.

In one example of the present invention embodiment, above-mentioned data access method further includes from first instance programmed cell Read data frame；And it is read according to the second check code in read data frame using third check code circuit to check Data frame in the first data.

One example of the present invention embodiment provides a kind of for controlling the storage of reproducible nonvolatile memorizer module Device control circuit unit comprising host interface, one first check code circuit, memory management circuitry, the second check code circuit, Third check code circuit, memory interface and error checking and correcting circuit.First check code circuit is electrically connected to host and connects Mouthful, memory management circuitry is electrically connected to the first check code circuit, and the second check code circuit is electrically connected to memory management Circuit, third check code circuit is electrically connected to the second check code circuit, and memory interface is electrically connected to third inspection Code and is electrically connected to reproducible nonvolatile memorizer module at circuit.Error checking and correcting circuit are electrically connected To memory management circuitry.Above-mentioned reproducible nonvolatile memorizer module has multiple entity erased cells, and each reality Body erased cell has multiple entity program units.Host interface receives the first serial data, the generation pair of the first check code circuit Answer the first check code of the first serial data, and memory management circuitry according to the first serial data and corresponding first serial data the One check code generates the first data acquisition system.Second check code circuit obtained from the first data acquisition system the first serial data with it is corresponding First check code of the first serial data, and the first serial data is verified using the first check code of corresponding first serial data.The Three check code circuits generate the second check code according to the information of corresponding checked first serial data.Error checking and correcting circuit Generate error checking and correcting code.Memory management circuitry is examined according to checked first serial data, the second check code and mistake It looks into correcting code and generates data frame, and this data frame is written to above-mentioned reality by memory interface for memory management circuitry First instance programmed cell among body programmed cell, wherein the first check code circuit is different from third check code circuit.

In one example of the present invention embodiment, host interface receives the second serial data, the generation pair of the first check code circuit Answer the first check code of the second serial data, first inspection of the memory management circuitry according to the second serial data and corresponding second serial data Code is looked into generate the second data set.In addition, the second check code circuit obtained from the second data set the second serial data with it is right The first check code of the second serial data is answered, and verifies the second serial data using the first check code of corresponding second serial data. Also, in above-mentioned generation error checking and the running of correcting code, third check code circuit is according to checked first data String generates above-mentioned second check code with checked second serial data.Also, it is above-mentioned according to checked first serial data, In second check code and error checking and running of the correcting code to generate data frame, memory management circuitry is according to checked First serial data, checked second serial data, the second check code and error checking and correcting code generate above-mentioned data frame.

In one example of the present invention embodiment, the information of checked first serial data is corresponded in above-mentioned foundation to generate In the running of second check code, third check code circuit is to generate the according to the address information of first instance programmed cell Two check codes.

In one example of the present invention embodiment, memorizer control circuit unit further includes being electrically connected to memory management The data compression circuit of circuit, to compress checked first serial data to generate the first compressed data string.Also, upper It states in running of the information of corresponding checked first serial data of foundation to generate the second check code, third check code circuit foundation Compressed data string generates the second check code for the first of corresponding checked first serial data.In addition, in above-mentioned generation mistake It checks in the running with correcting code, error checking with correcting circuit has been pressed according to the first of corresponding checked first serial data Contracting serial data generates error checking and correcting code.Furthermore it is above-mentioned according to checked first serial data, the second check code with In error checking and running of the correcting code to generate data frame, memory management circuitry is according to corresponding checked first serial data First compressed data string, the second check code and the error checking and correcting code generate data frame.

In one example of the present invention embodiment, memorizer control circuit unit further includes being electrically connected to memory management The data compression circuit of circuit, to compress checked first serial data to generate the first compressed data string.Also, upper It states in running of the information of corresponding checked first serial data of foundation to generate the second check code, third check code circuit foundation The address information of the first of corresponding checked first serial data compressed data string and first instance programmed cell generates Second check code.In addition, error checking is according to right with correcting circuit in above-mentioned generation error checking and the running of correcting code Answer the first of checked first serial data compressed data string generate error checking and correcting code.Furthermore in above-mentioned foundation In checked first serial data, the second check code and error checking and running of the correcting code to generate data frame, memory pipe Manage first compressed data string, second check code and error checking and correction of the circuit according to corresponding checked first serial data Code generates data frame.

One example of the present invention embodiment proposes a kind of memory storage apparatus comprising connecting interface unit can be made carbon copies Formula non-volatile memory module and above-mentioned memorizer control circuit unit.Connecting interface unit is electrically connected to host system System.Reproducible nonvolatile memorizer module has multiple entity program units.Memorizer control circuit unit electrically connects It is connected to connecting interface unit and reproducible nonvolatile memorizer module.

Based on above-mentioned, memorizer control circuit unit that exemplary embodiment of the present invention is proposed, memory storage apparatus and Its data access method used can effectively ensure that in memorizer control circuit unit the correct of data in transmission process Property, while avoiding the problem that the insufficient space in data supernumerary position area can not store a large amount of check codes.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Fig. 1 is the host system according to shown by an exemplary embodiment and memory storage apparatus；

Fig. 2 is computer, input/output device and memory storage apparatus shown by exemplary embodiment according to the present invention Schematic diagram；

Fig. 3 is the schematic diagram of host system and memory storage apparatus shown by exemplary embodiment according to the present invention；

Fig. 4 shows the schematic block diagram of memory storage apparatus shown in FIG. 1；

Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment；

Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to shown by an exemplary embodiment；

Fig. 8 is the example schematic of the data flow of execution write-in running according to shown by an exemplary embodiment；

Fig. 9 is the flow chart of the data access method according to shown by an exemplary embodiment.

Description of symbols:

1000: host system；

1100: computer；

1102: microprocessor；

1104: random access memory；

1106: input/output device；

1108: system bus；

1110: data transmission interface；

1202: mouse；

1204: keyboard；

1206: display；

1208: printer；

1210: mobile hard disk；

1212: storage card；

1214: solid state hard disk；

1310: digital camera；

1312:SD card；

1314:MMC card；

1316: memory stick；

1318:CF card；

1320: embedded storage device；

100: memory storage apparatus；

102: connecting interface unit；

104: memorizer control circuit unit；

106: reproducible nonvolatile memorizer module；

202: memory management circuitry；

204: host interface；

206: memory interface；

208: electric power management circuit；

210: buffer storage；

212: error checking and correcting circuit；

214: the first check code circuits；

216: the second check code circuits；

218: third check code circuit；

410 (0)~410 (N): entity erased cell；

506: system area；

502: data field；

504: idle area；

508: replacing area；

LA (0)~LA (H): logic unit；

LZ (0)~LZ (M): logic region；

D1, D2, D3, D4, D5, D6, D7, D8: serial data；

CRC1, CRC2, CRC3, CRC4, CRC5, CRC6, CRC7, CRC8: check code；

DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8: data acquisition system；

CI: control information；

NCRC: check code；

ECC: error checking and correcting code；

DF: data frame；

S901, S903, S905, S907, S909, S911, S913, S915: the step of data access method.

Specific embodiment

Fig. 1 is the host system according to shown by an exemplary embodiment and memory storage apparatus.

Fig. 1 is please referred to, host system 1000 generally comprises computer 1100 and input/output (input/output, abbreviation I/O) device 1106.Computer 1100 include microprocessor 1102, random access memory (random access memory, Abbreviation RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes the mouse such as Fig. 2 1202, keyboard 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input of device shown in Fig. 2/defeated Device 1106 out, input/output device 1106 can further include other devices.

In embodiments of the present invention, memory storage apparatus 100 is by data transmission interface 1110 and host system 1000 other components are electrically connected.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106 Running can write data into memory storage apparatus 100 or read data from memory storage apparatus 100.For example, depositing Reservoir storage device 100 can be mobile hard disk 1210 as shown in Figure 2, storage card 1212 or solid state hard disk (Solid State Drive, abbreviation SSD) 1214 equal type nonvolatile storage devices.

In general, host system 1000 is that can substantially cooperate appointing with storing data with memory storage apparatus 100 Meaning system.Although host system 1000 is explained with computer system, however, in the present invention in this exemplary embodiment Host system 1000 can be digital camera, video camera, communication device, audio player or video and broadcast in another exemplary embodiment Put the systems such as device.For example, when host system is digital camera (video camera) 1310, type nonvolatile storage Device is then its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or insertion Formula storage device 1320 (as shown in Figure 3).Embedded storage device 1320 include embedded multi-media card (Embedded MMC, Abbreviation eMMC).It is noted that embedded multi-media card is directly electrically connected on the substrate of host system.

Fig. 4 shows the schematic block diagram of memory storage apparatus shown in FIG. 1.

Referring to figure 4., memory storage apparatus 100 includes connecting interface unit 102, memorizer control circuit unit 104 With reproducible nonvolatile memorizer module 106.

In this exemplary embodiment, connecting interface unit 102 is compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, abbreviation SATA) standard.However, it is necessary to be appreciated that, the present invention is not limited to This, connecting interface unit 102 is also possible to meet parallel advanced technology annex (Parellel Advanced Technology Attachment, abbreviation PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, abbreviation IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, abbreviation PCI Express) standard, universal serial bus (Universal Serial Bus, abbreviation USB) standard, a ultrahigh speed generation (Ultra High Speed-I, abbreviation UHS-I) interface standard, superelevation Fast two generations (Ultra High Speed-II, abbreviation UHS-II) interface standard, secure digital (Secure Digital, abbreviation SD) interface standard, memory stick (Memory Stick, abbreviation MS) interface standard, multimedia storage card (Multi Media Card, abbreviation MMC) interface standard, compact flash (Compact Flash, abbreviation CF) interface standard, integrated driving electronics connect Mouth (Integrated Device Electronics, abbreviation IDE) standard or other suitable standard.In this exemplary embodiment In, connecting interface unit can be encapsulated in a chip with memorizer control circuit unit, or is laid in one and is included memory control Outside the chip of circuit unit processed.

Memorizer control circuit unit 104 is to execute in the form of hardware or multiple logic gates of form of firmware implementation or control System instruction, and data are carried out in reproducible nonvolatile memorizer module 106 according to the instruction of host system 1000 The running such as be written, read and erase.

Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and uses The data being written with host system 1000.Reproducible nonvolatile memorizer module 106 has entity erased cell 410 (0)~410 (N).For example, entity erased cell 410 (0)~410 (N) can belong to the same memory crystal grain (die) or Belong to different memory crystal grains.Each entity erased cell is respectively provided with a plurality of entity program units, wherein belonging to same The entity program unit of one entity erased cell can be written independently and simultaneously be erased.However, it is necessary to understand It is that the invention is not limited thereto, each entity erased cell is can be by 64 entity program units, 256 entity program lists First or other any entity program units are formed.

In more detail, entity erased cell is the minimum unit erased.That is, each entity erased cell contains minimum The storage unit of number being erased together.Entity program unit is the minimum unit of sequencing.That is, entity program unit For the minimum unit that data are written.Each entity program unit generally includes data bit area and redundant digit area.Data bit area packet Data containing multiple entity access addresses to store user, and redundant digit area to storage system data (for example, control Information and error correcting code).It can include 8 in the data bit area of each entity program unit in this exemplary embodiment Entity access address, and the size of an entity access address is 512 bytes (byte).However, in other exemplary embodiments, It also may include the more or fewer entity access addresses of number in data bit area, the present invention is not intended to limit the big of entity access address Small and number.For example, entity erased cell is physical blocks, and entity program unit is in an exemplary embodiment Physical page or entity sector, but invention is not limited thereto.

In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi Level Cell, abbreviation MLC) NAND-type flash memory module be (that is, can store the flash memory mould of 2 data bit in a storage unit Block).However, the invention is not limited thereto, reproducible nonvolatile memorizer module 106 can also be single-order storage unit (Single Level Cell, abbreviation SLC) NAND-type flash memory module is (that is, can store 1 data bit in a storage unit Flash memory module), Complex Order storage unit (Trinary Level Cell, abbreviation TLC) NAND-type flash memory module is (that is, one is deposited The flash memory module of 3 data bit can be stored in storage unit), other flash memory modules or other memory moulds with the same characteristics Block.

Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment.

Referring to figure 5., memorizer control circuit unit 104 includes memory management circuitry 202, host interface 204, storage Device interface 206, electric power management circuit 208, buffer storage 210, error checking and correcting circuit 212, the first check code circuit 214, the second check code circuit 216 and third check code circuit 218.

Overall operation of the memory management circuitry 202 to control memorizer control circuit unit 104.Specifically, it deposits Reservoir, which manages circuit 202, has multiple control instructions, and when memory storage apparatus 100 operates, these control instruction meetings It is executed to write duplicative non-volatile memory module and assigns instruction, to carry out the write-in of data, read and erase Running.

In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with form of firmware.For example, Memory management circuitry 202 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 100 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.

Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to shown by an exemplary embodiment.

Fig. 6 is please referred to, memorizer control circuit unit 104 (or memory management circuitry 202) can be by entity erased cell 410 (0)~410- (N) are logically grouped into data field 502, idle area 504, system area 506 and replace area 508.

The entity erased cell for logically belonging to data field 502 and idle area 504 is to store from host system 1000 data.Specifically, the entity erased cell of data field 502 is regarded as the entity erased cell of storing data, And the entity erased cell in idle area 504 is the entity erased cell to replacement data area 502.That is, working as from host When system 1000 receives write instruction and the data to be written, memory management circuitry 202 can be extracted real from idle area 504 Body erased cell, and writing data into extracted entity erased cell is erased list with the entity in replacement data area 502 Member.

The entity erased cell for logically belonging to system area 506 is to record system data.For example, system data includes Entity about the manufacturer of reproducible nonvolatile memorizer module and model, reproducible nonvolatile memorizer module Erased cell number, entity program unit number of each entity erased cell etc..

Logically belonging to replace the entity erased cell in area 508 is to replace program for bad entity erased cell, to take The entity erased cell of generation damage.Specifically, still there are normal entity erased cell and data if replacing in area 508 When the entity erased cell damage in area 502, memory management circuitry 202 can extract normal entity from substitution area 508 and erase Unit replaces the entity erased cell of damage.

In particular, the quantity meeting of data field 502, idle area 504, system area 506 and the entity erased cell for replacing area 508 It is different according to different memory specifications.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 100, Entity erased cell is associated with to data field 502, idle area 504, system area 506 and replaces the grouping relationship in area 508 can be dynamically It changes.For example, when the entity erased cell that the entity erased cell damage in idle area 504 is substituted area 508 replaces, then Replace the entity erased cell in area 508 that can be associated to idle area 504 originally.

Fig. 7 is please referred to, memorizer control circuit unit 104 (or memory management circuitry 202) can configuration logic unit LA (0)~LA (H) with the entity erased cell in Image Data area 502, wherein each logic unit have multiple logical subunits with The entity program unit of the corresponding entity erased cell of image.Also, work as the logic unit to be write data to of host system 100 Or when updating storage data in logical units, memorizer control circuit unit 104 (or memory management circuitry 202) can be from An entity erased cell is extracted data are written, with the entity erased cell of alternation data field 502 in idle area 504.At this In exemplary embodiment, logical subunit can be logical page (LPAGE) or logic sector.

In order to identify that the data of each logic unit of data are stored in that entity erased cell, in this exemplary embodiment In, memorizer control circuit unit 104 (or memory management circuitry 202) will record between logic unit and entity erased cell Image.Also, when host system 1000 is intended to access data in logical subunit, memorizer control circuit unit 104 (or Memory management circuitry 202) it can confirm logic unit belonging to this logical subunit, and in the reality of this logic unit institute image Data are accessed in body erased cell.For example, in this exemplary embodiment, memorizer control circuit unit 104 (or memory pipe Reason circuit 202) storage logic it can turn physical address mapping table in reproducible nonvolatile memorizer module 106 to record often The entity erased cell of one logic unit institute image, and when data to be accessed memorizer control circuit unit 104 (or storage Device manages circuit 202) logic can be turned physical address mapping table and be loaded onto buffer storage 210 to safeguard.

Reflecting for all logic units is recorded it is noted that can not store since the capacity of buffer storage 210 is limited As the mapping table of relationship, therefore, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) logic unit LA (0)~LA (H) can be grouped into multiple logic region LZ (0)~LZ (M), and be each logic region It configures a logic and turns physical address mapping table.In particular, when (or the memory management circuitry of memorizer control circuit unit 104 202) when being intended to update the image of some logic unit, the logic of logic region belonging to this corresponding logic unit turns physical address and reflects It is updated as table can be loaded on buffer storage 210.

As described above, in this exemplary embodiment, the type nonvolatile mould of memory storage apparatus 100 Block 106 is managed based on the page, therefore, when executing write instruction, regardless of current data are to be written to that The logical subunit of a logic unit, memorizer control circuit unit 104 (or memory management circuitry 202) all can be with a realities Body programmed cell connects the mode of an entity program unit data (hereinafter also referred to random writing mechanism) is written.Tool For body, memorizer control circuit unit 104 (or memory management circuitry 202) can be extracted from idle area 504 one it is empty Data are written as entity erased cell used at present (also referred to as actuation entity erased cell) in entity erased cell.And And when this entity erased cell used at present has been fully written, memorizer control circuit unit 104 (or memory management electricity Road 202) another empty entity erased cell can be extracted from idle area 504 again as entity erased cell used at present, To continue to write to the data of the corresponding write instruction from host system 1000.In particular, in order to avoid the reality in area 504 of leaving unused Body erased cell is depleted, when memorizer control circuit unit 104 (or memory management circuitry 202) is intended to from idle area 504 The number for extracting entity erased cell and the entity erased cell in idle area 504 drops to set garbage recycling door When value, memorizer control circuit unit 104 (or memory management circuitry 202) can first carry out data consolidation procedure, to make data Data at least one entity erased cell in area 502 become invalid data, and the data that will be stored in data field 502 It is all that the entity erased cell of invalid data is associated with go back to idle area 504, so that the number of the entity erased cell in idle area 504 Threshold value is recycled greater than set garbage.For example, when executing data consolidation procedure, memorizer control circuit unit 104 (or memory management circuitries 202) are at least needed using an empty entity erased cell, and therefore, garbage reclamation threshold value is extremely It can be set to be greater than 1 numerical value less.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also be with program code shape Formula is stored in the specific region of reproducible nonvolatile memorizer module 106 (for example, being exclusively used in storage system in memory module The system area for data of uniting) in.In addition, memory management circuitry 202 has microprocessor unit (not shown), read-only memory (not shown) and random access memory (not shown).In particular, this read-only memory has driving code, and work as memory control When circuit unit 104 processed is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in property memory module 106 is loaded onto the random access memory of memory management circuitry 202.Later, micro- Processor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.

In addition, the control instruction of memory management circuitry 202 can also be with a hardware in another exemplary embodiment of the present invention Form carrys out implementation.For example, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is electrically connected to microcontroller.Wherein, it stores Entity erased cell of the Single Component Management circuit to manage reproducible nonvolatile memorizer module 106；Memory write-in electricity Road writes data into non-volatile to duplicative to assign write instruction to reproducible nonvolatile memorizer module 106 In property memory module 106；Memory reading circuitry refers to assign reading to reproducible nonvolatile memorizer module 106 It enables to read data from reproducible nonvolatile memorizer module 106；Memory erases circuit to non-to duplicative Volatile 106 assigns instruction of erasing so that data to be erased from reproducible nonvolatile memorizer module 106； And data processing circuit is intended to be written data to reproducible nonvolatile memorizer module 106 and from can make carbon copies to handle The data read in formula non-volatile memory module 106.

Referring again to Fig. 5, host interface 204 is electrically connected to memory management circuitry 202 and to receive and know The instruction and data that other host system 1000 is transmitted.That is, the instruction that host system 1000 is transmitted can lead to data Host interface 204 is crossed to be sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is compatible with SATA standard.However, it is necessary to be appreciated that the invention is not limited thereto, host interface 204 be also possible to be compatible with PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS Standard, MMC standard, CF standard, IDE standard or other suitable data transmission standard.

Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative Property memory module 106.It can be by depositing to the data of reproducible nonvolatile memorizer module 106 that is, being intended to be written Memory interface 206 is converted to the 106 receptible format of institute of reproducible nonvolatile memorizer module.

Electric power management circuit 208 is electrically connected to memory management circuitry 202 and to control memory storage dress Set 100 power supply.

Buffer storage 210 is electrically connected to memory management circuitry 202 and is configured to temporarily store from host system 1000 data and instruction or the data from reproducible nonvolatile memorizer module 106.

Error checking and correcting circuit 212 are electrically connected to memory management circuitry 202 and to execute wrong inspection It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 202 connects from host system 1000 When receiving write instruction, error checking can generate corresponding mistake with correcting circuit 212 for the data of this corresponding write instruction and examine Look into correcting code (Error Checking and Correcting Code, abbreviation ECC Code), and memory management electricity The data of this corresponding write instruction can be written with correcting code to duplicative is non-volatile with corresponding error checking and be deposited by road 202 In memory modules 106.Later, when memory management circuitry 202 reads number from reproducible nonvolatile memorizer module 106 According to when can read the corresponding error checking of this data and correcting code simultaneously, and error checking and correcting circuit 212 can be according to these Error checking and correcting code execute error checking and correction program to read data.

First check code circuit 214 and the second check code circuit 216 are to ensure institute in memorizer control circuit unit 104 The correctness of the data of transmission.In this exemplary embodiment, the first check code circuit 214 is phase with the second check code circuit 216 Same circuit, and configure in memorizer control circuit unit 104 at host interface 204 or memory interface 206.Tool For body, pass through host interface 204 after receiving data in host system 1000 in memory management circuitry 202, first Check code circuit 214 can generate corresponding check code according to this data.Later, pass through memory in memory management circuitry 202 Interface 206 transfers data to before reproducible nonvolatile memorizer module 106, and the second check code circuit 216 can be according to right This data of the inspection code check of this data are answered, to ensure the correctness of data.For example, the first check code circuit 214 and the second inspection Looking into yard circuit 216 is the circuit using cyclic redundancy check (Cycle Redundancy Check, abbreviation CRC) technology implementation. In another exemplary embodiment, the second check code circuit 216 can also be configuration in reproducible nonvolatile memorizer module 106 In.

Third check code circuit 218 is electrically connected to the second check code circuit 216.In this exemplary embodiment, third Check code circuit 218 to for by the second check code circuit 216 complete verification data regenerate new check code, and Checked data and new check code are sent to reproducible nonvolatile memorizer module 106 to carry out sequencing running (that is, write-in running).For example, third check code circuit 218 is the circuit using cyclic redundancy check technology implementation.

In one exemplary embodiment of this example, the checking feature of the first check code circuit 214 and the second check code circuit 216 It is the checking feature different from third check code circuit 218.Specifically, the first check code circuit 214 and the second check code electricity Road 216 is to generate correspondence proving code for data as unit of the first preset data length, and third check code circuit 218 is with the Two preset data length are that unit to generate correspondence proving code for data.For example, in an exemplary embodiment, the first preset data Length is that check code caused by 512 bytes (Bytes) and the first check code circuit 214 and the second check code circuit 216 is 2 Byte；And the second preset data length is to check caused by 4 kilobytes (Kilobytes) and third check code circuit 216 The length of code is 2 bytes.

In particular, third check code circuit 218 can also be with the entity program unit to be written in an exemplary embodiment Address as generate check code parameter, thus can confirm when reading data received by data whether be from correct It is read in address.

Fig. 8 is the example schematic of the data flow of execution write-in running according to shown by an exemplary embodiment.

Please referring to Fig. 8, it is assumed that host system 1000 is intended to store the data of 4 kilobytes to memory storage apparatus 100, and Host system 1000 is to transmit data as unit of 512 bytes.When memorizer control circuit unit 104 (or host interface 204) Write instruction is received from host system 1000 and data length is the first stroke data (hereinafter referred to as serial data D1) of 512 bytes When, the first check code circuit 214 can generate corresponding check code CRC1 according to serial data D1.Later, memory management circuitry 202 The data acquisition system DS1 comprising serial data D1 and check code CRC1 can be handled and data acquisition system DS1 is temporarily stored in buffer storage In 210.

Then, memorizer control circuit unit 104 (or host interface 204) receives data length from host system 1000 For 512 bytes second data (hereinafter referred to as serial data D2) when, the first check code circuit 214 can according to serial data D2 generate Corresponding check code CRC2.Later, memory management circuitry 202 can handle the data set comprising serial data D2 Yu check code CRC2 It closes DS2 and data acquisition system DS2 is temporarily stored in buffer storage 210.

Then, memorizer control circuit unit 104 (or host interface 204) receives data length from host system 1000 For 512 bytes third data (hereinafter referred to as serial data D3) when, the first check code circuit 214 can according to serial data D3 generate Corresponding check code CRC3.Later, memory management circuitry 202 can handle the data set comprising serial data D3 Yu check code CRC3 It closes DS3 and data acquisition system DS3 is temporarily stored in buffer storage 210.

Then, memorizer control circuit unit 104 (or host interface 204) receives data length from host system 1000 For 512 bytes the 4th data (hereinafter referred to as serial data D4) when, the first check code circuit 214 can according to serial data D4 generate Corresponding check code CRC4.Later, memory management circuitry 202 can handle the data set comprising serial data D4 Yu check code CRC4 It closes DS4 and data acquisition system DS4 is temporarily stored in buffer storage 210.

Then, memorizer control circuit unit 104 (or host interface 204) receives data length from host system 1000 For 512 bytes the 5th data (hereinafter referred to as serial data D5) when, the first check code circuit 214 can according to serial data D5 generate Corresponding check code CRC5.Later, memory management circuitry 202 can handle the data set comprising serial data D5 Yu check code CRC5 It closes DS5 and data acquisition system DS5 is temporarily stored in buffer storage 210.

Then, memorizer control circuit unit 104 (or host interface 204) receives data length from host system 1000 For 512 bytes the 6th data (hereinafter referred to as serial data D6) when, the first check code circuit 214 can according to serial data D2 generate Corresponding check code CRC6.Later, memory management circuitry 202 can handle the data set comprising serial data D6 Yu check code CRC6 It closes DS6 and data acquisition system DS6 is temporarily stored in buffer storage 210.

Then, memorizer control circuit unit 104 (or host interface 204) receives data length from host system 1000 For 512 bytes the 7th data (hereinafter referred to as serial data D7) when, the first check code circuit 214 can according to serial data D7 generate Corresponding check code CRC7.Later, memory management circuitry 202 can handle the data set comprising serial data D7 Yu check code CRC7 It closes DS7 and data acquisition system DS7 is temporarily stored in buffer storage 210.

Then, memorizer control circuit unit 104 (or host interface 204) receives data length from host system 1000 For 512 bytes the 8th data (hereinafter referred to as serial data D8) when, the first check code circuit 214 can according to serial data D8 generate Corresponding check code CRC8.Later, memory management circuitry 202 can handle the data set comprising serial data D8 Yu check code CRC8 It closes DS8 and data acquisition system DS8 is temporarily stored in buffer storage 210.

In an exemplary embodiment, after all data for receiving this corresponding write instruction, memorizer control circuit Just transmittable confirmation message can be transmitted next unit 104 (or memory management circuitry 202) again to host system 1000 with informing A instruction.However, the invention is not limited thereto, in another exemplary embodiment, memorizer control circuit unit 104 (or memory Manage circuit 202) received write instruction can also executed by Data programming to duplicative non-volatile memories After device module 106, confirmation message is just transmitted to host system 1000.

Later, refer to when memorizer control circuit unit 104 (or memory management circuitry 202) will execute the received write-in of institute It enables, when by received serial data D1~D8 sequencing to reproducible nonvolatile memorizer module 106, memory control Circuit unit 104 (or memory management circuitry 202) processed can select an empty entity program in actuation entity erased cell Change unit (hereinafter referred to as first instance programmed cell) serial data D1~D8 is written, and generates corresponding control information CI (for example, the information such as corresponding logical address).

In particular, the data acquisition system DS1~DS8 for being temporarily stored into buffer storage 210 can be sent to the second check code circuit 216, and the second check code circuit 216 can verify corresponding serial data according to the check code in each data acquisition system, with true Protect the serial data inerrancy position in data acquisition system.Specifically, the second check code circuit 216 can be verified according to check code CRC1 Serial data D1, to confirm serial data D1 in transmission process without generation mistake.Similarly, the second check code circuit 216 can basis Check code CRC2~CRC8 verifies serial data D2~D8.

In particular, being written by checked serial data D1~D8 to before first instance programmed cell, error checking It can be the corresponding error checking of checked serial data D1~D8 generations and correcting code ECC with correcting circuit 212, and third inspection Corresponding check code NCRC can be generated for checked serial data D1~D8 by looking into yard circuit 218.As described above, third check code electricity Road 218 is that (for example, 4 kilobytes) generate check code as unit of the second preset length.Therefore, third check code circuit 218 It is that a corresponding check code is generated according to checked serial data D1~D8.For example, in an exemplary embodiment, third inspection Look into yard circuit 218 can according to the address information of the first instance programmed cell for being intended to store checked serial data D1~D8 or/ And the content of checked serial data D1~D8 generates check code NCRC.

Finally, memorizer control circuit unit 104 (or memory management circuitry 202) can will include checked serial data D1~D8, information CI, check code NCRC and error checking and the data frame DF sequencing of correcting code ECC are controlled to first instance journey Sequence unit.Specifically, checked serial data D1~D8 can be programmed into the data bit of first instance programmed cell Area, and control information CI, check code NCRC and error checking and correcting code ECC and can be programmed into redundant digit area.

For example, when host system 1000 assigns reading instruction to read the data being stored in first instance programmed cell When, memorizer control circuit unit 104 (or memory management circuitry 202) can read data from first instance programmed cell Frame DF.Error checking and correcting circuit 212 can carry out wrong school to serial data D1~D8 according to error checking and correcting code ECC Positive program, with the error bit in correction data string D1~D8.Then, the serial data D1~D8 and check code NCRC corrected can quilt It send to third check code circuit 216.Third check code circuit 216 can verify serial data D1~D8 according to check code NCRC.Example Such as, as described above, check code NCRC can be generated according to the address information of first instance programmed cell, therefore, pass through this school It tests, can confirm whether received data are the data for being stored in first instance programmed cell.Later, the second check code electricity Road 214 respectively can generate corresponding check code CRC1~CRC8 for checked serial data D1~D8.Then, memory controls Circuit unit 104 (or memory management circuitry 202) meeting will be respectively containing serial data D1~D8's and check code CRC1~CRC8 Data acquisition system DS1~DS8 is kept in buffer storage 210, and in order one then one send host system 1000 to Instruction is read to respond this.In particular, serial data can be transferred into the first inspection before transmitting data by host interface 204 Yard circuit 214 is looked into, and the first check code circuit 214 will use corresponding check code to verify serial data, to ensure to send to The correctness of the data of host system 1000.For example, before sending serial data D1 to host system 1000, the first check code Circuit 214 can verify serial data D1 according to the check code CRC1 in data acquisition system DS1, and the serial data D1 after verification Host system 1000 can be sent to by host interface 204.Similarly, before transmitting data acquisition system DS2~DS8, first is checked Code circuit 214 can carry out school to data acquisition system DS2~DS8 according to check code CRC2~CRC8 in data acquisition system DS2~DS8 It tests.

It will be appreciated that although error checking and correcting circuit 212 are before data check in this exemplary embodiment Error-correcting routine is carried out, but the invention of this hair is without being limited thereto.In another exemplary embodiment, error checking and correcting circuit 212 Error-correcting routine can also be carried out after data check.

Third check code circuit third check code circuit the second check code circuit the first check code circuit the first check code electricity Road the first check code circuit the first check code circuit is as described above, can according to check code caused by the first check code circuit 214 Whether mistake occurs when transmitting in memorizer control circuit unit 104 with verify data string.However, according to host system 1000 Data transmission unit (for example, 512 bytes) generate check code (that is, the inspection as caused by the first check code circuit 214 Code) example in, by data with the size (for example, 4 kilobytes) of entity program unit be unit execute sequencing when, greatly The check code of amount can occupy the space in redundant digit area, be likely to result in redundant digit area without sufficient space and store control information or mistake Inspection and correcting code.In this exemplary embodiment, before serial data is sent to reproducible nonvolatile memorizer module, School first can be carried out to serial data according to corresponding check code with the identical second check code circuit 216 of the first check code circuit 214 It tests, third check code circuit 218 generates a check code (such as the example institute of Fig. 8 for checked more serial datas again later It states).Base this, while can avoid the problem that again redundant digit area insufficient space in the correctness that ensuring data transmission.

It is noted that memorizer control circuit unit 104 may also include data compression in another exemplary embodiment Circuit, so that data bit area can store serial data of more pens from host system 1000 and save the sky in more redundant digit areas Between.Specifically, the serial data (for example, first serial data) that data compression circuit can be verified the second check code circuit 216 Third check code circuit 218 is just sent to after being compressed into compressed data (for example, first compressed data string).For example, being with Fig. 8 Example, an entity program unit can store 8 serial datas, and the total length of corresponding 8 serial datas is the check code of 16 bytes It can be replaced with the check code that data length is 2 bytes, the space saved is 14 bytes.If data length is 512 bytes When serial data all can be compressed as the serial data of 128 bytes, an entity program unit will store 16 serial datas, and right The total length for answering 16 serial datas is the check code of 32 bytes to be replaced with check code that data length is 2 bytes, is saved Space is 30 bytes.

Fig. 9 is please referred to, in step S901, host interface 204 receives serial data (hereinafter referred to as from host system 1000 First serial data).In step S903, the first check code circuit 214 can generate the check code of corresponding first serial data (hereinafter referred to as For the first check code) and memorizer control circuit unit 104 (or memory management circuitry 202) can according to the first serial data with The first check code of the first serial data is corresponded to generate the first data acquisition system.

In step S905, host interface 204 receives another serial data (the hereinafter referred to as second number from host system 1000 According to string).In step s 907, the first check code circuit 214 can generate the first check code of corresponding second serial data and store Device control circuit unit 104 (or memory management circuitry 202) can be according to the second serial data and the first of corresponding second serial data Check code generates the second data set.

In step S909, memorizer control circuit unit 104 (or memory management circuitry 202) selects an empty reality Body programmed cell (hereinafter referred to as first instance programmed cell) is ready for sequencing.

In step S911, the second check code circuit 216 obtains the first serial data and corresponding from the first data acquisition system First check code of one serial data, and the first serial data is verified using the first check code of corresponding first serial data；And The first check code of the second serial data with corresponding second serial data is obtained from the second data set, and uses corresponding second number The second serial data is verified according to the first check code of string.

Later, in step S913, third check code circuit 218 can be verified according to the second check code circuit 216 has been passed through The first serial data and the second serial data generate new check code (hereinafter referred to as the second check code).For example, in example reality It applies in example, third check code circuit 218 can be according to the address of the first serial data, the second serial data and first instance programmed cell Information generates the second check code, thus can confirm whether read data be storage according to check results when reading data Data in first instance programmed cell.In addition, as described above, the checking feature of third check code circuit 218 is different In the first check code circuit 214 and the second check code circuit 216, therefore, the first of corresponding first serial data and the second serial data The size of check code can be less than the size of the second check code.In another exemplary embodiment, corresponding first serial data and the second number It is not less than the length of the second check code according to the length of the first check code of string.

In step S915, memorizer control circuit unit 104 (or memory management circuitry 202) can be according to checked First serial data and the second serial data and the second check code generate data frame, and by memory interface 206 by data Frame is written to first instance programmed cell.

It will be appreciated that the exemplary flow of Fig. 9 be with from host system 1000 receive two serial datas after by this two Serial data is described for being written together to entity program unit, however the invention is not limited thereto.For example, in another example In embodiment, memorizer control circuit unit 104 can also be carried out above procedureization running only receiving a serial data.Example Such as, above-mentioned steps S903 can be omitted, and the second check code circuit 216 only verifies the first serial data, third check code circuit 218 according to Generate new check code according to the first serial data, and memorizer control circuit unit 104 (or memory management circuitry 202) according to Data frame is generated according to checked first serial data and the second check code, and is write data frame by memory interface 206 Enter to first instance programmed cell.In addition, memorizer control circuit unit 104 can also connect in another exemplary embodiment After receiving more serial datas, above procedure running is just carried out.

In conclusion data access method provided by the present invention, memorizer control circuit unit and memory storage fill It sets, can effectively ensure that the correctness of the data in transmission process in memorizer control circuit unit, while avoiding data superfluous The insufficient space in the area Yuan Wei can not store the problem of a large amount of check codes.In addition, data access method provided by the present invention, storage Device control circuit unit and memory storage apparatus can regenerate check code according to sequencing address, therefore, operate reading When, read error can be effectively prevented from.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims

1. a kind of data access method is used for a memory storage apparatus, which is characterized in that the memory storage apparatus has There are multiple entities to erase list for one reproducible nonvolatile memorizer module, the reproducible nonvolatile memorizer module Member, and each of entity erased cell has multiple entity program units, the data access method includes:

One first serial data is received, one first check code of corresponding first serial data is generated using one first check code circuit And one first data set is generated with first check code of corresponding first serial data according to first serial data It closes；

First serial data and corresponding described first are obtained from first data acquisition system using one second check code circuit First check code of serial data, and described is verified using first check code of correspondence first serial data One serial data；

An information according to corresponding checked first serial data generates one second inspection using third check code circuit Code；

An error checking and correcting code are generated using an error checking and correcting circuit；

A number is generated according to checked first serial data, second check code and the error checking and correcting code According to frame；And

The first instance programmed cell to those entity program units is written into the data frame,

Wherein the first check code circuit is different from the third check code circuit.

2. data access method according to claim 1, which is characterized in that the length of first check code is not less than institute State the length of the second check code.

3. data access method according to claim 1, which is characterized in that further include:

One second serial data is received, generate corresponding second serial data using the first check code circuit one first checks Code and generate one second data with first check code of corresponding second serial data according to second serial data Set；And

Second serial data and corresponding described are obtained from the second data set using the second check code circuit First check code of two serial datas, and verified using first check code of correspondence second serial data described Second serial data,

Wherein the information according to corresponding checked first serial data is generated using the third check code circuit The step of second check code includes: to make according to checked first serial data and checked second serial data Second check code is generated with the third check code circuit,

Wherein generated the step of the error checking and correcting code using the error checking and correcting circuit includes: according to First data and checked second data of verification are generated described using the error checking and correcting circuit Error checking and correcting code,

Wherein generated according to checked first serial data, second check code with the error checking and correcting code The step of data frame includes: according to checked first serial data, checked second serial data, described Two check codes and the error checking generate the data frame with correcting code.

4. data access method according to claim 3, which is characterized in that described the first of corresponding first serial data The size of check code is greater than described second with the summation of the size of first check code of corresponding second serial data and checks The size of code.

5. data access method according to claim 1, which is characterized in that

The information according to corresponding checked first serial data is generated described using the third check code circuit The step of second check code includes:

Address information according to the first instance programmed cell generates described second using the third check code circuit Check code.

6. data access method according to claim 1, which is characterized in that further include:

Compress checked first serial data to generate one first compressed data string,

Wherein the information according to corresponding checked first serial data is generated using the third check code circuit The step of second check code includes:

Compressed data string uses the third check code electricity to described the first of corresponding checked first serial data of foundation Road generates second check code,

The error checking is wherein generated with correcting circuit with the step of correcting code using the error checking includes:

Compressed data string uses the error checking and school to described the first of corresponding checked first serial data of foundation Positive circuit generates the error checking and correcting code,

Wherein generated according to checked first serial data, second check code with the error checking and correcting code The step of data frame includes:

According to corresponding checked first serial data described first compressed data string, second check code with it is described Error checking generates the data frame with correcting code.

7. data access method according to claim 1, which is characterized in that further include:

Wherein the information according to corresponding checked first serial data is generated described using third check code circuit The step of second check code includes:

The described first compressed data string and first instance sequencing according to corresponding checked first serial data The address information of unit generates second check code using the third check code circuit,

8. data access method according to claim 1, which is characterized in that further include:

The data frame is read from the first instance programmed cell；And

It is read according to second check code in the read data frame using the third check code circuit to check First data in the data frame taken.

9. a kind of memorizer control circuit unit, for controlling a reproducible nonvolatile memorizer module, which is characterized in that The memorizer control circuit unit includes:

One host interface；

One first check code circuit, is electrically connected to the host interface；

One memory management circuitry is electrically connected to the first check code circuit；

One error checking and correcting circuit are electrically connected to the memory management circuitry；

One second check code circuit, is electrically connected to the memory management circuitry；

One third check code circuit, is electrically connected to the second check code circuit；And

One memory interface is electrically connected to the third check code circuit and to be electrically connected to the duplicative non- Volatile, wherein the reproducible nonvolatile memorizer module, the non-hair property memory of duplicative Module has multiple entity erased cells, and each entity erased cell has multiple entity program units,

Wherein the host interface receives one first serial data, and the first check code circuit generates corresponding first serial data One first check code,

Wherein first inspection of the memory management circuitry according to first serial data and corresponding first serial data Code is looked into generate one first data acquisition system,

Wherein the second check code circuit obtains first serial data and corresponding described from first data acquisition system First check code of one serial data, and verified using first check code of correspondence first serial data described First serial data,

Wherein the third check code circuit generates one second according to corresponding checked first serial data, one information and checks Code,

Wherein the error checking and correcting circuit generate an error checking and correcting code,

Wherein the memory management circuitry is according to checked first serial data, second check code and the mistake It checks with correcting code and generates a data frame,

Wherein the data frame is written to those entity programs by the memory interface for the memory management circuitry A first instance programmed cell among unit,

10. memorizer control circuit unit according to claim 9, which is characterized in that the length of first check code Not less than the length of second check code.

11. memorizer control circuit unit according to claim 9, which is characterized in that

The host interface receives one second serial data,

Wherein the first check code circuit generates one first check code of corresponding second serial data,

Wherein first inspection of the memory management circuitry according to second serial data and corresponding second serial data Code is looked into generate a second data set,

Wherein the second check code circuit obtains second serial data and corresponding described from the second data set First check code of two serial datas, and verified using first check code of correspondence second serial data described Second serial data,

Wherein in the above-mentioned generation error checking and the running of correcting code, the third check code circuit is that foundation has verified First data and checked second data generate the mistake using the error checking and correcting circuit Inspection and correcting code,

Wherein above-mentioned according to checked first serial data, second check code and the error checking and correcting code In running to generate the data frame, the memory management circuitry is according to checked first serial data, the school Second serial data, second check code tested generate the data frame with the error checking and correcting code.

12. memorizer control circuit unit according to claim 11, which is characterized in that corresponding first serial data The size of first check code is greater than described with the summation of the size of first check code of corresponding second serial data The size of second check code.

13. memorizer control circuit unit according to claim 9, which is characterized in that

The running of second check code is generated in the above-mentioned information according to corresponding checked first serial data In, the third check code circuit is the address information according to the first instance programmed cell using the third check code Circuit generates second check code.

14. memorizer control circuit unit according to claim 9, which is characterized in that further include:

One data compression circuit is electrically connected to the memory management circuitry, and to compress checked first number According to string to generate one first compressed data string,

Wherein second check code is generated according to the information for corresponding to checked first serial data above-mentioned In running, the third check code circuit is the described first compressed data according to corresponding checked first serial data String generates second check code using the third check code circuit,

Wherein in the above-mentioned generation error checking and the running of correcting code, the error checking is according to right with correcting circuit Answer described the first of checked first serial data compressed data string produced using the error checking with correcting circuit The raw error checking and correcting code,

Wherein above-mentioned according to checked first serial data, second check code and the error checking and correcting code In running to generate the data frame, the memory management circuitry is according to corresponding checked first serial data Described first compressed data string, second check code and the error checking and correcting code generate the data frame.

15. memorizer control circuit unit according to claim 9, which is characterized in that further include:

Wherein second check code is generated according to the information for corresponding to checked first serial data above-mentioned In running, the third check code circuit is the described first compressed data according to corresponding checked first serial data The address information of string and the first instance programmed cell is generated described second using the third check code circuit and checked Code,

16. memorizer control circuit unit according to claim 9, which is characterized in that

Wherein the memory management circuitry reads the data frame, and described from the first instance programmed cell Three check code circuits check the read data frame according to second check code in the read data frame In first data.

17. a kind of memory storage apparatus characterized by comprising

One connecting interface unit, is electrically connected to a host system；

One reproducible nonvolatile memorizer module, wherein the reproducible nonvolatile memorizer module has multiple realities Body erased cell, and each of entity erased cell has multiple entity program units；And

One memorizer control circuit unit, including a host interface, a memory interface, one first check code circuit, one second Check code circuit, a third check code circuit, a memory management circuitry and an error checking and correcting circuit,

Wherein the host interface is electrically connected to the connecting interface unit, and the first check code circuit is electrically connected to institute Host interface is stated, the memory management circuitry is electrically connected to the first check code circuit, the second check code circuit It is electrically connected to the memory management circuitry, the third check code circuit is electrically connected to the second check code circuit, The memory interface is electrically connected to the third check code circuit and the reproducible nonvolatile memorizer module, and And the error checking and correcting circuit are electrically connected to the memory management circuitry,

Wherein the host interface receives one first serial data, the first check code circuit generation pair from the host system One first check code of first serial data is answered,

Wherein the third check code circuit generates one second inspection according to an information of corresponding checked first serial data Code is looked into,

Wherein the first check code circuit is the same as the second check code circuit.

18. memory storage apparatus according to claim 17, which is characterized in that the length of first check code is not small In the length of second check code.

19. memory storage apparatus according to claim 17, which is characterized in that

The host interface receives one second serial data,

Wherein in the above-mentioned generation error checking and the running of correcting code, the third check code circuit is that foundation has verified First data and checked second data generate the mistake using the error checking and correcting circuit Inspection and correcting code

20. memory storage apparatus according to claim 19, which is characterized in that correspond to the described of first serial data The size of first check code is greater than described second with the summation of the size of first check code of corresponding second serial data The size of check code.

21. memory storage apparatus according to claim 17, which is characterized in that

22. memory storage apparatus according to claim 17, which is characterized in that the memorizer control circuit unit is also Including a data compression circuit, the memory compression circuit is electrically connected to the memory management circuitry and to compress First serial data of verification to generate one first compressed data string,

23. memory storage apparatus according to claim 17, which is characterized in that the memorizer control circuit unit is also Including a data compression circuit, the memory compression circuit is electrically connected to the memory management circuitry and to compress First serial data of verification to generate one first compressed data string,

24. memory storage apparatus according to claim 17, which is characterized in that

The memory management circuitry reads the data frame from the first instance programmed cell, and the third is examined Yard circuit is looked into according to second check code in the read data frame to check in the read data frame First data.