CN106372000A

CN106372000A - Update method for mapping table, control circuit unit of memory, and storage device of memory

Info

Publication number: CN106372000A
Application number: CN201510425001.5A
Authority: CN
Inventors: 叶志刚; 谢长翰
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2015-07-20
Filing date: 2015-07-20
Publication date: 2017-02-01
Anticipated expiration: 2035-07-20
Also published as: CN106372000B

Abstract

The invention provides an update method for a mapping table, a control circuit unit of a memory and a storage device of the memory. The method comprises the steps that mapping table storage space is distributed in the buffer memory so as to store a physical address-logic address mapping table; whether residual storage space of the mapping table storage space is smaller than a threshold value is judged, wherein if the residual storage space is smaller than the threshold value, mapping information of the physical address-logic address mapping table stored in the mapping table storage space will be updated to at least one logic address-physical address mapping table, and the mapping information of the physical address-logic address mapping table stored in the mapping table storage space will be eliminated; and update mapping information of a corresponding programmed actuation physical erasing unit is stored in the mapping table storage space. According to the invention, the problem that programmed data cannot be recovered due to programming failures of other physical programming units after mapping table update can be avoided.

Description

Mapping table updating method, memorizer control circuit unit and memory storage apparatus

Technical field

The invention relates to a kind of mapping table updating method, more particularly, to a kind of non-for duplicative The mapping table updating method of the logical address-physical address of volatile, memorizer control circuit Unit and memory storage apparatus.

Background technology

Digital camera, mobile phone and mp3 are in growth over the years very rapidly so that consumer is to storage The demand of media also rapidly increases.Due to type nonvolatile (rewritable non-volatile Memory) there is the characteristics such as data non-volatile, power saving, small volume, mechanical structure, read or write speed be fast, Therefore, type nonvolatile industry becomes a quite popular ring in electronic industry in recent years. For example, have been widely used as calculating using flash memory as the solid state hard disc (solid-state drive) of storage media The hard disk of machine host, to lift the access efficiency of computer.

It is used reproducible nonvolatile memorizer module can build as the memory storage apparatus of storage media Vertical logical address-physical address mapping table, to record the map information between logical block and solid element, makes Host computer system can smoothly access the data of reproducible nonvolatile memorizer module.For example, when main frame system During data to be write of uniting, this data can be programmed to solid element by memory storage apparatus, and by this data The mapping relations of logical block and solid element be updated to logical address-physical address mapping table.Concrete and Speech, the logical address-physical address mapping table of this logical block corresponding can be loaded onto by memory storage apparatus Buffer storage is updating.

And because the logical block of host computer system data to be write every time likely corresponds to different logical addresses - physical address mapping table, for avoiding continually more new logical addresses-physical address mapping table, memory storage Device can distribute a temporarily providing room to store temporary mapping table, and the data being intended to write is programmed to start in fact Body wipes unit, and the logical block belonging to data and start entity is wiped the mapping relations storage of unit In temporarily providing room.When temporarily providing room is expired, then will be stored in the temporary mapping table in temporarily providing room Map information is once updated to logical address-physical address mapping table.

However, the actual data volume being programmable to each solid element may different (for example, data be through overvoltage Contracting) that is to say, that each solid element may be mapped to the logical block of varying number.Therefore, keep in In mapping table, the map information size of each solid element corresponding also can be different.Consequently, it is possible to when temporary sky Between completely when, it is possible to create start entity wipes the situation that unit is not yet fully written.And in the case, Because temporarily providing room is full, the control circuit of memory storage apparatus can be temporary by stored in temporarily providing room The map information depositing mapping table is updated to logical address-physical address mapping table, and by the number subsequently to be write Not yet it is programmed that entity programming unit according to being programmed in start entity erasing unit according to programmed order.

For example, the entity erasing unit of multi-level cell memory (multi level cell, mlc) nand flash memory Including lower entity programming unit (also known as Fast Page) and upper entity programming unit (also known as the page at a slow speed).To After the map information of temporary mapping table is updated to logical address-physical address mapping table, if according to programming When the data being sequentially intended to write is programmed to the upper entity programming unit that start entity is wiped in unit, send out Raw misprogrammed (for example, occurring not expect power-off), can lead to correspond to the programming of entity programming unit on this The data of lower entity programming unit also make a mistake.But due to logical address-physical address mapping table by Update, have no way of learning the old address of this data, and the situation that this data cannot recover occurs.

Content of the invention

The embodiment of the present invention provides a kind of mapping table updating method, memorizer control circuit unit and memorizer Storage device, its can efficiently more new logical addresses-physical address mapping table, and avoid more new logic After address-physical address mapping table, the data of programming is because of the program fail of other entity programming units no The situation that method is recovered.

One embodiment of the invention proposes a kind of mapping table updating method, for memory storage apparatus.Deposit Reservoir storage device has reproducible nonvolatile memorizer module.Type nonvolatile Module has multiple entity erasing units, and each entity erasing unit has multiple entity programming units.Reflect Firing table update method includes: allocation map table memory space in buffer storage, with storage entity address- Logical address mapping table；Judge whether the residual memory space in mapping table memory space is less than one first Threshold value；If judging that residual memory space is less than the first threshold value, then will be stored in mapping table memory space In the map information of physical address-logical address mapping table be updated at least one logical address-physical address Mapping table；Remove the mapping letter of the physical address-logical address mapping table being stored in mapping table memory space Breath；And many write data belonging to multiple programming in logic units are programmed to described entity erasing unit One of start entity wipe unit multiple entity programming units, set up programming said write data Entity programming unit and programming in logic unit between multiple renewal map informations, and by described renewal Map information stores to mapping table memory space.

In one embodiment of this invention, above-mentioned store described renewal map information stores sky to mapping table Between in step include: when described a portion updating map information is stored store to mapping table empty Between and mapping table memory space in residual memory space be not more than the second threshold value when, judge start reality Whether there are at least one first instance programming unit, wherein said at least one first instance in body erasing unit Programming unit is lower entity programming unit, and described at least one first instance programming unit has programmed valid data And the upper entity programming unit of at least one first instance programming unit is not programmed described in corresponding；If judging Described in having in start entity erasing unit during at least one first instance programming unit, then virtual data is compiled The upper entity programming unit of at least one first instance programming unit described in journey is extremely corresponding；Virtual data is being compiled After the upper entity programming unit of at least one first instance programming unit described in journey is extremely corresponding, will be stored in reflecting The map information of the physical address in firing table memory space-logical address mapping table is updated at least one logic Address-physical address mapping table；And remove and be stored in physical address in mapping table memory space-logically The map information of location mapping table and by described update map information remainder store to mapping table storage In space.

In one embodiment of this invention, stored correspondence in above-mentioned mapping table memory space multiple to program Entity wipes multiple renewal map informations of unit.

In one embodiment of this invention, above-mentioned mapping table updating method also includes: calculates corresponding described Programming entity wipe unit one of them programming entity wipe unit renewal map information big Little, one of them programming entity erasing unit wherein said is that said write data is being programmed to start Entity wipes the entity erasing unit finally programming before multiple entity programming units of unit；And set One of them programming entity wipe unit renewal map information size as the first threshold value.

In one embodiment of this invention, above-mentioned mapping table updating method also includes: calculates correspondence each Programming entity wipes the size of the renewal map information of unit；Described in calculating, programming entity wipes unit Renewal map information size meansigma methodss；And set meansigma methodss as the first threshold value.

In one embodiment of this invention, above-mentioned mapping table updating method also includes: calculates correspondence each Programming entity wipes the size of the renewal map information of unit；Programming entity erasing described in identification is corresponding Maximum among the size of renewal map information of unit；And set maximum as the first threshold value.

In one embodiment of this invention, at least a portion data among above-mentioned write data is by from master Produced data after the many compressing original data that machine system is received.

One embodiment of the invention proposes a kind of memorizer control circuit unit, stores dress for control memory The reproducible nonvolatile memorizer module put.Wherein reproducible nonvolatile memorizer module has Multiple entities wipe unit, and each entity erasing unit has multiple entity programming units.Memorizer controls Circuit unit includes: HPI, memory interface and memory management circuitry.HPI is in order to electricity Property connects to host computer system；Memory interface is electrically connected to type nonvolatile mould Block；And memory management circuitry is electrically connected to HPI and memory interface.Memory management circuitry In order to allocation map table memory space in buffer storage, with storage entity address-logical address mapping Table, additionally, memory management circuitry is also in order to judge that the residual memory space in mapping table memory space is No it is less than one first threshold value.If judging that residual memory space is less than the first threshold value, memory management Circuit is also in order to will be stored in the mapping of the physical address in mapping table memory space-logical address mapping table Information updating is at least one logical address-physical address mapping table.Furthermore, memory management circuitry also in order to Remove the map information of the physical address-logical address mapping table being stored in mapping table memory space.Separately Outward, memory management circuitry is also in order to be programmed to many write data belonging to multiple programming in logic units Described entity wipe unit one of start entity wipe multiple entity programming units of unit, set up Multiple more new mappings between the entity programming unit of programming said write data and those programming in logic units Information, and described renewal map information is stored to mapping table memory space.

In one embodiment of this invention, when described a portion updating map information is stored to reflecting When the residual memory space of firing table memory space and mapping table memory space is not more than the second threshold value, storage Device management circuit is also in order to judge whether there is at least one first instance programming list in start entity erasing unit Unit, wherein said at least one first instance programming unit is lower entity programming unit, described at least one first Entity programming unit programmed valid data and to should described at least one first instance programming unit upper reality Body programming unit is not programmed.If additionally, judge start entity erasing unit in have described at least one During first instance programming unit, memory management circuitry is also in order to be programmed to described in correspondence extremely virtual data The upper entity programming unit of a few first instance programming unit.And, virtual data is being programmed to correspondence After the upper entity programming unit of described at least one first instance programming unit, memory management circuitry is also used Updated with the map information that will be stored in the physical address in mapping table memory space-logical address mapping table To at least one logical address-physical address mapping table.Furthermore, memory management circuitry is also in order to remove storage The map information of the physical address in mapping table memory space-logical address mapping table and by described more The remainder of new mappings information stores to mapping table memory space.

In one embodiment of this invention, above-mentioned memory management circuitry is also compiled described in correspondence in order to calculate One of them of Cheng Shiti erasing unit programming entity wipes the size of the renewal map information of unit, its Described in one of them programming entity erasing unit be by said write data be programmed to start entity wipe Entity erasing unit except programming last before multiple entity programming units of unit.And, memorizer pipe Reason circuit also in order to set described one of them programming entity wipe unit renewal map information size As the first threshold value.

In one embodiment of this invention, also in order to calculate, correspondence is each to be compiled above-mentioned memory management circuitry Cheng Shiti wipes the size of the renewal map information of unit.Additionally, memory management circuitry is also in order to calculate Described programming entity wipes the meansigma methodss of the size of renewal map information of unit, and sets this meansigma methods As the first threshold value.

In one embodiment of this invention, also in order to calculate, correspondence is each to be compiled above-mentioned memory management circuitry Cheng Shiti wipes the size of the renewal map information of unit.Additionally, memory management circuitry is also in order to identify Described in correspondence, programming entity wipes the maximum among the size of renewal map information of unit, and sets This maximum is as the first threshold value.

In one embodiment of this invention, at least a portion data among above-mentioned write data is by upper State memory management circuitry by produced number after many received from host computer system compressing original data According to.

One embodiment of the invention proposes a kind of memory storage apparatus, comprising: connecting interface unit, can answer Write formula non-volatile memory module and memorizer control circuit unit.Connecting interface unit is in order to electrically to connect It is connected to host computer system；Reproducible nonvolatile memorizer module includes multiple entity erasing units；Storage Device control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module. Memorizer control circuit unit in order to allocation map table memory space in buffer storage, in order to store reality Body address-logical address mapping table.Additionally, memorizer control circuit unit also stores in order to judge mapping table Whether the residual memory space in space is less than one first threshold value.If judging that residual memory space is less than First threshold value, memorizer control circuit unit is also in order to will be stored in the entity in mapping table memory space The map information of address-logical address mapping table is updated at least one logical address-physical address mapping table.Again Person, memorizer control circuit unit is also in order to remove the physical address that is stored in mapping table memory space-patrol Collect the map information of address mapping table.In addition, memorizer control circuit unit will be also in order to will belong to multiple patrolling Many write data of volume programming unit be programmed to described entity wipe unit one of start entity wipe Except multiple entity programming units of unit, set up entity programming unit and the logic of programming said write data Multiple renewal map informations between programming unit, and described renewal map information is stored to mapping table In memory space.

In one embodiment of this invention, when described a portion updating map information is stored to reflecting When residual memory space in firing table memory space and mapping table memory space is not more than the second threshold value, Memorizer control circuit unit is also in order to judge whether have at least one first in fact in start entity erasing unit Body programming unit, wherein said at least one first instance programming unit be lower entity programming unit, described extremely Lack a first instance programming unit and program valid data and at least one first instance programming unit described in correspondence Upper entity programming unit be not programmed.If additionally, judging to have in start entity erasing unit described During at least one first instance programming unit, memorizer control circuit unit is also in order to be programmed to virtual data The upper entity programming unit of at least one first instance programming unit described in correspondence.And, by virtual data After being programmed to the upper entity programming unit of at least one first instance programming unit described in corresponding to, memorizer control Circuit unit processed is also in order to will be stored in the physical address in mapping table memory space-logical address mapping table Map information be updated at least one logical address-physical address mapping table.Furthermore, memorizer control circuit Unit is also in order to remove reflecting of the physical address-logical address mapping table being stored in mapping table memory space Penetrate information and store the described remainder updating map information to mapping table memory space.

In one embodiment of this invention, above-mentioned memorizer control circuit unit is also corresponding described in order to calculate Programming entity wipe unit one of them programming entity wipe unit renewal map information big Little, one of them programming entity erasing unit wherein said is that said write data is being programmed to start Entity wipes the entity erasing unit finally programming before multiple entity programming units of unit.And, deposit Memory control circuit unit also in order to set described one of them programming entity wipe unit more new mappings The size of information is as the first threshold value.

In one embodiment of this invention, above-mentioned memorizer control circuit unit is also each in order to calculate correspondence Programming entity wipes the size of the renewal map information of unit.Additionally, memorizer control circuit unit is also Wipe the meansigma methodss of the size of the renewal map information of unit in order to programming entity described in calculating, and set This meansigma methods is as the first threshold value.

In one embodiment of this invention, above-mentioned memorizer control circuit unit is also each in order to calculate correspondence Programming entity wipes the size of the renewal map information of unit.Additionally, memorizer control circuit unit is also In order to identify that described in correspondence, programming entity wipes the maximum among the size of the renewal map information of unit Value, and set this maximum as the first threshold value.

In one embodiment of this invention, at least a portion data among above-mentioned write data is by depositing Memory control circuit unit is by produced number after many received from host computer system compressing original data According to.

Based on above-mentioned, mapping table updating method provided in an embodiment of the present invention, memorizer control circuit unit And memory storage apparatus, the renewal efficiency of logical address-physical address mapping table can be lifted, and avoid more After new logical addresses-physical address mapping table, the data of programming is because of the programming mistake of other entity programming units The situation losing and cannot recovering.

It is that the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate Accompanying drawing is described in detail below.

Brief description

Fig. 1 is the schematic diagram of the host computer system shown by the embodiment of the present invention and memory storage apparatus；

Fig. 2 is computer shown by the embodiment of the present invention, input/output device and memory storage apparatus Schematic diagram；

Fig. 3 is the schematic diagram of the host computer system shown by the embodiment of the present invention and memory storage apparatus；

Fig. 4 is the schematic block diagram of the memory storage apparatus shown by the embodiment of the present invention；

Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by the embodiment of the present invention；

Fig. 6 a and Fig. 6 b is that the example of the management entity erasing unit shown by the embodiment of the present invention is illustrated Figure；

Fig. 7 a, Fig. 7 b and Fig. 7 c are, shown by the embodiment of the present invention, start entity is wiped unit Update map information to store to the example schematic of mapping table memory space；

Fig. 8 is of the renewal map information that start entity is wiped unit shown by the embodiment of the present invention Part stores to the example schematic of mapping table memory space；

Fig. 9 is the schematic diagram putting in order of the entity programming unit shown by the embodiment of the present invention；

Figure 10 a and Figure 10 b is that the start entity that is programmed to virtual data shown by the embodiment of the present invention is wiped Example schematic except the upper entity programming unit of unit；

Figure 11 is the flow chart of the mapping table updating method shown by the embodiment of the present invention；

Figure 12 is another exemplary flowchart of the mapping table updating method shown by the embodiment of the present invention.

Description of reference numerals:

10: memory storage apparatus；

11: host computer system；

12: computer；

13: input/output device；

122: microprocessor；

124: random access memory (ram)；

126: system bus；

128: data transmission interface

21: mouse；

22: keyboard；

23: display；

24: printer；

25: portable disk；

26: storage card；

27: solid state hard disc；

31: digital camera；

32:sd card；

33:mmc card；

34: memory stick；

35:cf card；

36: embedded storage device；

402: connecting interface unit；

404: memorizer control circuit unit；

406: reproducible nonvolatile memorizer module；

410 (0)～410 (n): entity wipes unit；

502: memory management circuitry；

504: HPI；

506: memory interface；

508: buffer storage；

510: electric power management circuit；

512: error checking and correcting circuit；

514: data compression/decompression contracting circuit；

602: data field；

604: idle area；

606: system area；

608: replace area；

610 (0)～610 (d): logical address；

701st, 801: mapping table memory space；

Um0, um1, um2, um3: update map information；

Pba (0-0)～pba (0-k): entity programming unit；

W (0)～w (l): character line；

D0～d5: valid data

Dd: virtual data

s1101、s1103、s1105、s1107、s1109、s1111、s1201、s1203、s1205、 S1207: the step of mapping table updating method.

Specific embodiment

In general, memory storage apparatus (also referred to as, storage system) inclusion duplicative is non-volatile Property memory module and controller (also referred to as, control circuit).Being commonly stored device storage device is and host computer system It is used together, so that host computer system can write data into memory storage apparatus or from memory storage dress Put middle reading data.

Fig. 1 is the schematic diagram of the host computer system shown by the embodiment of the present invention and memory storage apparatus, and Fig. 2 is showing of computer shown by the embodiment of the present invention, input/output device and memory storage apparatus It is intended to.

Refer to Fig. 1, host computer system 11 generally comprise computer 12 and input/output (input/output, Abbreviation i/o) device 13.Computer 12 includes microprocessor 122, random access memory (random access Memory, abbreviation ram) 124, system bus 126 and data transmission interface 128.Input/output device 13 include mouse 21 as Fig. 2, keyboard 22, display 23 and printer 24.It will be appreciated that The unrestricted input/output device of device shown in Fig. 2 13, input/output device 13 may also include other dresses Put.

In the present embodiment, memory storage apparatus 10 are by data transmission interface 128 and host computer system 11 other assemblies are electrically connected with.By microprocessor 122, random access memory 124 and input/defeated The running going out device 13 can write data into memory storage apparatus 10 or from memory storage apparatus 10 Middle reading data.For example, memory storage apparatus 10 can be portable disks 25 as shown in Figure 2, deposit Card storage 26 or the duplicative non-volatile memories of solid state hard disc (solid state drive, abbreviation ssd) 27 grades Device storage device.

Fig. 3 is the schematic diagram of the host computer system shown by the embodiment of the present invention and memory storage apparatus.

In general, host computer system 11 is substantially to coordinate with memory storage apparatus 10 to store number According to any system.Although in the present embodiment, host computer system 11 is to be explained with computer system, However, host computer system 11 can be digital camera, video camera, communicator, sound in another embodiment The system such as frequency player or video player.For example, it is (the shooting of digital camera in Fig. 3 in host computer system Machine) 31 when, sd card 32 that type nonvolatile storage device is then used by it, mmc Card 33, memory stick (memory stick) 34, cf card 35 or embedded storage device 36 (as shown in Figure 3). Embedded storage device 36 includes embedded multi-media card (embedded mmc, abbreviation emmc).It is worth One is mentioned that, embedded multi-media card is directly to be electrically connected on the substrate of host computer system.

Fig. 4 is the schematic block diagram of the memory storage apparatus shown by the embodiment of the present invention.

Refer to Fig. 4, memory storage apparatus 10 include connecting interface unit 402, memorizer controls electricity Road unit 404 and reproducible nonvolatile memorizer module 406.

In the present embodiment, connecting interface unit 402 is compatible with Serial Advanced Technology adnexa (serial Advanced technology attachment, abbreviation sata) standard.However, it is necessary to be appreciated that, this Invention not limited to this, connecting interface unit 402 can also be met and shape advanced technology attachment (parallel Advanced technology attachment, abbreviation pata) standard, Institute of Electrical and Electric Engineers (institute of electrical and electronic engineers, abbreviation ieee) 1394 standards, high-speed peripheral Part connecting interface (peripheral component interconnect express, pci express) standard, USB (universal serial bus) (universal serial bus, abbreviation usb) standard, a ultrahigh speed generation (ultra high Speed-i, abbreviation uhs-i) interface standard, ultrahigh speed secondary (ultra high speed-ii, uhs-ii) interface Standard, secure digital (secure digital, sd) interface standard, memory stick (memory stick, abbreviation ms) Interface standard, multimedia storage card (multi media card, abbreviation mmc) interface standard, compact flash (compact flash, abbreviation cf) interface standard, Integrated Device Electronics (integrated device electronics, Ide) standard or other standard being suitable for.In the present embodiment, connecting interface unit can be with memorizer control Circuit unit is encapsulated in a chip, or is laid in outside a chip comprising memorizer control circuit unit.

Memorizer control circuit unit 404 is in order to execute in the form of hardware or multiple patrolling of realizing of software form Volume door or control instruction, and according to the instruction of host computer system 11 in type nonvolatile mould Carry out the write of data in block 406, read and the runnings such as erasing.

Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404, and the data being write in order to host system 11.Type nonvolatile mould Block 406 has entity erasing unit 410 (0)～410 (n).For example, entity erasing unit 410 (0)～410 (n) Same memory crystal grain (die) can be belonged to or belong to different memory crystal grain.Each entity erasing is single Unit is respectively provided with a plurality of entity programming units, wherein belongs to the entity programming that same entity wipes unit Unit can be written independently and simultaneously be wiped.However, it is necessary to be appreciated that, the invention is not restricted to This, each entity erasing unit be can by 64 entity programming units, 256 entity programming units or its Its arbitrarily individual entity programming unit is formed.

In more detail, entity wipes the least unit that unit is erasing.That is, each entity erasing is single First memory element being wiped free of in the lump containing minimal amount.Entity programming unit is the minimum unit of programming. That is, entity programming unit is the minimum unit of write data.Each entity programming unit generally includes data Position area and redundancy function area.Data bit area comprises multiple entity access addresses in order to store the data of user, And redundancy function area is in order to the data (for example, control information and error correcting code) of storage system.In the present embodiment In, 8 entity access addresses can be comprised in the data bit area of each entity programming unit, and a reality The size of body access address is 512 bytes (byte).However, in other embodiments, in data bit area Number more or less of entity access address can be comprised, the present invention is not intended to limit the big of entity access address Little and number.For example, in one embodiment, entity erasing unit is physical blocks, and entity is compiled Cheng Danyuan is physical page or entity sector, but the present invention is not limited.

In the present embodiment, reproducible nonvolatile memorizer module 406 is multi-level cell memory (multi Level cell, abbreviation mlc) nand type flash memory module (that is, can store 2 in a memory element The flash memory module of individual data bit).However, the invention is not restricted to this, type nonvolatile Module 406 may also be single-order memory element (single level cell, abbreviation slc) nand type flash memory Module (that is, can store the flash memory module of 1 data bit in a memory element), Complex Order storage are single First (trinary level cell, abbreviation tlc) nand type flash memory module (that is, memory element In can store the flash memory module of 3 data bit), other flash memory module or other there is depositing of identical characteristics Memory modules.

Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by the embodiment of the present invention.

Refer to Fig. 5, memorizer control circuit unit 404 includes memory management circuitry 502, main frame connects Mouth 504 and memory interface 506.

Memory management circuitry 502 is in order to the overall operation of control memory control circuit unit 404.Tool For body, memory management circuitry 502 has multiple control instructions, and in memory storage apparatus 10 During running, this little control instruction can be performed write, reading and the runnings such as erasing to carry out data.

In the present embodiment, the control instruction of memory management circuitry 502 is to carry out implementation in a software form. For example, memory management circuitry 502 has microprocessor unit (not shown) and read only memory (not shown), And this little control instruction is to be programmed so far in read only memory.When memory storage apparatus 10 operate When, this little control instruction can be executed write, reading and the erasing to carry out data by microprocessor unit Deng running.

In an alternative embodiment of the invention, the control instruction of memory management circuitry 502 can also program generation Code form is stored in specific region (for example, the memorizer mould of reproducible nonvolatile memorizer module 406 It is exclusively used in the system area of storage system data in block) in.Additionally, memory management circuitry 502 has micro- place Reason device unit (not shown), read only memory (not shown) and random access memory (not shown).Particularly, This read only memory has driving code, and when memorizer control circuit unit 404 is enabled, micro- place Reason device unit can first carry out this and drive code section will be stored in reproducible nonvolatile memorizer module 406 In control instruction be loaded onto in the random access memory of memory management circuitry 502.Afterwards, micro- place Reason device unit can operate this little control instruction to carry out the write of data, to read and the runnings such as erasing.

HPI 504 is electrically connected to memory management circuitry 502 and the company of being electrically connected to Connection interface unit 402, to receive the instruction being transmitted with identification host computer system 11 and data.That is, The instruction that host computer system 11 is transmitted and data can be sent to memory management electricity by HPI 504 Road 502.In the present embodiment, HPI 504 is compatible with sata standard.However, it is necessary to Solution is to the invention is not restricted to this, and HPI 504 can also be compatible with pata standard, ieee 1394 Standard, pci express standard, usb standard, uhs-i interface standard, uhs-ii interface standard, sd Standard, ms standard, mmc standard, cf standard, ide standard or other data transfer mark being suitable for Accurate.

Memory interface 506 is electrically connected to memory management circuitry 502 and can make carbon copies in order to access Formula non-volatile memory module 406.That is, being intended to write to type nonvolatile The data of module 406 can be converted to reproducible nonvolatile memorizer module by memory interface 506 The receptible form of 406 institutes.

In one embodiment, memorizer control circuit unit 404 also includes buffer storage 508, power supply Management circuit 510, error checking and correcting circuit 512 and data compression/decompression contracting circuit 514.

Buffer storage 508 is electrically connected to memory management circuitry 502 and being configured to temporarily store and comes from The data of host computer system 11 and instruction or the number coming from reproducible nonvolatile memorizer module 406 According to.

Electric power management circuit 510 is electrically connected to memory management circuitry 502 and in order to control storage The power supply of device storage device 10.

Error checking and correcting circuit 512 are electrically connected to memory management circuitry 502 and in order to hold Row error checking and correction program are to guarantee the correctness of data.Specifically, work as memory management circuitry 502 when receiving write instruction from host computer system 11, and error checking can be corresponding with correcting circuit 512 The data of this write instruction produces corresponding error checking and correcting code (error checking and Correcting code, abbreviation ecc code), and memory management circuitry 502 can be by this write corresponding The data of instruction is write to reproducible nonvolatile memorizer module with corresponding error checking and correcting code In 406.Afterwards, when memory management circuitry 502 is from reproducible nonvolatile memorizer module 406 Middle reading data when can read the corresponding error checking of this data and correcting code simultaneously, and error checking with Correcting circuit 512 can execute error checking and school with correcting code to the data being read according to this error checking Positive program.

Data compression/decompression contracting circuit 514 is electrically connected to memory management circuitry 502.Here, number It is intended to write to reproducible nonvolatile memorizer module 406 in order to compress according to compression/decompression circuit 514 Data and in order to decompress the number being read from reproducible nonvolatile memorizer module 406 According to.For example, data compression/decompression contracting circuit 514 comprises compressor (compressor) and decompressor (decompressor).Compressor may be used to find out the burden of data present in initial data (original data) (data redundancy), remove found out burden, remaining necessary data is encoded and exports coding Result (that is, compressed data (compressed data).And decompressor in order to will read in compressed data according to Set step decodes and sends decoding result (that is, decompression data (decompressed data)).At this In exemplary embodiment, data compression/decompression contracting circuit 514 is to carry out compressed data using Lossless Compression algorithm, So that the data after compression can be reduced.

Fig. 6 a and Fig. 6 b is that the example of the management entity erasing unit shown by the embodiment of the present invention is illustrated Figure.

It will be appreciated that being described herein the entity erasing of reproducible nonvolatile memorizer module 106 During the running of unit, reality is operated with the word such as " extraction ", " packet ", " division ", " association " Body wipes the concept that unit is in logic.That is, the reality of reproducible nonvolatile memorizer module The physical location that body wipes unit is not changed, but in logic to type nonvolatile mould The entity erasing unit of block is operated.

Refer to Fig. 6 a, memorizer control circuit unit 404 (or memory management circuitry 502) can be by entity Erasing unit 410 (0)～410 (n) is logically grouped into data field 602, idle area 604, system area 606 With replacement area 608.

The entity erasing unit logically belonging to data field 602 with idle area 604 is to store to come from The data of host computer system 11.Specifically, the entity erasing unit of data field 602 is regarded as storing The entity erasing unit of data, and the entity erasing unit in idle area 604 is in order to replacement data area 602 Entity erasing unit.That is, work as receiving write instruction and the number to be write from host computer system 11 According to when, memory management circuitry 502 can extract entity erasing unit from idle area 604, and by number According in write to the entity erasing unit being extracted, unit is wiped with the entity in replacement data area 602.

The entity erasing unit logically belonging to system area 606 is in order to record system data.For example, it is The manufacturer that system data is included with regard to reproducible nonvolatile memorizer module is non-with model, duplicative The entity of volatile wipes unit number, each entity wipes the entity programming unit number of unit Deng.

The entity erasing unit logically belonging to replace in area 608 is to replace journey for bad entity erasing unit Sequence, wipes unit with replacing damaged entity.Specifically, still have normally if replacing in area 608 Entity when wiping the entity erasing unit of unit and data field 602 and damaging, memory management circuitry 502 The entity erasing unit that normal entity erasing unit to change damage can be extracted from replacing area 608.

Particularly, data field 602, idle area 604, system area 606 and the entity erasing replacing area 608 The quantity of unit can be different according to different memorizer specifications.Further, it is necessary to be appreciated that, In the running of memory storage apparatus 10, entity erasing unit close be coupled to data field 602, idle area 604, System area 606 can dynamically be changed with the packet relation replacing area 608.For example, when in idle area 604 Entity wipe that unit damages and when the entity erasing unit in substituted area 608 replaces, then originally replace area 608 entity erasing unit can be associated to idle area 604.

Refer to Fig. 6 b, as described above, the entity erasing unit in data field 602 and idle area 604 be with The mode of rotating carrys out the data that host system 11 is write.In the present embodiment, memorizer control circuit Unit 404 (or memory management circuitry 502) can configure logical address 610 (0)～610 (d) to host computer system 11, unit 414 (0)～410 (f-1) is wiped with the entity mapping to part in data field 602, is beneficial to Carry out data access in the entity erasing unit carrying out data storage in the above-mentioned mode of rotating.Particularly, main frame System 11 can access the data in data field 602 by logical address 610 (0)～610 (d).Additionally, Memorizer control circuit unit 404 (or memory management circuitry 502) can set up logical address-physical address Mapping table (logical address-physical address mapping table), to record logical block and entity Mapping relations between unit.This logical address-physical address mapping table may, for example, be record logical address With entity erasing unit, logical address and entity programming unit, programming in logic unit and entity erasing unit And/or the various logic such as mapping relations between programming in logic unit and entity programming unit and entity is right Should be related to, the present invention is not any limitation as.

In the present embodiment, the reproducible nonvolatile memorizer module 406 of memory storage apparatus 10 Can be based on entity programming unit ((page based) also referred to as based on the page) being managed. For example, when executing write instruction, no matter current data is intended to write to that programming in logic unit, deposit Memory control circuit unit 404 (or memory management circuitry 502) all can be continued with an entity programming unit The mode of one entity programming unit is writing data (also referred to as random writing mechanism).Specifically, store Device control circuit unit 404 (or memory management circuitry 502) can extract from idle area 604 one empty Entity erasing unit to write data as start entity erasing unit.And, when the erasing of this start entity When unit writes full, memorizer control circuit unit 404 (or memory management circuitry 502) can be again from idle Extract another empty entity erasing unit in area 604 and wipe unit as start entity, to continue to write to Correspondence comes from the data of the write instruction of host computer system 11.

In the present embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can be slow Rush allocation map table memory space in memorizer 508, in order to storage entity address-logical address mapping table (physical address-logical address mapping table), to record the start entity erasing of programming The entity programming unit of unit and the mapping relations of the programming in logic unit belonging to data.In the present embodiment, The data being programmed to entity programming unit can be through overcompression or without overcompression.Therefore, a reality Body programming unit can map one or more programming in logic units.If an entity programming unit is to be mapped to One programming in logic unit (for example, be programmed to start entity and wipe the data of unit without overcompression), as When dynamic entity erasing unit writes full, start entity wipes multiple entity programming units of unit and multiple logics The size of the renewal map information that multiple mapping relations of programming unit are formed is just 1 unit.Memorizer Control circuit unit 404 (or memory management circuitry 502) can distribute 4 units in buffer storage 508 Memory space carry out storage entity address-logical address mapping table as mapping table memory space.However, Visual actual demand determining that distributing more or less of memory space is used as mapping table memory space, this Invention is not any limitation as.

Fig. 7 a, Fig. 7 b and Fig. 7 c are, shown by the embodiment of the present invention, start entity is wiped unit Update map information to store to the example schematic of mapping table memory space.

Refer to Fig. 7 a, for convenience of description, the present embodiment is not yet there to be any entity erasing unit to be closed Being coupled to data field is to start to illustrate.Memorizer control circuit unit 404 (or memory management circuitry 502) the mapping table memory space 701 distributing 4 unit memory spaces in buffer storage 508 is to store Physical address-logical address mapping table.When memorizer control circuit unit 404 (or memory management circuitry 502) when host computer system 11 receives the write instruction writing data into logical address, memorizer controls electricity It is single that road unit 404 (or memory management circuitry 502) can extract an empty entity erasing from idle area 604 Unit is wiped as start entity by unit's (that is, entity erasing unit 410 (0)).Memorizer control circuit unit 404 (or memory management circuitry 502) can wipe the programming of the entity programming unit of unit according to start entity Data is programmed in the entity programming unit that entity wipes unit 410 (0) order.Memorizer control circuit Unit 404 (or memory management circuitry 502) the entity according to programming in entity erasing unit 410 (0) Programming unit updates map information with the mapping relations foundation of the programming in logic unit belonging to data, and will more New mappings information Store is to mapping table memory space 701.When start entity wipes unit (i.e. entity erasing Unit 410 (0)) when writing full, memorizer control circuit unit 404 (or memory management circuitry 502) can be from the spare time Put area 604 and extract another empty entity erasing unit 410 (1) as new start entity erasing unit, To store the data of follow-up write instruction.

In the present embodiment, when start entity erasing unit write Man Erxu choose from idle area 604 another When individual empty entity erasing unit wipes unit as new start entity, memorizer control circuit unit 404 (or memory management circuitry 502) determine whether need to more new logical addresses-physical address mapping table.Tool For body, memorizer control circuit unit 404 (or memory management circuitry 502) may estimate that mapping table stores Whether the residual memory space in space 701 also can reflect in the renewal of wiping unit of the corresponding entity of full storage Penetrate information, and then decide whether to will be stored in physical address in mapping table memory space 701-logically The map information of location mapping table updates logical address-physical address mapping table.In the present embodiment, store Device control circuit unit 404 (or memory management circuitry 502) can judge the surplus of mapping table memory space 701 Whether remaining memory space is less than specific first threshold value.If residual memory space is less than the first threshold value, Memorizer control circuit unit 404 (or memory management circuitry 502) can be according to physical address-logical address The map information being stored in mapping table 701, corresponding logical address-physical address mapping table is loaded onto Buffer storage 508, and map information is updated to logical address-physical address mapping table.

In the present embodiment, the first threshold value may be set to be stored in mapping table memory space 701 and corresponds to The entity of programming wipes the size of the renewal map information of one of entity erasing unit of unit.Example As, this one of entity wipe unit can be before choosing new start entity erasing unit last The entity erasing unit of individual programming.

In the present embodiment, wipe unit 410 (0) when entity to have write completely, and choose entity erasing unit 410 (1) as new start entity erasing unit when, memorizer control circuit unit 404 (or memorizer pipe Reason circuit 502) the entity erasing unit 410 (0) corresponding to programming in mapping table memory space 701 can be calculated The size of renewal map information um0 be 1 unit, and the remaining storage of mapping table memory space 701 is empty Between be 3 units.Now, choosing the entity that before new start entity wipes unit, last programs Erasing unit wipes unit 410 (0) for entity.Therefore, memorizer control circuit unit 404 (or memorizer Management circuit 502) set size (i.e. 1 list that entity wipes the renewal map information um0 of unit 410 (0) Position) as the first threshold value.Further, memorizer control circuit unit 404 (or memory management circuitry 502) can judge that the residual memory space (i.e. 3 unit) of mapping table memory space 701 is not less than the first threshold value (i.e. 1 unit), and need not more new logical addresses-physical address mapping table.That is, can be by new work The renewal map information that dynamic entity wipes unit stores to mapping table memory space 701.

Refer to Fig. 7 b, memorizer control circuit unit 404 (or memory management circuitry 502) chooses entity Erasing unit 410 (1) wipes unit as start entity, and data is programmed to entity erasing unit 410 (1) In.Memorizer control circuit unit 404 (or memory management circuitry 502) wipes unit 410 (1) according to entity In the mapping relations of the entity programming unit of programming and the programming in logic unit belonging to data set up renewal and reflect Penetrate information, and store updating map information to mapping table memory space.When entity wipes unit 410 (1) When writing full, memorizer control circuit unit 404 (or memory management circuitry 502) computational entity address-logic In address mapping table 701, the entity of corresponding programming wipes the renewal map information um1's of unit 410 (1) Size is 1.5 units.

Now, mapping table memory space 701 be stored with correspondent entity wipe unit 410 (0) renewal reflect Penetrate information um0 and correspondent entity wipes the renewal map information um1 of unit 410 (1), wherein update and reflect The size penetrating information um0 is 1 unit, and the size updating map information um1 is 1.5 units.Storage Device control circuit unit 404 (or memory management circuitry 502) simultaneously calculates the surplus of mapping table memory space 701 Remaining memory space is 1.5 units.And last programming before choosing new start entity erasing unit Entity erasing unit be entity erasing unit 410 (1).Therefore, memorizer control circuit unit 404 (or Memory management circuitry 502) set the size that entity wipes the renewal map information um1 of unit 410 (1) (i.e. 1.5 unit) is as the first threshold value.Further, memorizer control circuit unit 404 (or memorizer Management circuit 502) judge that residual memory space (i.e. 1.5 unit) is not less than the first threshold value (i.e. 1.5 unit), Thus not more new logical addresses-physical address mapping table.That is, new start entity can be wiped single The renewal map information of unit stores to mapping table memory space 701.

Refer to Fig. 7 c, memorizer control circuit unit 404 (or memory management circuitry 502) chooses entity Erasing unit 410 (2) wipes unit as start entity, and data is programmed to entity erasing unit 410 (2) In.Memorizer control circuit unit 404 (or memory management circuitry 502) wipes unit 410 (2) according to entity In the mapping relations of the entity programming unit of programming and the programming in logic unit belonging to data set up renewal and reflect Penetrate information, and store updating map information to mapping table memory space 701.When entity wipes unit 410 (2) when writing full, and memorizer control circuit unit 404 (or memory management circuitry 502) calculates mapping table In memory space 701, the entity of corresponding programming wipes the big of the renewal map information um2 of unit 410 (2) Little is 1 unit.

Now, mapping table memory space 701 be stored with correspondent entity wipe unit 410 (0) renewal reflect Penetrate information um0, correspondent entity wipes the renewal map information um1 of unit 410 (1) and correspondent entity is wiped Except the renewal map information um2 of unit 410 (2), the size wherein updating map information um0 is 1 list Position, the size updating map information um1 is 1.5 units, and the size updating map information um2 is 1 Unit.Memorizer control circuit unit 404 (or memory management circuitry 502) simultaneously calculates mapping table storage sky Between 701 residual memory space be 0.5 unit.Last before choosing new start entity erasing unit The entity erasing unit of one programming wipes unit 410 (2) for entity.Therefore, memorizer control circuit list First 404 (or memory management circuitry 502) sets the renewal map information um1 that entity wipes unit 410 (2) Size (i.e. 1 unit) as the first threshold value.Further, memorizer control circuit unit 404 (or Memory management circuitry 502) judge that residual memory space (i.e. 0.5 unit) is less than the first threshold value (i.e. 1 list Position), need more new logical addresses-physical address mapping table.That is, mapping table memory space 701 may The renewal map information that a new start entity wipes unit cannot be corresponded to by full storage, and need to will store The map information of the physical address in mapping table memory space 701-logical address mapping table stores to logic Address-physical address mapping table, and the physical address-logical address removed in mapping table memory space 701 reflects The map information of firing table.

In another embodiment of the invention, the first threshold value may also be set to institute in mapping table memory space The each programming entity of the correspondence of storage wipes the maximum among the size of renewal map information of unit.

For example, refer to Fig. 7 a, now, mapping table memory space 701 only stores correspondent entity erasing The renewal map information um0 of unit 410 (0), the size wherein updating map information um0 is 1 unit, And the residual memory space of mapping table memory space 701 is 3 units.Memorizer control circuit unit 404 (or Memory management circuitry 502) identify that corresponding each programming entity wipes the size of the renewal map information of unit Among, the size that entity wipes the renewal map information um0 of unit 410 (0) is maximum.Therefore, deposit Memory control circuit unit 404 (or memory management circuitry 502) sets entity erasing unit 410 (0) more The size (i.e. 1 unit) of new mappings information um0 is as the first threshold value.Further, memorizer controls Circuit unit 404 (or memory management circuitry 502) judges that the remaining storage of mapping table memory space 701 is empty Between (i.e. 3 unit) be not less than the first threshold value (i.e. 1 unit), thus more new logical addresses-physical address does not reflect Firing table.

For example, refer to Fig. 7 b, now, mapping table memory space 701 has stored correspondent entity erasing The renewal map information um0 of unit 410 (0) wipes the renewal map information of unit 410 (1) with correspondent entity Um1, the size wherein updating map information um0 is 1 unit, updates the size of map information um1 For 1.5 units, and the residual memory space of mapping table memory space 701 is 1.5 units.Memorizer controls The corresponding each programming entity of circuit unit 404 (or memory management circuitry 502) identification wipes the renewal of unit Among the size of map information, the size that entity wipes the renewal map information um1 of unit 410 (1) is Big value.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) sets entity erasing The size (i.e. 1.5 unit) of the renewal map information um1 of unit 410 (1) is as the first threshold value.Enter one Step ground, memorizer control circuit unit 404 (or memory management circuitry 502) judges mapping table memory space 701 residual memory space (i.e. 1.5 unit) is not less than the first threshold value (i.e. 1.5 unit), does not thus update Logical address-physical address mapping table.

For example, refer to Fig. 7 c, now, mapping table memory space 701 has stored correspondent entity erasing The renewal map information um0 of unit 410 (0), correspondent entity wipe the renewal map information of unit 410 (1) Um1 wipes the renewal map information um2 of unit 410 (2) with correspondent entity, wherein updates map information The size of um0 is 1 unit, and the size updating map information um1 is 1.5 units, and more new mappings are believed The size of breath um2 is 1 unit, and the residual memory space of mapping table memory space 701 is 0.5 unit. The corresponding each erasing of programming entity of memorizer control circuit unit 404 (or memory management circuitry 502) identification Among the size of renewal map information of unit, entity wipes the renewal map information um1 of unit 410 (1) Size be maximum.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) sets The size (i.e. 1.5 unit) of renewal map information um1 determining entity erasing unit 410 (1) is as first Threshold value.Further, memorizer control circuit unit 404 (or memory management circuitry 502) judges mapping The residual memory space (i.e. 0.5 unit) of table memory space 701 is less than the first threshold value (i.e. 1.5 unit), And the map information that will be stored in the physical address-logical address mapping table in mapping table memory space 701 is deposited Store up to logical address-physical address mapping table, and remove physical address in mapping table memory space 701- The map information of logical address mapping table.

In the above-described embodiment, the first threshold value is set to be stored in mapping table memory space 701 The entity of corresponding programming wipes the big of the renewal map information of one of entity erasing unit of unit Little.However, in another embodiment of the invention, it is empty that the first threshold value also may be set to mapping table storage Between in each programming entity of the correspondence that stored wipe unit the size of renewal map information meansigma methodss.

For example, refer to Fig. 7 a, now, mapping table memory space 701 only stores correspondent entity erasing The renewal map information um0 of unit 410 (0), the size wherein updating map information um0 is 1 unit, And the residual memory space of mapping table memory space 701 is 3 units.Memorizer control circuit unit 404 (or Memory management circuitry 502) calculate the size that corresponding each programming entity wipes the renewal map information of unit Meansigma methodss be 1 unit, and the first threshold value is set as 1 unit.Further, memorizer controls Circuit unit 404 (or memory management circuitry 502) judges that the remaining storage of mapping table memory space 701 is empty Between (i.e. 3 unit) be not less than the first threshold value (i.e. 1 unit), not more new logical addresses-physical address mapping table.

For example, refer to Fig. 7 b, now, mapping table memory space 701 has stored correspondent entity erasing The renewal map information um0 of unit 410 (0) wipes the renewal map information of unit 410 (1) with correspondent entity Um1, the size wherein updating map information um0 is 1 unit, updates the size of map information um1 For 1.5 units, and the residual memory space of mapping table memory space 701 is 1.5 units.Memorizer controls Circuit unit 404 (or memory management circuitry 502) calculates the renewal that corresponding each programming entity wipes unit The meansigma methodss of the size of map information are 1.25 units, and the first threshold value is set as 1.25 units.Enter One step ground, memorizer control circuit unit 404 (or memory management circuitry 502) judges that mapping table storage is empty Between 701 residual memory space (i.e. 1.5 unit) be not less than the first threshold value (i.e. 1.25 unit), do not update Logical address-physical address mapping table.

For example, refer to Fig. 7 c, now, mapping table memory space 701 be stored with correspondent entity erasing The renewal map information um0 of unit 410 (0), correspondent entity wipe the renewal map information of unit 410 (1) Um1 wipes the renewal map information um2 of unit 410 (2) with correspondent entity, wherein updates map information The size of um0 is 1 unit, and the size updating map information um1 is 1.5 units, and more new mappings are believed The size of breath um2 is 1 unit, and the residual memory space of mapping table memory space 701 is 0.5 unit. Memorizer control circuit unit 404 (or memory management circuitry 502) calculates corresponding each erasing of programming entity The meansigma methodss of the size of renewal map information of unit are 1.17 units, and the first threshold value is set as 1.17 unit.Further, memorizer control circuit unit 404 (or memory management circuitry 502) judges Physical address-logical address mapping table 701 residual memory space (i.e. 0.5 unit) is less than the first threshold value (i.e. 1.17 units), and will be stored in the physical address-logical address mapping table in mapping table memory space 701 Map information stores to logical address-physical address mapping table, and removes in mapping table memory space 701 The map information of physical address-logical address mapping table.

Because the present invention is the correspondence each programming entity erasing list to be stored in mapping table memory space The size of the renewal map information of unit, whether the residual memory space to estimate mapping table memory space can be complete The renewal map information that a new start entity wipes unit is stored up in whole deposit.Therefore, when new start entity Wipe the size of renewal map information of unit not as expected, and the residue being more than mapping table memory space is deposited During storage space, start entity erasing unit can be formed and also do not write completely, it is right that mapping table memory space only stores A part for the renewal map information of start entity erasing unit that should be new has just write full situation.

Fig. 8 is of the renewal map information that start entity is wiped unit shown by the embodiment of the present invention Part stores to the example schematic of mapping table memory space.

Refer to Fig. 8, entity is wiped unit 410 (0) and wiped, with entity, the entity that unit 410 (1) is programming Erasing unit.When entity erasing unit 410 (0) writes full with entity erasing unit 410 (1), mapping table The renewal map information um0 that correspondent entity wipes unit 410 (0) is stored in memory space 801, and right Answer entity to wipe the renewal map information um1 of unit 410 (1), wherein update the big of map information um0 Little is 1 unit, and the size updating map information um1 is 1.5 units, and residual memory space is 1.5 Unit.Memorizer control circuit unit 404 (or memory management circuitry 502) chooses entity erasing unit 410 (2) wipe unit as start entity.Memorizer control circuit unit 404 (or memory management circuitry 502) set entity erasing unit 410 (1) and (choose last volume before new start entity erasing unit The entity of journey wipes unit) renewal map information size (i.e. 1.5 unit) as the first threshold value.Enter One step ground, memorizer control circuit unit 404 (or memory management circuitry 502) judges that mapping table storage is empty Between 801 residual memory space (i.e. 1.5 unit), not less than the first threshold value (i.e. 1.5 unit), not more New logical addresses-physical address mapping table.Therefore, memorizer control circuit unit 404 (or memory management Circuit 502) data is programmed to entity erasing unit 410 (2), and wiped in unit 410 (2) according to entity The entity programming unit of programming and the mapping relations of the programming in logic unit belonging to data set up more new mappings Information, and store updating map information to mapping table memory space 801.

In the present embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can enter one Step judges whether the residual memory space of mapping table memory space 801 is not more than the second threshold value, to determine Whether to judge that start entity removes to smear unit (i.e. entity remove smear unit 410 (2)) and sequentially can be programmed that entity Whether programming unit is upper entity programming unit.Second threshold value is smaller than the first threshold value, or is equal to zero (i.e. mapping table memory space 801 has been write completely), or set according to actual demand, the present invention is not any limitation as.With Lower will be illustrated with the situation that the second threshold value is zero.

In the present embodiment, in fact, when entity is wiped unit 410 (2) and write full, being wiped according to entity The mapping relations of the entity programming unit of programming and programming in logic unit belonging to data in unit 410 (2) The size of the renewal map information set up is 2 units, but the remaining storage of mapping table memory space 801 Space is only capable of storing the renewal map information of 1.5 unit-sized again.Therefore, mapping table memory space 801 Only store correspondent entity to wipe the renewal map information um3 of part of unit 410 (2) (that is, part is more The size of new mappings information um3 is 1.5 units) just write completely, but entity erasing unit 410 (2) is not yet write Full.

When mapping table memory space 801 writes full that is to say, that mapping table memory space 801 no Residual memory space can store renewal map information, need to will be stored in the reality in mapping table memory space 801 The map information of body address-logical address mapping table is updated to logical address-physical address mapping table, and will reflect The map information of the physical address in firing table memory space 801-logical address mapping table is removed.But due to making Dynamic entity erasing unit (i.e. entity erasing unit 410 (2)) is not yet full, memorizer control circuit unit 404 (or memory management circuitry 502), before more new logical addresses-physical address mapping table, can first judge Start entity erasing unit (i.e. entity erasing unit 410 (2)) sequentially can be programmed that entity programming unit is No for upper entity programming unit.Specifically, memorizer control circuit unit 404 (or memory management electricity Road 502) can judge in start entity erasing unit (i.e. entity erasing unit 410 (2)) with the presence or absence of programming The lower entity programming unit of valid data, and this upper entity programming unit corresponding to lower entity programming unit Not yet it is programmed.If judging to exist in start entity erasing unit (i.e. entity erasing unit 410 (2)) above-mentioned Lower entity programming unit, memorizer control circuit unit 404 (or memory management circuitry 502) can be empty by one Intend data (dummy data) to be programmed in the upper entity programming unit corresponding to above-mentioned lower entity programming unit.

Fig. 9 is the schematic diagram putting in order of the entity programming unit shown by the embodiment of the present invention.Here, Wiped by entity and illustrate as a example unit 410 (2), the structure that other entities wipe unit can also be such Push away.

Refer to Fig. 9, entity erasing unit 410 (2) includes entity programming unit pba (0-0)～pba (0-k). For example, in the present embodiment, k is integer.For example, k is 255.Entity programming unit pba (0-0) It is to be made up of the memory element on character line w (0) with entity programming unit pba (0-2)；Entity programming is single First pba (0-1) and entity programming unit pba (0-4) are to be made up of the memory element on character line w (1)； Entity programming unit pba (0-3) and entity programming unit pba (0-6) are by the storage on character line w (2) Unit is constituted；Entity programming unit pba (0-5) and entity programming unit pba (0-8) are by character line Memory element on w (3) is constituted；And by that analogy, entity programming unit pba (0- (k-4)) and reality Body programming unit pba (0- (k-1)) is to be made up of the memory element on character line w (l-1) and entity programming Unit pba (0- (k-2)) and entity programming unit pba (0-k) are by the memory element on character line w (l) Constituted.Here, entity programming unit pba (0-0), pba (0-1), pba (0-3), pba (0-5) ..., Pba (0- (k-4)), pba (0- (k-2)) they are lower entity programming unit, and entity programming unit pba (0-2), Pab (0-4), pba (0-6), pba (0-8) ..., pba (0- (k-1)), pba (0-k) be that upper entity is compiled Cheng Danyuan.

Figure 10 a and Figure 10 b is that the start entity that is programmed to virtual data shown by the embodiment of the present invention is wiped Example schematic except the upper entity programming unit of unit.

Refer to Figure 10 a, when mapping table memory space 801 writes full, start entity erasing unit is (i.e. Entity wipe unit 410 (2)) programmed valid data entity programming unit be lower entity programming unit Pba (0-0), pba (0-1), pba (0-3) and upper entity programming unit pba (0-2), pba (0-4).Its In, memorizer control circuit unit 404 (or memory management circuitry 502) judges entity erasing unit 410 (2) Upper entity programming unit pba (0-6) corresponding to lower entity programming unit pba (0-3) be not yet programmed. Base this, memorizer control circuit unit 404 (or memory management circuitry 502) can first program virtual data Wipe after upper entity programming unit pba (0-6) of unit 410 (2) to entity, then will be stored in mapping table and deposit The map information of the physical address-logical address mapping table in storage space 801 is updated to logical address-entity Address mapping table, and remove reflecting of the physical address-logical address mapping table in mapping table memory space 801 Penetrate information.

Refer to Figure 10 b, in an alternative embodiment of the invention, when mapping table memory space 801 has been write completely When, start entity wipes the entity programming list that unit (i.e. entity wipes unit 410 (2)) has programmed valid data First is that lower entity programming unit pba (0-0), pba (0-1), pba (0-3), pba (0-5) and upper entity are compiled Cheng Danyuan pba (0-2), pba (0-4).Wherein, memorizer control circuit unit 404 (or memory management Circuit 502) judge that entity wipes the upper reality corresponding to lower entity programming unit pba (0-3) of unit 410 (2) Body programming unit pba (0-6) and the upper entity programming unit corresponding to lower entity programming unit pba (0-5) Pba (0-8) is all not yet programmed.Base this, memorizer control circuit unit 404 (or memory management circuitry 502) can by virtual data be programmed to entity wipe unit 410 (2) upper entity programming unit pba (0-6) with After upper entity programming unit pba (0-8), then by the physical address in mapping table memory space 801-logically The map information of location mapping table is updated to logical address-physical address mapping table, and it is empty to remove mapping table storage Between physical address-logical address mapping table in 801 map information.

Figure 11 is the flow chart of the mapping table updating method shown by the embodiment of the present invention.

Refer to Figure 11, in step s1101, memorizer control circuit unit 404 (or memory management Circuit 502) allocation map table memory space, with storage entity address-logical address mapping table.Specifically, Memorizer control circuit unit 404 (or memory management circuitry 502) is distribution in buffer storage 508 Mapping table memory space.

In step s1103, memorizer control circuit unit 404 (or memory management circuitry 502) is from master Machine system 11 receives many write data, and wherein, those write data belong to multiple programming in logic units.

In step s1105, memorizer control circuit unit 404 (or memory management circuitry 502) is chosen One entity erasing unit wipes unit as start entity.Specifically, memorizer control circuit unit 404 (or memory management circuitry 502) are the multiple realities from reproducible nonvolatile memorizer module 406 Choose one of them in body erasing unit and wipe unit as start entity.

In step s1107, memorizer control circuit unit 404 (or memory management circuitry 502) judges Whether the residual memory space of mapping table memory space is less than the first threshold value.First threshold value can be according to reality Demand is set as different particular values, and this part illustrates in embodiment above, will not be described here.

If the residual memory space of mapping table memory space is less than the first threshold value, in step s1109, Memorizer control circuit unit 404 (or memory management circuitry 502) will be stored in mapping table memory space Physical address-logical address mapping table in map information be updated at least one logical address-physical address Mapping table, and remove the mapping of the physical address-logical address mapping table being stored in mapping table memory space Information.Map information can updated by memorizer control circuit unit 404 (or memory management circuitry 502) To after at least one logical address-physical address mapping table, remove immediately and be stored in mapping table memory space Physical address-logical address mapping table map information.However, memorizer control circuit unit 404 (or Memory management circuitry 502) also can click through in the random time before programming next time start entity erasing unit Row is removed, and the present invention is not any limitation as.

In step s1111, memorizer control circuit unit 404 (or memory management circuitry 502) should A little write data are programmed to multiple entity programming units that start entity wipes unit, and those are write to set up programming Enter the multiple renewal map informations between multiple entity programming units of data and those programming in logic units, And store those renewal map informations to mapping table memory space.Specifically, in step s1107 In, if judging the residual memory space of mapping table memory space not less than the first threshold value, memorizer control Circuit unit 404 (or memory management circuitry 502) processed directly execution step s1111.Relatively, in step In rapid s1107, if judging that the residual memory space of mapping table memory space, less than the first threshold value, is deposited Memory control circuit unit 404 (or memory management circuitry 502) then first carries out step s1109, then executes Step s1111.Specifically, in the present embodiment, it is that write data is being programmed to start Before entity erasing unit, first judge whether the residual memory space of mapping table memory space is less than first Threshold value.However, in another embodiment, also unit can be wiped in the start entity that will write data programming Afterwards, that is, judge whether the residual memory space of mapping table memory space is less than the first threshold value, the present invention It is not any limitation as.

Figure 12 is another exemplary flowchart of the mapping table updating method shown by the embodiment of the present invention.Figure 12 is the example reality that renewal map information stores the step to mapping table memory space for Figure 11 Apply a method flow diagram.

Refer to Figure 12, store to mapping table in multiple renewal map informations that start entity is wiped unit In step in memory space, store to mapping table when only storing those parts updating map information In space and when physical address-logical address mapping table is not more than the second threshold value, in step s1201, Memorizer control circuit unit 404 (or memory management circuitry 502) can judge in start entity erasing unit Whether there is at least once entity programming unit having programmed valid data, and this at least entity programming once The corresponding upper entity programming unit of unit is not programmed.

If judging there is this at least once entity programming unit, in step in start entity erasing unit In s1203, a virtual data is compiled by memorizer control circuit unit 404 (or memory management circuitry 502) Journey is so far at least once in the corresponding upper entity programming unit of entity programming unit.

In step s1205, memorizer control circuit unit 404 (or memory management circuitry 502) will be deposited The map information of physical address-logical address mapping table in mapping table memory space for the storage is updated at least One logical address-physical address mapping table.Specifically, in step s1201, if judging do not have This at least once entity programming unit, memorizer control circuit unit 404 (or memory management circuitry 502) Then direct execution step s1205.Relatively, in step s1201, if judge have this at least one Lower entity programming unit, memorizer control circuit unit 404 (or memory management circuitry 502) then first carries out Step s1203, then execution step s1205.

In step s1207, memorizer control circuit unit 404 (or memory management circuitry 502) can be clear Except the map information of the physical address-logical address mapping table being stored in mapping table memory space, and will The remainder that those update map information stores to mapping table memory space.

In sum, the embodiment of the present invention is proposed mapping table updating method, memorizer control circuit list Unit and memory storage apparatus are stored using mapping table memory space and wipe unit corresponding to start entity The renewal map information of physical address-logical address mapping table, and deposited according to residue in mapping table memory space The size in storage space, to determine whether to will be stored in physical address in mapping table memory space-logically The map information of location mapping table is updated to logical address-physical address mapping table.When start entity wipes unit Do not write full, but need to will be stored in reflecting of the physical address-logical address mapping table in mapping table memory space Penetrate information updating to logical address-physical address mapping table, if judging sequentially programmable data Entity programming unit is upper entity programming unit, then by upper for virtual data write entity programming unit.Base This, can lift the efficiency of more new logical addresses-physical address mapping table, and avoid more new logical addresses- After physical address mapping table, the data of programming cannot be extensive because of the program fail of other entity programming units Multiple situation.

Last it is noted that various embodiments above is only in order to illustrating technical scheme rather than right It limits；Although being described in detail to the present invention with reference to foregoing embodiments, this area common Technical staff it is understood that it still can be modified to the technical scheme described in foregoing embodiments, Or equivalent is carried out to wherein some or all of technical characteristic；And these modifications or replacement, and Do not make the scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution.

Claims

1. a kind of mapping table updating method, for memory storage apparatus it is characterised in that described deposit Reservoir storage device has a reproducible nonvolatile memorizer module, and described duplicative is non-volatile Memory module has multiple entity erasing units, and each those entities erasing unit has multiple entities and compiles Cheng Danyuan, described mapping table updating method includes:

Distribute a mapping table memory space in a buffer storage, to store one physical address-logical address Mapping table；

Judge whether the residual memory space in described mapping table memory space is less than one first threshold value；

If judging that described residual memory space is less than described first threshold value, then will be stored in described mapping The map information of the described physical address-logical address mapping table in table memory space is updated at least one and patrols Collect address-physical address mapping table；

Remove the described physical address-logical address mapping table being stored in described mapping table memory space Map information；And

Many write data belonging to multiple programming in logic units are programmed among those entities erasing unit One start entity wipe unit multiple entity programming units, set up programming those write data those Multiple renewal map informations between entity programming unit and those programming in logic units, and by those more New mappings information Store is to described mapping table memory space.

2. mapping table updating method according to claim 1 is it is characterised in that reflect those renewals Penetrate the step to described mapping table memory space for the information Store to include:

When a portion that those update map information stores to described mapping table memory space and institute When stating described residual memory space no more than second threshold value in mapping table memory space, judge described Whether start entity is wiped has one at least one first instance programming unit in unit, and wherein said at least one First instance programming unit is entity programming unit, and described first instance programming unit has programmed one to be had Imitate data and the upper entity programming unit of at least one first instance programming unit described in correspondence is not programmed；

If at least one first instance programming unit described in judging to have in described start entity erasing unit When, then a virtual data is programmed to the upper entity programming of at least one first instance programming unit described in corresponding to Unit；

Compile in the upper entity that described virtual data is programmed at least one first instance programming unit described in correspondence After Cheng Danyuan, will be stored in the described physical address-logical address mapping in described mapping table memory space The map information of table be updated to described at least one logical address-physical address mapping table；And

Remove the described physical address-logical address mapping table being stored in described mapping table memory space Map information and by those update map informations remainders store to described mapping table memory space In.

3. mapping table updating method according to claim 1 is it is characterised in that described mapping table is deposited Multiple renewal map informations that the multiple programming entity of correspondence wipes unit have been stored in storage space.

4. mapping table updating method according to claim 3 is it is characterised in that also include:

One of them programming entity calculating those programming entity erasing units corresponding wipes unit more The size of new mappings information, one of them programming entity erasing unit wherein said is to write those Data is programmed to described start entity and wipes the entity finally programming before multiple entity programming units of unit Erasing unit；And

Set described one of them programming entity wipe unit renewal map information size as described First threshold value.

5. mapping table updating method according to claim 3 is it is characterised in that also include:

Calculate correspondence each those programming entity wipe unit renewal map information size；

Calculate those programming entity wipe unit renewal map information size meansigma methodss；And

Set described meansigma methodss as described first threshold value.

6. mapping table updating method according to claim 3 is it is characterised in that also include:

Identification those programming entities corresponding wipe the maximum among the size of renewal map information of unit Value；And

Set described maximum as described first threshold value.

7. mapping table updating method according to claim 1 is it is characterised in that those write data Among at least a portion data be to be produced after the many compressing original data that will be received from a host computer system Raw data.

8. a kind of memorizer control circuit unit, for controlling a reproducible nonvolatile memorizer module, It is characterized in that, described reproducible nonvolatile memorizer module has multiple entity erasing units, often One those entities erasing unit has multiple entity programming units, and described memorizer control circuit unit includes:

One HPI, is electrically connected to a host computer system；

One memory interface, is electrically connected to described reproducible nonvolatile memorizer module；With And

One memory management circuitry, is electrically connected to described HPI and described memory interface,

Wherein, described memory management circuitry is empty in order to distribute a mapping table storage in a buffer storage Between, to store one physical address-logical address mapping table,

Wherein, described memory management circuitry is also in order to judge the residue in described mapping table memory space Whether memory space is less than one first threshold value,

Wherein, if judging that described residual memory space is less than this first threshold value, described memory management Circuit is also in order to will be stored in the described physical address in described mapping table memory space-logical address mapping The map information of table is updated at least one logical address-physical address mapping table,

Wherein, described memory management circuitry is also stored in described mapping table memory space in order to remove The map information of described physical address-logical address mapping table,

Wherein, described memory management circuitry will be also in order to will belong to many writes of multiple programming in logic units Data is programmed to multiple entities programming lists that those entities wipe the start entity erasing unit among unit Unit, sets up between those entity programming units and those programming in logic units of those write data of programming Multiple renewal map informations, and those renewal map informations are stored to described mapping table memory space.

9. memorizer control circuit unit according to claim 8 is it is characterised in that work as those The a portion updating map information stores to described mapping table memory space and the storage of described mapping table When described residual memory space in space is not more than second threshold value, described memory management circuitry is also In order to judge whether there is one at least one first instance programming unit in described start entity erasing unit, its Described at least one first instance programming unit be entity programming unit, described first instance programming is single Unit has programmed valid data and the upper entity programming unit of at least one first instance programming unit described in correspondence It is not programmed,

Wherein, if at least one first instance programming described in judging to have in described start entity erasing unit During unit, described memory management circuitry also in order to by a virtual data be programmed to corresponding described at least 1 the The upper entity programming unit of one entity programming unit,

Wherein, described virtual data is being programmed to the upper of at least one first instance programming unit described in correspondence After entity programming unit, described memory management circuitry is also empty in order to will be stored in described mapping table storage Between in described physical address-logical address mapping table map information be updated to described at least one logically Location-physical address mapping table,

Wherein, described memory management circuitry is also stored in described mapping table memory space in order to remove The map information of described physical address-logical address mapping table and by those update map informations remaining Part stores to described mapping table memory space.

10. memorizer control circuit unit according to claim 8 is it is characterised in that described reflect Multiple renewal map informations that the multiple programming entity of correspondence wipes unit have been stored in firing table memory space.

11. memorizer control circuit units according to claim 10 are it is characterised in that described deposit Reservoir manages circuit and also wipes one of them of unit and programmed reality in order to calculate those programming entities corresponding Body wipes the size of the renewal map information of unit, and one of them programming entity wherein said wipes unit It is before those write data are programmed to multiple entity programming units that described start entity wipes unit The entity erasing unit finally programming,

Wherein said memory management circuitry also wipes unit in order to set one of them programming entity described Renewal map information size as described first threshold value.

12. memorizer control circuit units according to claim 10 are it is characterised in that described deposit Reservoir manage circuit also in order to calculate correspondence each those programming entity wipe unit renewal map information Size,

Wherein, described memory management circuitry also in order to calculate those programming entity wipe unit renewal One meansigma methodss of the size of map information,

Wherein, described memory management circuitry is also in order to set described meansigma methodss as described first threshold value.

13. memorizer control circuit units according to claim 10 are it is characterised in that described deposit Reservoir manage circuit also in order to calculate correspondence each those programming entity wipe unit renewal map information Size,

Wherein said memory management circuitry also wipes unit more in order to identify those programming entities corresponding A maximum among the size of new mappings information,

Wherein said memory management circuitry is also in order to set described maximum as described first threshold value.

14. memorizer control circuit units according to claim 8 are it is characterised in that those are write Entering at least a portion data among data is will be from described host computer system by described memory management circuitry Produced data after the many compressing original data being received.

A kind of 15. memory storage apparatus are it is characterised in that include:

One connecting interface unit, is electrically connected to a host computer system；

One reproducible nonvolatile memorizer module, wipes unit, those realities each including multiple entities Body erasing unit has multiple entity programming units；And

One memorizer control circuit unit, is electrically connected to described connecting interface unit and described duplicative Non-volatile memory module,

Wherein, described memorizer control circuit unit is deposited in order to distribute a mapping table in a buffer storage Storage space, in order to store one physical address-logical address mapping table,

Wherein, described memorizer control circuit unit is also in order to judge in described mapping table memory space Whether residual memory space is less than one first threshold value,

Wherein, if judging that described residual memory space is less than described first threshold value, described memorizer control Circuit unit processed is also in order to will be stored in the described physical address in described mapping table memory space-logically The map information of location mapping table is updated at least one logical address-physical address mapping table,

Wherein, described memorizer control circuit unit is also stored in described mapping table memory space in order to remove In described physical address-logical address mapping table map information,

Wherein, described memorizer control circuit unit will be also in order to will belong to many of multiple programming in logic units Write data is programmed to multiple entities volumes that those entities wipe the start entity erasing unit among unit Cheng Danyuan, set up those write data of programming those entity programming units and those programming in logic units it Between multiple renewal map informations, and those renewal map informations are stored store to described mapping table empty Between in.

16. memory storage apparatus according to claim 15 are it is characterised in that work as by those more A portion of new mappings information stores to described mapping table memory space and the storage of described mapping table is empty Between in described residual memory space be not more than second threshold value when, described memorizer control circuit unit Also in order to judge whether there is one at least one first instance programming unit in described start entity erasing unit, Wherein said at least one first instance programming unit is entity programming unit, described first instance programming Unit has programmed valid data and the upper entity programming of at least one first instance programming unit described in correspondence is single Unit is not programmed,

Wherein, if at least one first instance programming described in judging to have in described start entity erasing unit During unit, described memorizer control circuit unit is also in order to be programmed to described in correspondence at least a virtual data The upper entity programming unit of one first instance programming unit,

Wherein, described virtual data is being programmed to the upper of at least one first instance programming unit described in correspondence After entity programming unit, described memorizer control circuit unit is also deposited in order to will be stored in described mapping table The map information of the described physical address-logical address mapping table in storage space at least one is patrolled described in being updated to Collect address-physical address mapping table,

Wherein, described memorizer control circuit unit is also stored in described mapping table memory space in order to remove In the map information of described physical address-logical address mapping table and those are updated map informations Remainder stores to described mapping table memory space.

17. memory storage apparatus according to claim 15 are it is characterised in that described mapping table Multiple renewal map informations that the multiple programming entity of correspondence wipes unit have been stored in memory space.

18. memory storage apparatus according to claim 17 are it is characterised in that described memorizer Control circuit unit is also wiped one of them of unit and has been programmed reality in order to calculate those programming entities corresponding Body wipes the size of the renewal map information of unit, and one of them programming entity wherein said wipes unit It is before those write data are programmed to multiple entity programming units that described start entity wipes unit The entity erasing unit finally programming,

Wherein said memorizer control circuit unit is also in order to set one of them programming entity erasing described The size of the renewal map information of unit is as described first threshold value.

19. memory storage apparatus according to claim 17 are it is characterised in that described memorizer Control circuit unit also in order to calculate correspondence each those programming entity wipe unit renewal map information Size,

Wherein, described memorizer control circuit unit also wipes unit in order to calculate those programming entities Update meansigma methodss of the size of map information,

Wherein, described memorizer control circuit unit is also in order to set described meansigma methodss as described first Threshold value.

20. memory storage apparatus according to claim 17 are it is characterised in that described memorizer Control circuit unit also in order to calculate correspondence each those programming entity wipe unit renewal map information Size,

Wherein said memorizer control circuit unit also wipes unit in order to identify those programming entities corresponding Renewal map information size among a maximum,

Wherein said memorizer control circuit unit is also in order to set described maximum as described first threshold Value.

21. memory storage apparatus according to claim 15 are it is characterised in that those write number According among at least a portion data be will be from described host computer system by described memorizer control circuit unit Produced data after the many compressing original data being received.