CN103577346A - Memory control method and memory control circuit - Google Patents
Memory control method and memory control circuit Download PDFInfo
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- CN103577346A CN103577346A CN201310218907.0A CN201310218907A CN103577346A CN 103577346 A CN103577346 A CN 103577346A CN 201310218907 A CN201310218907 A CN 201310218907A CN 103577346 A CN103577346 A CN 103577346A
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Abstract
The invention provides a memory control method and a memory control circuit. The memory control method comprises the steps of writing a write data having a logical address into a write data temporary memory; generating a write-in address comparison table of a physical address in a main memory corresponding to the logical address, and writing the write data into the caching data comparison table; writing the write data into the main memory based on the write-in address comparison table; writing the caching data comparison table into the main memory when the available storing space of the temporary memory reaches to a predetermined critical value, and recording the corresponding main memory write-in address comparison table into an integral comparison table contemporary memory.
Description
Technical field
Disclosed embodiment of this invention is relevant to storer and controls, memory control methods and the interlock circuit of espespecially a kind of page grade (page-level).
Background technology
Solid state hard disc (Solid State Drive in recent years, SSD) (for example Sheffer stroke gate flash memory (NAND flash)) consolidates its status in storing media market gradually, and is used in widely among PC and various mobile device.Compared to conventional hard, solid state hard disc, without any need for mechanical organ, does not have to search and rotate the delay causing, therefore comparatively power saving, yet the usefulness of flash memory can be subject to the impact of data payload, for example, solid state hard disc is carried out random read-write and reads and writes and have very large physical variation continuously.Wherein, flash memory conversion layer (Flash Translation Layer, FTL) has been responsible for the conversion between virtual address and physical address, so the design of flash memory conversion layer is just quite important for the usefulness of solid state hard disc.
Traditionally, in the middle of flash memory conversion layer, can use a random access memory (random access memory, RAM) record the conversion table of comparisons between virtual address and physical address, yet, along with the capacity requirement of flash memory is more and more higher, relatively, random access memory size in the middle of flash memory conversion layer also can and then increase, especially when flash memory conversion layer adopt be comparatively tiny page grade (page-level) the address contrast mode of unit time, can increase rapidly small product size and manufacturing cost.Therefore, the usefulness while carrying out random read-write in order to reduce the demand to random access memory in solid state hard disc system, can to take into account again solid state hard disc, just needs a kind of page class stores device control method of innovation.
Summary of the invention
One of object of the present invention is to provide a kind of page class stores device control method and interlock circuit to improve above-mentioned problem.
According to the first embodiment of the present invention, a kind of memory control methods is disclosed.This memory control methods includes: a data writing with a logical address is write in a data writing temporary storage (cache buffer); This logical address that produces this data writing corresponds to a writing address table of comparisons of the physical address in a main storer, and is write to a buffer memory (cached) the data table of comparisons and write in temporary storage; This data writing is write to this main storer according to this writing address table of comparisons; And if the available storage area that this data cached table of comparisons writes temporary storage reaches a predetermined critical, this writing address table of comparisons this data cached table of comparisons being write in temporary storage writes in this main storer, and a corresponding main storer writing address table of comparisons is recorded in a whole table of comparisons temporary storage.
According to a second embodiment of the present invention, a kind of memory control methods is disclosed.This memory control methods includes: a logical address of the reading out data that search is wanted to read in a data cached table of comparisons writes temporary storage corresponds to a reading address table of comparisons of the physical address in a main storer; If this reading address table of comparisons is present in this data cached table of comparisons, write in temporary storage, this reading out data with this physical address is read out from this main storer, and write in a reading out data temporary storage.
A third embodiment in accordance with the invention, discloses a kind of memorizer control circuit.This memorizer control circuit includes: a data writing temporary storage, a data cached table of comparisons write temporary storage and a whole table of comparisons temporary storage.Wherein this data writing temporary storage is used for storing a data writing with a logical address; This data cached table of comparisons writes the writing address table of comparisons that this logical address that temporary storage is used for storing this data writing corresponds to the physical address in a main storer; And this integral body table of comparisons temporary storage available storage area of being used for writing temporary storage at this data cached table of comparisons is while reaching a predetermined critical, stores the corresponding main storer writing address table of comparisons that this data cached table of comparisons being written in this main storer writes this writing address table of comparisons in temporary storage.
A fourth embodiment in accordance with the invention, discloses a kind of memorizer control circuit.This memorizer control circuit includes: a data cached table of comparisons reads temporary storage, a reading out data temporary storage and a whole table of comparisons temporary storage.Wherein this data cached table of comparisons reads the reading address table of comparisons that a logical address that temporary storage is used for storing the reading out data wanting to read corresponds to the physical address in a main storer; This reading out data temporary storage is used for storing this reading out data with this physical address reading out from this main storer; And this integral body table of comparisons temporary storage is used for finding out this reading address table of comparisons from this main storer.
The present invention, in the situation that the read-write usefulness of excessive influence random data not replaces traditional temporary storage with the sub-fraction space in main storer, can increase the elasticity of hardware on the one hand, can reduce significantly cost again on the other hand.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of an one exemplary embodiment of storer write-in control method of the present invention.
Fig. 2 is the process flow diagram of an one exemplary embodiment of storer reading and control method thereof of the present invention.
Fig. 3 is the schematic diagram of an one exemplary embodiment of storage control device of the present invention.
[symbol description]
200～204 steps
300 storage control devices
302 serial advanced technology attachment impact dampers
304 first direct memory access (DMA) unit
306 processors
308 reading out data temporary storages
310 data writing temporary storages
The 312 data cached tables of comparisons read temporary storage
The 314 data cached tables of comparisons write temporary storage
316 whole table of comparisons temporary storages
320 second direct memory access (DMA) unit
322 Sheffer stroke gate flash memories
Embodiment
In the middle of instructions and follow-up claims, used some vocabulary to censure specific element.Person with usual knowledge in their respective areas should understand, and same element may be called with different nouns by manufacturer.This instructions and follow-up claims are not used as distinguishing the mode of element with the difference of title, but the difference in function is used as the criterion of distinguishing with element.In the whole text, in the middle of instructions and follow-up claims, be an open term mentioned " comprising ", therefore should be construed to " comprise but be not limited to ".In addition, " coupling " word comprises directly any and is indirectly electrically connected means at this.Therefore, if describe a first device in literary composition, be coupled to one second device, represent that this first device can directly be electrically connected in this second device, or be indirectly electrically connected to this second device by other devices or connection means.
Please refer to Fig. 1, Fig. 1 is the process flow diagram of an one exemplary embodiment of storer write-in control method of the present invention.If can reach identical result substantially, do not need necessarily in accordance with the sequence of steps in the flow process shown in Fig. 1, to carry out, and the step shown in Fig. 1 not necessarily will be carried out continuously, that is other steps also can be inserted wherein, in addition, some step in Fig. 1 also can be omitted it according to different embodiment or design requirement.The method includes following steps:
Step 100 a: data writing with a logical address is write in a data writing temporary storage;
Step 102: this logical address that produces this data writing corresponds to a writing address table of comparisons of the physical address in a main storer, and write to a data cached table of comparisons and write in temporary storage;
Step 104: this data writing is write to this main storer according to this writing address table of comparisons; And
Step 106: reach a predetermined critical if this data cached table of comparisons writes the available storage area of temporary storage, this writing address table of comparisons this data cached table of comparisons being write in temporary storage writes in this main storer, and a corresponding main storer writing address table of comparisons is recorded in a whole table of comparisons temporary storage.
About the storer write-in control method shown in Fig. 1, please also refer to Fig. 3, the schematic diagram of the one exemplary embodiment that Fig. 3 is storage control device of the present invention.Storage control device 300 is in order to by the logic page number on upper strata (logical page number, LPN) be converted to the entity page number (the physical page number in solid state hard disc, PPN), and include serial advanced technology attachment (SATA) impact damper 302, one first direct memory access (DMA) unit (Direct Memory Access, DMA) 304, one processor 306, one reading out data temporary storage 308, one data writing temporary storage 310, the one data cached table of comparisons reads temporary storage 312, the one data cached table of comparisons writes temporary storage 314, one whole table of comparisons temporary storage 316, one second direct memory access (DMA) unit 320 and a Sheffer stroke gate flash memory 322.When upper system wish, that Sheffer stroke gate flash memory 322 is carried out to writing of a specific data writing is fashionable, first this specific data writing is sequentially write to this specific data writing in data writing temporary storage 310 by the first direct memory access (DMA) unit 304 via SATA impact damper 302, i.e. step 100.Simultaneously, one logical address of processor 306 these specific data writings of meeting generation corresponds to a writing address table of comparisons of the physical address in Sheffer stroke gate flash memory 322, and write to the data cached table of comparisons and write in temporary storage 314, be i.e. step 102.Please note, storage control device 300 of the present invention can be for take memory data read-write and the address contrast that page grade (page-level) is unit, for instance, if each page size is 8K bit group in Sheffer stroke gate flash memory 322, no matter each cell size of upper strata SATA is why, the first direct memory access (DMA) unit 304 all can be sequentially temporary in data writing temporary storage 310, to waiting a little while,please, collecting a full page just can be write in Sheffer stroke gate flash memory 322 by the second direct memory access (DMA) unit 320, it is step 104.It should be noted, storage control device 300 in the present embodiment is in order to control a SATA equipment end (being Sheffer stroke gate flash memory 322), and in order to link a SATA main control end by SATA impact damper 302 and the first direct memory access (DMA) unit 304, yet in fact the present invention is not defined in SATA system, for instance, the direct memory access (DMA) unit that SATA impact damper 302 and the first direct memory access (DMA) unit 304 can be changed to USB (universal serial bus) 3.0 (USB3.0) impact damper and meet USB3.0 standard, in addition, Sheffer stroke gate flash memory 322 can also be changed to the solid-state memory of other kinds.Variation in these designs all falls into category of the present invention.
The size that the data cached table of comparisons in the present embodiment writes temporary storage 314 is 64k bit group, yet this is only as the use of example explanation, is not restriction of the present invention place.If writing the available storage area of temporary storage 314, the data cached table of comparisons reaches one while writing predetermined critical T1, first the data cached table of comparisons is write to the writing address table of comparisons in temporary storage 314 and for example, by fixed size (8M bit group), give group for interval unit according to its logical address, according to group, write in Sheffer stroke gate flash memory 322 again, last and a corresponding main storer writing address table of comparisons is recorded in whole table of comparisons temporary storage 316, i.e. step 106.It should be noted, in the present embodiment, in Sheffer stroke gate flash memory 322, can retain millesimal space (not as limit) depositing for this writing address table of comparisons, yet when the data cached table of comparisons is write to this writing address table of comparisons in temporary storage 314 and writes to Sheffer stroke gate flash memory 322, do not need to be write in the specific region of distinguishing to some extent with general data in Sheffer stroke gate flash memory 322, in other words, this writing address table of comparisons in Sheffer stroke gate flash memory 322 is to can be mixed in general data (that is be used as general data carry out data write processing), when needing use afterwards, can find this corresponding writing address table of comparisons according to this main storer writing address table of comparisons recording in whole table of comparisons temporary storage 316, thus, can avoid the access times of specific region in Sheffer stroke gate flash memory 322 higher than the situation in general data region, to cause the early ageing of memory component, on the other hand, in traditional practice, all writing address tables of comparisons need to be recorded in temporary storage, and along with the increase of storer, often need to account for that the size of depositing storer is increased to dozens of or more than hundreds of megabit tuples, the present invention uses a fraction of space in Sheffer stroke gate flash memory 322, can increase on the one hand the elasticity of hardware, can reduce significantly cost again on the other hand.
Please refer to Fig. 2, Fig. 2 is the process flow diagram of an one exemplary embodiment of storer reading and control method thereof of the present invention.If can reach identical result substantially, do not need necessarily in accordance with the sequence of steps in the flow process shown in Fig. 2, to carry out, and the step shown in Fig. 2 not necessarily will be carried out continuously, that is other steps also can be inserted wherein, in addition, some step in Fig. 2 also can be omitted it according to different embodiment or design requirement.The method includes following steps:
Step 200 a: logical address of the reading out data that search is wanted to read in a data cached table of comparisons reads temporary storage corresponds to a reading address table of comparisons of the physical address in a main storer;
Step 202: write in temporary storage if this reading address table of comparisons is present in this data cached table of comparisons, this reading out data with this physical address is read out from this main storer, and write in a reading out data temporary storage;
Step 204: do not write in temporary storage if this reading address table of comparisons is not present in this data cached table of comparisons, search a data cached table of comparisons and read temporary storage;
Step 206: read in temporary storage if this reading address table of comparisons is present in this data cached table of comparisons, this reading out data with this physical address is read out from this main storer, and write in this reading out data temporary storage;
Step 208: this data cached table of comparisons writes temporary storage and this data cached table of comparisons reads in temporary storage if this reading address table of comparisons is not present in, and searches a whole table of comparisons temporary storage; And
Step 210: by this integral body table of comparisons temporary storage, this reading address table of comparisons is read to from this main storer to this data cached table of comparisons and read in temporary storage, and this reading out data with this physical address is read out from this main storer, and write in this reading out data temporary storage.
Similarly, please also refer to Fig. 2 and Fig. 3.When upper system is wanted to read in Sheffer stroke gate flash memory 322 a specific reading out data, one logical address of the processor 306 meeting requirement reading out datas that search is wanted to read in a data cached table of comparisons writes temporary storage 314 corresponds to a reading address table of comparisons of the physical address in a main storer, i.e. step 200.If being present in this data cached table of comparisons, this reading address table of comparisons writes in temporary storage 314, the second direct memory access (DMA) unit 320 can read out this reading out data with this physical address from Sheffer stroke gate flash memory 322, and write in a reading out data temporary storage in 308 i.e. step 202.If this reading address table of comparisons is not present in the data cached table of comparisons, do not write in temporary storage 314, search a data cached table of comparisons and read temporary storage 312, i.e. step 204.Next, if being present in the data cached table of comparisons, reads in temporary storage 312 by this reading address table of comparisons, the second direct memory access (DMA) unit 320 can read out this reading out data with this physical address from Sheffer stroke gate flash memory 322, and write in reading out data temporary storage 308 i.e. step 206.Yet the data cached table of comparisons writes temporary storage 314 and the data cached table of comparisons reads in temporary storage 312 if this reading address table of comparisons is not present in, search whole table of comparisons temporary storage 316, i.e. a step 208.Finally, in step 210, by whole table of comparisons temporary storage 316, this reading address table of comparisons being read to the data cached table of comparisons from Sheffer stroke gate flash memory 322 reads in temporary storage 312, and this reading out data with this physical address is read out from Sheffer stroke gate flash memory 322, and write in reading out data temporary storage 308.In addition, the size that the data cached table of comparisons in the present embodiment reads temporary storage 312 is 16k bit group, yet this is only as the use of example explanation, is not restriction of the present invention place.The present invention, in the situation that the read-write usefulness of excessive influence random data not replaces traditional temporary storage with the sub-fraction space in main storer, increases the elasticity of hardware on the one hand, has reduced significantly again on the other hand cost.
Claims (13)
1. a memory control methods, includes:
One data writing with a logical address is write in a data writing temporary storage;
This logical address that produces this data writing corresponds to a writing address table of comparisons of the physical address in a main storer, and is write to a data cached table of comparisons and write in temporary storage;
This data writing is write to this main storer according to this writing address table of comparisons; And
If writing the available storage area of temporary storage, this data cached table of comparisons reaches a predetermined critical, this writing address table of comparisons this data cached table of comparisons being write in temporary storage writes in this main storer, and a corresponding main storer writing address table of comparisons is recorded in a whole table of comparisons temporary storage.
2. memory control methods as claimed in claim 1, is characterized in that, this main storer is a Sheffer stroke gate flash memory.
3. memory control methods as claimed in claim 1, is characterized in that, it is the control method based on page grade.
4. memory control methods as claimed in claim 1, is characterized in that, this data cached table of comparisons is write to the step that this writing address table of comparisons in temporary storage writes in this main storer and include:
This writing address table of comparisons that this data cached table of comparisons is write in temporary storage writes in this main storer, and without being write in the specific region of distinguishing to some extent with general data in this main storer.
5. a memory control methods, includes:
One logical address of the reading out data that search is wanted to read in a data cached table of comparisons writes temporary storage corresponds to a reading address table of comparisons of the physical address in a main storer;
If this reading address table of comparisons is present in this data cached table of comparisons, write in temporary storage, this reading out data with this physical address is read out from this main storer, and write in a reading out data temporary storage.
6. memory control methods as claimed in claim 5, is characterized in that, separately includes:
If this reading address table of comparisons is not present in this data cached table of comparisons, do not write in temporary storage, search a data cached table of comparisons and read temporary storage;
If this reading address table of comparisons is present in this data cached table of comparisons, read in temporary storage, this reading out data with this physical address is read out from this main storer, and write in this reading out data temporary storage.
7. memory control methods as claimed in claim 5, is characterized in that, separately includes:
If this reading address table of comparisons is not present in, this data cached table of comparisons writes temporary storage and this data cached table of comparisons reads in temporary storage, searches a whole table of comparisons temporary storage;
By this integral body table of comparisons temporary storage, this reading address table of comparisons being read to from this main storer to this data cached table of comparisons reads in temporary storage, and this reading out data with this physical address is read out from this main storer, and write in this reading out data temporary storage.
8. memory control methods as claimed in claim 5, is characterized in that, this main storer is a Sheffer stroke gate flash memory.
9. memory control methods as claimed in claim 5, is characterized in that, it is the control method based on page grade.
10. a memorizer control circuit, includes:
One data writing temporary storage, is used for storing a data writing with a logical address;
The one data cached table of comparisons writes temporary storage, and this logical address that is used for storing this data writing corresponds to a writing address table of comparisons of the physical address in a main storer; And
One whole table of comparisons temporary storage, when the available storage area that is used for writing temporary storage at this data cached table of comparisons reaches a predetermined critical, store the corresponding main storer writing address table of comparisons that this data cached table of comparisons being written in this main storer writes this writing address table of comparisons in temporary storage.
11. memorizer control circuits as claimed in claim 10, is characterized in that, it is the memorizer control circuit based on page grade.
12. 1 kinds of memorizer control circuits, include:
The one data cached table of comparisons reads temporary storage, and a logical address that is used for storing the reading out data wanting to read corresponds to a reading address table of comparisons of the physical address in a main storer;
One reading out data temporary storage, is used for storing this reading out data with this physical address reading out from this main storer; And
One whole table of comparisons temporary storage, is used for finding out this reading address table of comparisons from this main storer.
13. memorizer control circuits as claimed in claim 12, is characterized in that, it is the memorizer control circuit based on page grade.
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| US201261673706P | 2012-07-19 | 2012-07-19 | |
| US61/673,706 | 2012-07-19 |
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Cited By (2)
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| CN106372000A (en) * | 2015-07-20 | 2017-02-01 | 群联电子股份有限公司 | Update method for mapping table, control circuit unit of memory, and storage device of memory |
| CN114077559A (en) * | 2020-08-11 | 2022-02-22 | 慧荣科技股份有限公司 | Method and apparatus for access management of storage device |
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| TWI530787B (en) | 2014-06-05 | 2016-04-21 | 宏碁股份有限公司 | Electronic device and method for writing data |
| TWI664568B (en) | 2016-11-15 | 2019-07-01 | 慧榮科技股份有限公司 | Operating method of data storage device |
| TWI631167B (en) | 2017-12-25 | 2018-08-01 | 財團法人工業技術研究院 | Monomer, resin composition, prepreg, and copper clad laminate |
| TWI656158B (en) | 2017-12-25 | 2019-04-11 | 聯茂電子股份有限公司 | Resin composition, film, and copper foil substrate |
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| TW201405311A (en) | 2014-02-01 |
| TWI475387B (en) | 2015-03-01 |
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Application publication date: 20140212 |