TWI475387B - Memory control method and memory control circuit thereof - Google Patents

Description

Memory control method and memory control circuit

The embodiments disclosed herein relate to memory control, and more particularly to a page-level memory control method and associated circuitry.

In recent years, solid state drives (SSDs) (such as NAND flash) have gradually consolidated their position in the storage media market and are widely used in personal computers and various mobile devices. in. Compared with the traditional hard disk, the solid state hard disk does not need any mechanical components, and there is no delay caused by searching and rotating, so it is more power-saving. However, the performance of the flash memory is affected by the data load, for example, the solid state hard disk. Random read and write and continuous read and write have great performance differences. Among them, the Flash Translation Layer (FTL) is responsible for the conversion between the virtual address and the physical address, so the design of the flash memory conversion layer is very important for the performance of the solid state drive.

Traditionally, a random access memory (RAM) is used in the flash memory translation layer to record the conversion table between the virtual address and the physical address. However, with the flash memory The capacity requirements are getting higher and higher. In contrast, the size of the random access memory in the flash memory conversion layer will also increase, especially when the flash memory conversion layer uses a relatively small page level (page- Level) When the address is compared, it will increase the product volume and manufacturing cost quickly. Therefore, in order to reduce the demand for random access memory in a solid state hard disk system, and to be able to balance the performance of a solid state hard disk for random reading and writing, an innovative page level memory control method is needed.

One of the objects of the present invention is to provide a page level memory control method and related circuitry to improve the above problems.

According to a first embodiment of the present invention, a memory control method is disclosed. The memory control method includes: writing a write data having a logical address to a write data temporary storage memory; and generating the logical address of the write data corresponding to a main memory a write address comparison table of a physical address, and write it to a cache data comparison table to be written into the temporary storage memory; the write data is written according to the write address comparison table to The main memory; and if the available storage space of the cache data comparison table written to the temporary storage memory reaches a predetermined threshold, the cache data comparison table is written into the write address in the temporary storage memory. The comparison table is written into the main memory, and a corresponding primary memory write address comparison table is recorded in a global comparison table temporary storage memory.

According to a second embodiment of the present invention, a memory control method is disclosed. The memory control method includes: searching a cache data in a temporary memory to search for one of the read data to be read, and the logical address corresponding to a physical address in a main memory a read address comparison table; if the read address comparison table is present in the cache data comparison table and written in the temporary storage memory, the read data having the physical address is from the primary memory It is read out and written to a read data temporary memory.

According to a third embodiment of the present invention, a memory control circuit is disclosed. The memory control circuit includes: a write data temporary storage memory, a cache data comparison table write to the temporary storage memory, and a global comparison table temporary storage memory. The write data temporary storage memory system is configured to store a write data having a logical address; the cache data comparison table is written to the temporary memory system for storing the logical data address of the write data corresponding to the a write address comparison table of a physical address in a primary memory; and the overall comparison table temporary storage memory system is used to write the cache data comparison table When the available storage space of the memory reaches a predetermined threshold, storing the cache data read table written in the main memory into the corresponding address of the write address comparison table in the temporary memory A primary memory write address comparison table.

According to a fourth embodiment of the present invention, a memory control circuit is disclosed. The memory control circuit includes: a cache data comparison table read temporary storage memory, a read data temporary storage memory, and a global comparison table temporary storage memory. The cache data comparison table reads a read address of a read data stored in the temporary memory system for storing a read data corresponding to a physical address in a main memory. a read data temporary storage memory system for storing the read data having the physical address read from the primary memory; and the overall comparison table temporary storage memory system for using the primary memory Find the read address comparison table in the body.

The invention replaces the traditional temporary memory by using a small part of the space in the main memory without excessively affecting the read/write performance of the random data, and on the other hand, can increase the elasticity of the hardware, and on the other hand, can greatly increase The ground has reduced costs.

200~204‧‧‧Steps

300‧‧‧ memory control device

302‧‧‧Serial Advanced Technology Attachment Buffer

304‧‧‧First Direct Memory Access Unit

306‧‧‧ Processor

308‧‧‧Read data temporary storage memory

310‧‧‧Write data temporary storage memory

312‧‧‧ Cache data comparison table to read temporary memory

314‧‧‧Cache data comparison table written to temporary memory

316‧‧‧Overall comparison table temporary memory

320‧‧‧Second direct memory access unit

322‧‧‧Anti-gate flash memory

1 is a flow chart of an exemplary embodiment of a memory write control method of the present invention.

2 is a flow chart of an exemplary embodiment of a memory read control method of the present invention.

Figure 3 is a schematic diagram of an exemplary embodiment of a memory control device of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. Throughout The "contains" mentioned in the specification and subsequent claims are an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

Please refer to FIG. 1. FIG. 1 is a flow chart of an exemplary embodiment of a memory write control method according to the present invention. If the same result is substantially achieved, it is not necessary to follow the sequence of steps in the flow shown in FIG. 1, and the steps shown in FIG. 1 do not have to be performed continuously, that is, other steps may be inserted therein. In addition, some of the steps in FIG. 1 may also be omitted in accordance with different embodiments or design requirements. The method includes the following steps: Step 100: Write a write data having a logical address into a write data temporary storage memory; Step 102: Generate the logical address corresponding to the write data corresponding to a write address comparison table of a physical address in a main memory, and writing it to a cache data comparison table to be written into the temporary storage memory; Step 104: writing the data according to the write The address comparison table is written to the main memory; and step 106: if the cache data is written into the temporary storage memory, the available storage space reaches a predetermined threshold, and the cache data comparison table is written. The write address comparison table in the temporary memory is written into the main memory, and a corresponding primary memory write address comparison table is recorded in a global comparison table temporary storage memory.

Regarding the memory write control method shown in Fig. 1, reference is made to Fig. 3, which is a schematic diagram of an exemplary embodiment of the memory control device of the present invention. Memory control device The 300 series is used to convert the upper logical page number (LPN) into a physical page number (PPN) in the solid state hard disk, and includes a serial advanced technology attachment (SATA) buffer 302, a first a direct memory access unit (DMA) 304, a processor 306, a read data temporary storage memory 308, a write data temporary storage memory 310, a cache data comparison table read temporarily The memory 312 and a cache data comparison table are written into the temporary storage memory 314, a global comparison table temporary storage memory 316, a second direct memory access unit 320, and a reverse gate flash memory 322. When the upper layer system wants to write a specific write data to the gate flash memory 322, the specific write data is first sequentially sent to the first direct memory access unit 304 via the SATA buffer 302. The specific write data is written into the write data temporary storage 310, step 100. At the same time, the processor 306 generates a logical address corresponding to the specific write data corresponding to a write address comparison table of a physical address in the gate flash memory 322, and writes it to the fast The data comparison table is written into the temporary storage memory 314, that is, step 102. Please note that the memory control device 300 of the present invention can read and write and address the memory data in units of page-level, for example, if each of the gate flash memory 322 is reversed. The page size is 8K bytes, and regardless of the size of each unit of the upper SATA, the first direct memory access unit 304 temporarily stores it in the write data temporary storage 310, at least to be full. A page is written to the inverse gate flash memory 322 via the second direct memory access unit 320, step 104. It should be noted that the memory control device 300 in this embodiment is used to control a SATA device end (ie, the anti-gate flash memory 322), and to pass through the SATA buffer 302 and the first direct memory. The unit 304 is connected to a SATA host. However, the present invention is not limited to the SATA system. For example, the SATA buffer 302 and the first direct memory access unit 304 can be changed to a universal serial bus 3.0 (USB). 3.0) Buffers and direct memory access units conforming to the USB 3.0 specification, in addition, the gate flash memory 322 can be changed to other types of solid state memory. These design variations are within the scope of the present invention.

The cache data comparison table in this embodiment is written into the size 64k of the temporary storage memory 314. Bytes, however, are for illustrative purposes only and are not limiting of the invention. If the available storage space of the cache data comparison table written to the temporary storage memory 314 reaches a write predetermined threshold T1, the cache data comparison table is first written into the write address comparison table in the temporary storage memory 314. According to the logical address, the group is grouped according to a fixed size (for example, 8M bytes), and then written into the anti-gate flash memory 322 according to the group, and finally a corresponding main memory The body write address comparison table is recorded in the overall lookup table temporary storage memory 316, step 106. It should be noted that, in this embodiment, one thousandth of the space is reserved in the anti-gate flash memory 322 (not limited thereto) for the storage of the write address comparison table, but the cache will be cached. When the data comparison table is written to the write address comparison table in the temporary memory 314, the write to the flash memory 322 does not need to be written into the inverse flash memory 322. In a specific area where the general information is different, in other words, the write address comparison table in the gate flash memory 322 can be mixed into the general data (that is, as general data for data writing). Processing), after the need to use, according to the main memory write address comparison table recorded in the overall comparison table temporary storage memory 316 to find the corresponding write address comparison table, so that It is avoided that the number of accesses of a specific area in the gate flash memory 322 is higher than that of the general data area, resulting in premature fading of the memory element. On the other hand, in the conventional method, all the write address comparison tables are required. Recorded in the temporary memory, and as the memory increases In addition, it is often necessary to increase the size of the occupied memory to several tens or hundreds of megabytes; the present invention borrows a small portion of the space in the gate flash memory 322, on the one hand Increase the flexibility of the hardware, on the other hand, the cost can be greatly reduced.

Please refer to FIG. 2, which is a flow chart of an exemplary embodiment of a memory read control method according to the present invention. If the same result is generally achieved, it is not necessary to follow the sequence of steps in the flow shown in FIG. 2, and the steps shown in FIG. 2 do not have to be performed continuously, that is, other steps may be inserted therein. In addition, some of the steps in FIG. 2 may also be omitted according to different embodiments or design requirements. The method includes the following steps: Step 200: Searching the temporary memory in a cache data comparison table to search for a read bit of a read data to be read. A logical address corresponding to a physical address in a main memory Address comparison table; Step 202: If the read address comparison table exists in the cache data comparison table and writes to the temporary storage memory, the read data having the physical address is read from the primary memory Extracting and writing to a read data temporary storage memory; Step 204: If the read address comparison table does not exist in the cache data comparison table and writing to the temporary storage memory, searching for a cache The data comparison table reads the temporary storage memory; step 206: if the read address comparison table exists in the cache data comparison table and reads the temporary storage memory, the read data having the physical address is The main memory is read out and written into the read data temporary storage memory; step 208: if the read address comparison table does not exist in the cache data comparison table and written into the temporary storage memory and The cache data comparison table is read into the temporary memory, and then a global comparison table is searched. And storing the memory; and reading the read address comparison table from the main memory to the cache data comparison table to read the temporary storage memory by using the overall comparison table temporary storage memory, And the read data having the physical address is read from the main memory and written into the read data temporary storage memory.

Similarly, please refer to Figures 2 and 3 together. When the upper layer system wants to read a specific read data in the anti-gate flash memory 322, the processor 306 may request a cache data comparison table to be written into the temporary memory 314 to search for the read to be read. One of the logical addresses of the data corresponds to a read address comparison table of a physical address in a primary memory, step 200. If the read address comparison table is stored in the cache data comparison table and written in the temporary storage memory 314, the second direct memory access unit 320 will reverse the read data having the physical address. The gate flash memory 322 reads out and writes it into a read data temporary storage memory 308, step 202. If If the read address comparison table is not present in the cache data comparison table and is written in the temporary storage memory 314, the cache data comparison table is searched for the temporary storage memory 312, that is, step 204. Next, if the read address comparison table exists in the cache data comparison table read temporary storage memory 312, the second direct memory access unit 320 will read the read data having the physical address from The gate flash memory 322 is read out and written to the read data temporary storage memory 308, step 206. However, if the read address comparison table does not exist in the cache data comparison table write temporary storage memory 314 and the cache data comparison table read temporary storage memory 312, then search for a global comparison table temporary storage memory 316, step 208. Finally, in step 210, the read address comparison table is read from the inverse gate flash memory 322 by the overall lookup table temporary storage memory 316 to the cache data comparison table to read the temporary storage memory. In 312, the read data having the physical address is read from the inverse gate flash memory 322 and written into the read data temporary storage memory 308. In addition, the cache data comparison table in this embodiment reads the size of the temporary storage memory 312 by 16k bytes. However, this is for illustrative purposes only and is not a limitation of the present invention. The invention replaces the traditional temporary storage memory by using a small part of the space in the main memory without excessively affecting the read/write performance of the random data, thereby increasing the elasticity of the hardware and greatly reducing the elasticity on the other hand. The cost.

100~106‧‧‧Steps

Claims (13)

A memory control method includes: writing a write data having a logical address to a write data temporary storage memory; and generating the logical address of the write data corresponding to a main memory a write address comparison table of a physical address in the medium and write it to a cache data comparison table to be written into the temporary storage memory; the write data is written according to the write address comparison table And to the main memory; and if the available storage space of the cache data comparison table written to the temporary storage memory reaches a predetermined threshold, writing the cache data comparison table to the write bit in the temporary storage memory The address comparison table is written into the main memory, and a corresponding primary memory write address comparison table is recorded in a global comparison table temporary storage memory. The memory control method according to claim 1, wherein the main memory system is opposite to the gate flash memory. The memory control method according to claim 1, which is based on a page level control method. The memory control method according to claim 1, wherein the step of writing the cache data comparison table to the write address in the temporary memory includes: : writing the cache data comparison table to the write address comparison table in the temporary memory to be written into the main memory without writing to the main memory to distinguish from the general data In a specific area. A memory control method comprising: Writing a cached data comparison table to the temporary storage memory to search for a read address of a read data corresponding to a physical address of a read address in a main memory If the read address comparison table exists in the cache data comparison table and is written in the temporary storage memory, the read data having the physical address is read from the main memory and written Read the data in the temporary storage memory. The memory control method according to claim 5, further comprising: if the read address comparison table is not present in the cache data comparison table and written in the temporary storage memory, searching for a cache data comparison The table reads the temporary storage memory; if the read address comparison table exists in the cache data comparison table and reads the temporary storage memory, the read data having the physical address is from the primary memory Read out and write to the read data temporary memory. The memory control method according to claim 5, further comprising: if the read address comparison table is not present in the cache data comparison table, the temporary memory is read, and the cache data comparison table is read. In the temporary memory, searching for a global comparison table temporary storage memory; reading the read address comparison table from the primary memory to the cache data comparison by using the overall comparison table temporary storage memory The table is read into the scratch memory, and the read data having the physical address is read from the main memory and written into the read data temporary storage memory. The memory control method according to claim 5, wherein the main memory system is opposite to the gate flash memory. The memory control method according to claim 5, which is based on a page level control method. A memory control circuit includes: a write data temporary storage memory for storing a write data having a logical address; a cache data comparison table is written to the temporary storage memory for storing the write The logical address of the incoming data corresponds to a write address comparison table of a physical address in a primary memory; and a global comparison table temporary storage memory for writing in the cache data comparison table When the available storage space of the temporary storage memory reaches a predetermined threshold, storing the cached data comparison table written in the primary memory into the corresponding address of the write address comparison table in the temporary storage memory A primary memory is written to the address comparison table. The memory control circuit according to claim 10, which is based on a page level memory control circuit. A memory control circuit includes: a cache data comparison table for reading a temporary memory for storing a logical address of a read data to be read corresponding to an entity in a primary memory a read address comparison table of the address; a read data temporary storage memory for storing the read data having the physical address read from the main memory; and a global comparison table The temporary memory is used to find the read address comparison table from the main memory. The memory control circuit according to claim 12, which is based on a page level memory control circuit.