CN106169869A

CN106169869A - A kind of pseudo-pwm control circuit

Info

Publication number: CN106169869A
Application number: CN201610562393.4A
Authority: CN
Inventors: 周泽坤; 曹建文; 李天生; 石跃; 王卓; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2016-07-18
Filing date: 2016-07-18
Publication date: 2016-11-30
Anticipated expiration: 2036-07-18
Also published as: CN106169869B

Abstract

Technical field of power management of the present invention, relates to a kind of pseudo-pwm control circuit.The present invention includes error amplifier, inductive current sample circuit, the PWM comparator with offset voltage and numeral logic control circuit, inductive current sample circuit is that inductive current is converted to voltage, and the output voltage of PWM comparator and clock signal are converted to the control signal of switching tube by Digital Logic control module.Beneficial effects of the present invention is, in the case of not increasing any extra module and system complexity, it is achieved that the PWM control mode under Chong Zai and the PSM control mode under underloading, promotes system overall transformation efficiency.

Description

A kind of pseudo-pwm control circuit

Technical field

The invention belongs to technical field of power management, relate to a kind of pseudo-pwm control circuit.

Background technology

Power management chip breaker in middle power supply is energy-efficient power supply.DC-DC converter, based on switch motion, passes through the cycle The time that is switched on and off of property modulation switch pipe, it is achieved the regulation of output voltage.The modulation system of switch controlled pulse has PWM, PFM, PSM etc..PWM control mode has that loop structure is simple, conversion efficiency is high, output ripple is little under large load current Advantage, and be widely used.PFM control mode can change operating frequency according to loading condition, conversion efficiency and PWM during heavy duty Control mode is suitable, and under underloading, efficiency is bigger than PWM control mode, but under PFM control mode, output voltage ripple compares Greatly.Additionally, along with the change of load, the frequency spectrum of PFM control mode can change, and harmonic spike energy is than PWM control mode Little, but spuious Energy distribution adds the difficulty of converter EMI design, needs to expand the operating frequency model of filter circuit Enclose, not only increase the design difficulty of filter circuit, and need bigger volume to realize filter circuit.PSM control mode Output voltage ripple is bigger than PWM control mode.Frequency spectrum relative to PFM, PSM is more concentrated, and has more superior electromagnetism and holds concurrently Capacitive energy.Equally exist the side frequency effect in PFM relative to PWM, PSM modulating mode, but the advantage of PSM modulation maximum is light During load, efficiency is high.DC-DC converter uses single modulation system always to have certain defect, is widely adopted the most at present Strategy is the difference according to load, switches between various control pattern.But this method generally requires extra increasing as negative Carry multiple supplementary modules and the systematic control algorithms of complexity such as detection, mode decision, and there is the secondary stable state of multi-mode switching Problem.

Summary of the invention

To be solved by this invention, it is simply that the defect brought for above-mentioned existing single modulation system and mixed model is asked Topic, it is proposed that a kind of pseudo-pwm control circuit.

The technical scheme is that a kind of pseudo-pwm control circuit, including error amplifier, inductive current sample circuit, There is PWM comparator and the numeral logic control circuit of offset voltage；Described Digital Logic control circuit by phase inverter, first with Not gate, the second NAND gate, the 3rd NAND gate and nor gate are constituted；The positive input termination reference voltage of error amplifier, negative input Termination feedback voltage, output termination has the negative input end of the PWM comparator of offset voltage；The PWM with offset voltage compares The outfan of the positive input termination inductive current sample circuit of device, the output termination of the PWM comparator with offset voltage is anti-phase The input of device；The outfan of one input termination phase inverter of the first NAND gate, another input termination of the first NAND gate External timing signal；The outfan of one input termination phase inverter of the second NAND gate, another input of the second NAND gate Connect the outfan of the 3rd NAND gate；The outfan of one input termination the first NAND gate of the 3rd NAND gate, the 3rd NAND gate The outfan of another input termination the second NAND gate；The outfan of one input termination the second NAND gate of nor gate, or non- Another input termination external timing signal of door, the outfan of nor gate is the outfan of pseudo-pwm control circuit.

In such scheme, the effect of error amplifier be by the output voltage of DC-DC converter compared with reference voltage； Inductive current sample circuit is that inductive current is converted to voltage；PWM comparator is that inductive current sampled voltage adds imbalance electricity Pressure with the output voltage of error amplifier compared with, Digital Logic control part be in order to by the output voltage of PWM comparator and Clock signal is converted into the control signal of switching tube.

Beneficial effects of the present invention is, in the case of not increasing any extra module and system complexity, it is achieved that PWM control mode under Chong Zai and the PSM control mode under underloading, promote system overall transformation efficiency.

Accompanying drawing explanation

The pseudo-PWM control mode Organization Chart that Fig. 1 present invention proposes；

Sequential chart under the pseudo-PWM control mode heavy duty that Fig. 2 present invention proposes；

Sequential chart under the pseudo-PWM control mode underloading that Fig. 3 present invention proposes.

Detailed description of the invention

Below in conjunction with the accompanying drawings, technical scheme is described in detail:

A kind of pseudo-PWM control mode Organization Chart that the present invention proposes as it is shown in figure 1, be made up of 4 parts, error amplifier, Inductive current sample circuit, has the PWM comparator of offset voltage, and Digital Logic controls part.As identified in FIG, by mistake Difference amplifier, PWM comparator is all traditional analog circuit unit module, and inductive current sample circuit is to be changed by inductive current For voltage, the output voltage of PWM comparator and clock signal are converted to the control signal of switching tube by Digital Logic control module. This invention of labor is carried out below in conjunction with instantiation.

Digital Logic control part and the PWM comparator with offset voltage are the key of the design: inductive current is sampled Voltage CS inputs as the forward of PWM comparator, and the output EA_OUT of error amplifier inputs as the reverse of PWM comparator, The output of PWM comparator controls the input of partial inversion device INV, the output of phase inverter INV and clock letter as Digital Logic Number as two inputs of the first NAND gate NAND1, the output of phase inverter INV simultaneously and the output of the 3rd NAND gate NAND3 Connecing the input of the second NAND gate NAND2, the output of the first NAND gate NAND1 and the output of the second NAND gate NAND2 are as the 3rd The input of NAND gate NAND3, the output of the 3rd NAND gate NAND3 and clock signal are as the input of nor gate NOR, nor gate The output of NOR is as the control signal of switching tube.

Before clock falling edge arrives, the outfan EA_OUT of error amplifier adds mistake more than inductive current sampled voltage When adjusting voltage, the output signal PWM_OUT low level of PWM comparator, then Digital Logic controls the A end of part is high, and B end is Low, after NAND gate, C end is low level, and C end and clock (now for high level) are output as low level after nor gate；Work as clock When trailing edge arrives, the B end of Digital Logic control part becomes high level, and C end remains in that as low level state, C end and time Clock (now for low level) is output as high level after nor gate, and switching tube is opened.Before clock falling edge arrives, error is put When the outfan EA_OUT of big device adds offset voltage less than inductive current sampled voltage, output signal PWM_OUT of PWM comparator For high level, the A end of Digital Logic control part is low level, and B end is high level, then C end is high level, C end and clock letter PWM_Control signal is low level number after nor gate, and when clock falling edge arrives, Digital Logic controls part C end and protects Holding high level state, the output PWM_Control signal of nor gate maintains low level.So PWM comparator exports on clock edge When being high level before arrival, in this cycle, switch controlled signal PWM_Control keeps low level, and switching tube is not switched on, This cycle is skipped in switch controlled pulse.PSM modulation when thus achieving underloading.

When under the working condition in heavy duty, the feedback voltage of system is smaller, and the output voltage of error amplifier raises, The voltage of EA_OUT is greater than the offset voltage of PWM comparator so that every time before clock falling edge arrives, PWM comparator Output voltage PWM_Control is low level, and switching tube is normal switch within this cycle.During system output voltage change, EA_ OUT voltage changes (still above the offset voltage of PWM comparator) the most therewith, then switching tube pulse width changes the most therewith, in It is to achieve PWM pattern under heavy loads.When, under the working condition of underloading, the feedback voltage of system is bigger, and error is put The output voltage of big device is smaller, when clock falling edge arrives, and EA_OUT voltage is less than the offset voltage of PWM comparator, and PWM The output end voltage PWM_OUT signal of comparator is high level, then Digital Logic controls the outfan PWM_Control letter of part Keeping low level state number within this cycle, switching tube was closed within this cycle, and the output voltage until system reduces to EA_ OUT is more than the offset voltage of PWM comparator, and when clock falling edge arrives, PWM_Control signal becomes high level, switch Pipe is normally opened, and thus achieves PSM modulation when underloading.

Fig. 2 is the oscillogram of PWM pattern under heavy duty, and output voltage is relatively small, and feedback voltage is smaller, by mistake The outfan EA_OUT of difference amplifier is bigger.So before clock falling edge arrives, switching tube is not also opened, and PWM compares Device positive input voltage is less than the voltage of reverse input end, and PWM comparator output terminal PWM_OUT is low level, and clock is along arriving When coming, PWM_Control signal becomes high level, and switching tube is opened, and inductive current sampled voltage increases, and PWM comparator overturns, PWM_OUT is high level, and after Digital Logic control part, PWM_Control becomes low level.When output end voltage changes, EA_OUT changes therewith, and when the positive input of PWM comparator and reverse input end are equal, PWM comparator overturns, PWM_ Control signal pulse width changes therewith, and then adjusts output voltage.

Fig. 3 is the oscillogram of PWM pattern under underloading, and under underloading, inductive current sampled voltage is smaller, output electricity Pressure increases, and EA_OUT reduces, and when clock falling edge arrival EA_OUT is less than PWM comparator positive input voltage, PWM compares Device outfan is high level, and in this cycle, PWM_Control signal is maintained low level state, and switching tube is not switched on, output electricity Pressure drop is low, until EA_OUT increases to when clock falling edge arrives more than comparator positive input voltage.Switch management and control Pulse processed can be skipped several cycle and be achieved PSM control mode.

Claims

1. a pseudo-pwm control circuit, compares including error amplifier, inductive current sample circuit, the PWM with offset voltage Device and numeral logic control circuit；Described Digital Logic control circuit by phase inverter, the first NAND gate, the second NAND gate, the 3rd NAND gate and nor gate are constituted；The positive input termination reference voltage of error amplifier, negative input termination feedback voltage, output termination There is the negative input end of the PWM comparator of offset voltage；There is the positive input termination inductive current of the PWM comparator of offset voltage The outfan of sample circuit, has the input of the output termination phase inverter of the PWM comparator of offset voltage；First NAND gate The outfan of one input termination phase inverter, another input termination external timing signal of the first NAND gate；Second NAND gate One input termination phase inverter outfan, the second NAND gate another input termination the 3rd NAND gate outfan；The The outfan of one input termination the first NAND gate of three NAND gate, another input termination second NAND gate of the 3rd NAND gate Outfan；The outfan of one input termination the second NAND gate of nor gate, when another input termination of nor gate is outside Clock signal, the outfan of nor gate is the outfan of pseudo-pwm control circuit.