CN106159084B - The mosaic technology of resistive random access memory top electrode - Google Patents
The mosaic technology of resistive random access memory top electrode Download PDFInfo
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- CN106159084B CN106159084B CN201510151228.5A CN201510151228A CN106159084B CN 106159084 B CN106159084 B CN 106159084B CN 201510151228 A CN201510151228 A CN 201510151228A CN 106159084 B CN106159084 B CN 106159084B
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Abstract
The present invention provides a kind of manufacturing method of memory.Insulating layer is formed on the array of interlayer conductor, etching isolation layer is open with define the first interlayer conductor in corresponding array first, and wherein etch stop is in the first upper surface of the first interlayer conductor.Metal oxide layer is formed on the first upper surface.Deposit the first barrier material layer that the surface being open with metal oxide layer and first is conformal and contacts.Then etching isolation layer is open with define the second interlayer conductor in corresponding array second, and wherein etch stop is in the second upper surface of the second interlayer conductor.Deposit the second barrier material layer that is conformal with the first barrier material layer in the first opening and contacting.Use the first opening of conductive material filling.
Description
Technical field
The present invention relates to memory devices and its manufacturing method based on metal oxide.
Background technique
Resistive random access memory (Resistive Random Access Memory, RRAM) is a kind of non-volatile
The type of property memory, give the advantage that small memory cell size, scalability, ultrahigh speed operation, low-power operation,
High-durability, good retentivity, big on-off ratio and CMOS compatibility.A seed type of RRAM includes metal oxide layer,
By applying the various degrees of electric pulse of the implementation suitable for integrated circuit, metal oxide layer can produce to change two
Or more resistance between steady resistance range.
When ic manufacturing technology is scaled, compared to line pattern, it is used to form the top electrode of RRAM
Mosaic technology becomes relatively to be suitble to.RRAM storage unit may include an access device with first terminal and Second terminal, connect
It touches one first plug of first terminal and contacts one second plug of Second terminal.This access device can be transistor or two
Pole pipe.One metal oxide layer contacts the upper surface of the first plug and as the memory component in RRAM storage unit.One insulation
Layer is configured on the first plug and the second plug, and there is corresponding first plug and the first opening of the second plug to open with second
Mouthful.The first top electrode and the second top electrode, and the first top electrode and the second top can be configured in the first opening and the second opening
Electrode is respectively connected to bit line and source electrode line.
In the manufacturing method of RRAM storage unit, for example, formed before respective top electrode in the opening, oxidation the
The upper surface of one plug and the second plug is to form a metal oxide layer.When the second plug is designed to be electrically connected access device
Second terminal to source electrode line, the metal oxide layer positioned at the upper surface of the second plug will be etched.However, etching is located at second
The metal oxide layer of the upper surface of the second plug in opening may cause the damage for the second plug, cause in the second plug
Higher resistance.Furthermore the side wall of the second opening in insulating layer is potentially contaminated.For example, if the second plug includes
Copper (copper, Cu) and metal oxide layer include copper oxide (copper oxide, CuOx), etch the metal oxygen in the second opening
When changing layer, copper may be sputtered on the side wall of the second opening.
In addition, when etching the metal oxide layer in the second opening, using anti-light erosion mask to protect the gold in the first opening
Belong to oxide layer.Anti-light erosion mask is removed after etching, the process of removing may damage the metal oxide layer in the first opening.
Therefore, in order to provide a kind of cost-effective manufacturing method, it is desirable to provide a kind of storage unit and its manufacture
Method, can eliminate by etching metal oxide layer caused by be connected to source electrode line plug damage possibility and by pair
Possibility is damaged caused by the mask removing of metal oxide layer, wherein metal oxide layer is as programmable resistance element.
Summary of the invention
The present invention provides a kind of manufacturing method of memory.Present invention definition corresponds to the first interlayer conductor and (also known as inserts
Plug) the first opening, form metal oxide layer on the upper surface of the first interlayer conductor in the first opening, correspond in definition
The first barrier material layer of preceding deposition of second opening of the second interlayer conductor is in the first opening.Therefore, the method is eliminated existing
Pass through the damage possibility caused by etching the metal oxide layer in the second opening for the second interlayer conductor in technology, pass through
Etching second opening in metal oxide layer caused by in insulating layer second opening side wall possibility of pollution and
For the damage possibility of the metal oxide layer in the first opening caused by being removed by mask.
In embodiments, insulating layer is formed on the array of interlayer conductor.Etching isolation layer is to define in corresponding array
First opening of the first interlayer conductor, wherein etch stop is in the first upper surface of the first interlayer conductor.In the first opening
Metal oxide layer is formed on first upper surface of the first interlayer conductor.Between the upper surface and insulating layer of the array of interlayer conductor
Diffusion barrier layer can be formed, diffusion barrier layer contacts upper surface, to prevent the diffusion from interlayer conductor and stop being located at layer
Between conductor array upper surface first opening with second opening etching.Deposition is open with metal oxide layer and first
Surface is conformal and the first barrier material layer of contact, and metal oxide layer is located on the first interlayer conductor.Pass through subsequent fabrication steps
To be formed and then remove the etching mask being located on metal oxide layer, the first barrier material layer can protect metal oxide layer and exempt from
It is damaged in current potential, thus preferable interface between metal oxide layer and top electrode is provided.The width of first opening can be greater than the
The width of one interlayer conductor.Etching isolation layer is after depositing the first barrier material layer to define corresponding second interlayer conductor in array
Second opening, wherein etch stop is in the second upper surface of the second interlayer conductor.Deposition stops with first in the first opening
Material layer it is conformal and contact the second barrier material layer.Use the first opening of conductive material filling.First and second interlayer conductor
It is respectively connected to first and second terminal of access device.
When etching is to define the first opening, the first etching mask can be used on insulating layer, wherein the first etching is covered
Mold has the masks area of corresponding second interlayer conductor and the spacer region of corresponding first opening.Etching is to define the second opening
When, the second etching mask can be used on insulating layer, wherein the second etching mask has the masks area of corresponding first opening
And the spacer region of corresponding second opening.
It deposits conformal with the surface of the second upper surface of the second interlayer conductor in the second opening and the second opening and connects
Second barrier material layer of touching can also use the second opening of conductive material filling, and wherein metal oxide layer is not present in second
Between upper surface and the second barrier material layer.
It can be electrically connected to metal oxide layer and can be used as the first access line of bit line.Electrical property can be formed
It is connected to the second interlayer conductor and can be used as the second access line of source electrode line.
The access device array for being coupled to the array of interlayer conductor can be formed, access device array includes above-mentioned first
Access device.First access device above-mentioned may include diode or transistor.It include crystalline substance in the first access device above-mentioned
In the embodiment of body pipe, it can be electrically connected to the third access line of the gate terminal of transistor.
The feature of metal oxide layer can be there is programmable resistance.First interlayer conductor can be substantially by metal
It is formed, and metal oxide layer may include the oxide of metal.First interlayer conductor can be substantially by transition metal institute group
At, and metal oxide layer may include the oxide of transition metal.
Detailed description of the invention
Fig. 1 shows the sectional view of the storage unit according to an embodiment；
Fig. 2-8 shows the exemplary steps for manufacturing storage unit as shown in Figure 1；
Fig. 9 shows resistive random access memory (the Resistive Random Access according to an embodiment
Memory, RRAM) array circuit diagram；
Figure 10 shows the simplification design drawing according to the storage unit of embodiment shown in Fig. 9；
Figure 11 shows the circuit diagram of the RRAM array according to second embodiment；
Figure 12 shows the simplification design drawing according to the storage unit of second embodiment shown in Figure 11；
Figure 13 shows the circuit diagram of the RRAM array according to 3rd embodiment；
Figure 14 shows the simplification design drawing according to the storage unit of 3rd embodiment shown in Figure 13；
Figure 15 show according to use diode as the circuit diagram of the RRAM array of the embodiment of access device；
Figure 16 is shown according to using diode to set shown in Figure 15 as the simplification of the storage unit of the embodiment of access device
Meter figure；
17th illustrates the simplified flowchart of the embodiment of the method for manufacturing memory device.
[description of symbols]
100: storage unit
111: first terminal
112: Second terminal
120: dielectric layer
131,941M, 1141M, 1341M: the first interlayer conductor
131T: the first upper surface
132,941A, 941B, 1141A, 1141B, 1341A: the second interlayer conductor
132T: the second upper surface
140: diffusion barrier layer
150: insulating layer
161: the first openings
162: the second openings
170: metal oxide layer
180: the first barrier layers
181: the first barrier material layers
182: the second barrier material layers
185: conductive material
310: the first etching masks
610: the second etching masks
900,1100,1300,1500:RRAM array
901、902、903、904、1101、1102、1103、1301、1302、1303、1304、1305、1306、1307、
1308,1544: storage unit
901A, 1101A: the first transistor
901B, 1101B: second transistor
901M, 1101M, 1301M, 1541M, 1542M, 1543M, 1544M: memory element
911,912,913,1111,1112,1113,1311,1312,1313,1314: the first access line
921,922,923,1121,1122,1123,1321,1322,1323,1324: the second access line
931、932、933、934、935、936、1131、1132、1133、1134、1135、1136、1331、1332、1333、
1334: third access line
1301A: transistor
1511,1512,1513,1514: bit line
1531,1532,1533,1534: wordline
1544D: diode
1510: bit line decoder
1530: word-line decoder
1551,1552,1553,1554: contact
1701,1702,1703,1704,1705,1706,1707: step
W1, W2: width
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
It should be understood that being not intended to the embodiments and methods for limiting the invention to specifically disclose, other spies can be used
Sign, element, method and embodiment implement the present invention.Preferred embodiment is described to illustrate the present invention, rather than limits its model
It encloses, this range is defined by the claims.Those skilled in the art will be appreciated that the various etc. of following narration
The variation of effect.Similar element usually has similar appended drawing reference in various embodiments.
Fig. 1 shows the sectional view of the storage unit (such as 100) according to an embodiment.Interlayer conductor (such as 131,
132) patterned insulation layer (such as 150) are configured on array.Patterned insulation layer (such as 150) includes in corresponding array
First opening (such as 161) of one interlayer conductor (such as 131) and the second interlayer conductor (such as 132) in corresponding array
Second opening (such as 162).First opening extends through patterned insulation layer with the second opening, and stops at the first interlayer conductor
The second upper surface (such as 132T) of first upper surface (such as 131T) of (such as 131) and the second interlayer conductor (such as 132).
First interlayer conductor (such as 131) and the second interlayer conductor (such as 132) include conducting element.For example, layer
Between conductor can be selected from by titanium (Ti), tungsten (W), molybdenum (Mo), aluminium (Al), hafnium (Hf), tantalum (Ta), copper (Cu), platinum (Pt), iridium (Ir),
One or more elements and combinations thereof in group composed by lanthanum (La), nickel (Ni), nitrogen (N), oxygen (O) and ruthenium (Ru), at certain
It may include more than one layer in a little embodiments.In one embodiment, first and second interlayer conductor substantially can be by metal institute
Composition, and metal oxide layer may include the oxide of metal.In another embodiment, first and second interlayer conductor essence
On can be made of transition metal, and metal oxide layer may include the oxide of transition metal.
Metal oxide layer (such as 170) is configured at the first upper surface (such as 131T) of the first interlayer conductor (such as 131)
On, and metal oxide layer is not present on the second upper surface (such as 132T) of the second interlayer conductor (such as 132).Metal oxygen
The feature for changing layer can be there is programmable resistance, so that metal oxide layer is programmable at least two resistance states.It lifts
For example, metal oxide layer may include one or more tungsten-oxygen compound (WOX), such as WO3、W2O5、WO2In one or more.Metal
Oxide layer can have including WO3、W2O5And WO2Gradient map, oxygen ratio in such metal oxide layer is from the first opening (example
As 161) reduced to the first interlayer conductor (such as 131).
It is shown in embodiment, the metal oxide layer 170 that the upper surface by aoxidizing the first interlayer conductor 131 is formed can be
Simple layer, therefore metal oxide layer 170 is self-aligned to the first interlayer conductor 131.Because during forming metal oxide layer
Volume expansion, metal oxide layer can project to the first opening from the first upper surface of the first interlayer conductor.In the implementation of substitution
In example, metal oxide layer 170 may include other metal oxides, for example be selected from nickel oxide, aluminium oxide, magnesia, oxidation
Metal oxide in cobalt, titanium oxide, titanium oxide-nickel, zirconium oxide and copper oxide group.
Can be configured between the upper surface and patterned insulation layer of the array of interlayer conductor diffusion barrier layer (such as
140).Diffusion barrier layer (such as 140) can prevent the diffusion from interlayer conductor.For example, interlayer conductor may include
The material of high diffusibility such as copper (copper, Cu), this may cause reliability issues.Diffusion barrier layer (such as 140) can wrap
Include silicon nitride (silicon nitride, SiN).In the upper surface of the array of interlayer conductor, diffusion barrier layer (such as 140) is also
It can stop the etching of the first opening with the second opening.Thicker diffusion barrier layer can increase the capacitor of RRAM storage unit, and
Relatively thin diffusion barrier layer may be not enough to prevent diffusion or the possibly upper table that can not stop interlayer conductor from interlayer conductor
The etching of first and second opening in face.In one embodiment, in the range of 10 nanometers (nanometer, nm) to 100nm,
Diffusion barrier layer (such as 140) can have the thickness of about 30nm, to prevent the diffusion from interlayer conductor, while not cause
Excessive capacitor.
On the first interlayer conductor and on the surface of the first opening, configures conformal with metal oxide layer (such as 170) and connect
The first barrier layer (such as 180) of touching, wherein the surface of the first opening includes the side and bottom surface of the first opening.First barrier layer
(such as 180) may include the first barrier material layer (such as 181) and the second resistance that is conformal and contacting the first barrier material layer
Obstructing material layer (such as 182).In one embodiment, in the range of 1nm to 50nm, first barrier material layer on the first barrier layer
(such as 181) and the second barrier material layer (such as 182) can have the thickness of about 10nm.
Second barrier layer may include the second barrier material layer (such as 182), configure the second barrier layer in the second opening
It is conformal with the second upper surface (such as 132T) of the second interlayer conductor (such as 132) and contact, and configure the second barrier layer and the
The side and bottom surface of two openings are conformal and contact.Thickness of the thickness on the second barrier layer less than the first barrier layer 180.Implement one
In example, the second barrier layer including the second barrier material layer (such as 182) can have about in the range of 1nm to 50nm
The thickness of 10nm.
Use the first opening of conductive material (such as 185) filling, in the first opening conductive material (such as 185) contact the
One barrier layer (such as 180).Using conductive material (such as 185) filling second opening, in the second opening conductive material (such as
185) the second barrier layer is contacted.First barrier material layer (such as 181) and the second barrier material layer (such as 182) may include not
With the one layer or more of material, different materials include selected from by titanium (Ti), titanium nitride (TiN), tungsten (W), aluminium copper (AlCu), nitrogen
Change tantalum (TaN), copper (Cu), hafnium (Hf), tantalum (Ta), golden (Au), platinum (Pt), silver-colored (Ag) and other are compatible with CMOS and will not make
One or more elements in group composed by metal at the variation electrical resistance property of metal oxide layer.
First interlayer conductor (such as 131) and the second interlayer conductor (such as 132) are respectively connected to the first of access device
Terminal (such as 111) and Second terminal (such as 112).The first terminal of access device is configured at the phase of dielectric layer with Second terminal
For the side of the first opening and the second opening.
The array of interlayer conductor extends through dielectric layer (such as 120).Dielectric layer (such as 120) may include oxide material
Material such as plasma-based auxiliary (plasma enhanced, PE) oxide, plasma-based assist tetraethoxysilane (plasma enhanced
Tetraethyl orthosilicate, PETEOS) oxide, low pressure tetraethoxysilane (low pressure
Tetraethyl orthosilicate, LPTEOS) oxide, high-density electric slurry (high density plasma, HDP) oxygen
Compound, bpsg film (borophosphosilicate glass film, BPSG), phosphosilicate glass film
(phosphosilicate glass film, PSG), fluorosilicate glass film (fluorosilicate glass film,
FSG), low-k (low k) material etc..
For example, the first access line can be electrically connected by the conductive material being filled in the first opening (not show
Out) to metal oxide layer, and the first access line can be used as the bit line of storage unit.For example, by being filled in second
Conductive material in opening can be electrically connected the second access line (not shown) to the second interlayer conductor, and the second access line
It can be used as the source electrode line of storage unit.First access line and the second access line may include one or more elements, these
Element includes titanium (Ti), tungsten (W), aluminium (Al), copper (Cu), platinum (Pt), tantalum nitride (TaN), hafnium (Hf), tantalum (Ta) and nickel
(Ni).First access line may include the material identical or different with the second access line.Be filled in the first opening (such as
161) it can be formed in metal layer 1 (ML1) with the conductive material in the second opening (such as 162), and first and second access line
Road can be formed in 2,3,4 or n of metal layer (ML2, ML3, ML4 or ... MLn).Furthermore first and second access line can be with shape
At in different metal layers.For example, the first access line can be formed in metal layer 3 (ML3), and the second access line can
To be formed in metal layer 4 (ML4).
Access device may include diode or transistor.In the embodiment that access device includes transistor, third
Access line (not shown) can be electrically connected to the gate terminal of transistor, and third access line can be used as storage unit
Wordline.
In operation, by metal oxide layer 170 and the first barrier layer 180, the first access line and are applied to
Voltage between one interlayer conductor 131 will cause electric current flowing between the first access line and the first interlayer conductor 131.This electricity
Stream can promote the programmable variation in the resistance of metal oxide layer 170, this resistance indicates the number being stored in storage unit 100
According to value.In some embodiments, the metal oxide layer 170 of storage unit 100 can store the data of two or more.
Fig. 2-8 shows the exemplary steps for manufacturing storage unit as shown in Figure 1.Fig. 2, which is shown in section to be formed to extend, to be led to
Cross the interlayer conductor of dielectric layer array and formed insulating layer (such as 150) on the array of interlayer conductor as a result, wherein
Interlayer conductor includes the first interlayer conductor (such as 131) and the second interlayer conductor (such as 132).In embodiment, diffusion barrier
Layer (such as 140) can be formed between insulating layer and dielectric layer, and contact interlayer conductor array upper surface (such as
131T, 132T) to stop being located at the etching of the first opening and the second opening of the array upper surface of interlayer conductor and protect interlayer
The upper surface of conductor is from oxidation.Dielectric layer may include silica.Insulating layer will be patterned to form storage unit
Top electrode.First and second interlayer conductor be connected to access device first terminal and Second terminal (example as shown in figure 1 111 with
112), wherein first terminal and Second terminal are located at the side relative to insulating layer of dielectric layer.
Fig. 3 etching isolation layer is shown with define in array the first opening of corresponding first interlayer conductor (such as 131) (such as
161), wherein etch stop in the first upper surface (such as 131T) of the first interlayer conductor.In the implementation for forming diffusion barrier layer
In example, the etching to define the first opening is also etched through diffusion barrier layer and the first interlayer stopped in the first opening is led
The upper surface of body.The opening of the second interlayer conductor in this manufacturing step, the array of corresponding interlayer conductor is not present in absolutely
In edge layer.For example, when etching is to define the first opening, the first etching mask (such as 310) such as anti-light erosion can be used and cover
Mould is open on insulating layer wherein the first etching mask has the masks area of corresponding second interlayer conductor and corresponds to first
The spacer region of (such as 161).
Fig. 4, which is shown, forms metal oxidation on the first upper surface (such as 131T) of the first interlayer conductor in the first opening
Layer.Various deposition and oxidation technology can be used to form metal oxide layer, such as rapid thermal oxidation (Rapid Thermal
Oxidation, RTO), photooxidation (photo-oxidation), direct electric slurry oxide, blow formula plasma-based (down-stream
Oxidation) oxidation, sputter and reactive sputter.For example, using RTO with tungsten oxide (tungsten, W) or copper
(copper, Cu), temperature can be from 200 DEG C to 1100 DEG C in oxygen or the environment of oxygen/nitrogen, and the processing time can be from 5
Second to 500 seconds, typically 30 seconds to 60 seconds.In the embodiment that the first interlayer conductor includes tungsten (tungsten, W), plasma-based
Oxidation can cause the W with gradientXOY, have as the tungsten-oxygen compound changed with exposure with the surface distance aoxidized is dense
Degree distribution.For example, metal oxide (such as 170) can have including WO3、W2O5、WO2Gradient map, such metal oxygen
Oxygen ratio in compound layer is reduced from the first opening (such as 161) to the first interlayer conductor (such as 131).Because forming metal oxygen
Change the volume expansion during layer, metal oxide layer can project to first from the first upper surface of the first interlayer conductor and open
Mouthful.
In embodiment using RTO oxidation technology, metal oxide layer can have about in the range of 1nm to 300nm
The thickness of 50nm.In another embodiment using electric slurry oxide technology, metal oxide layer can be in the range of 1nm to 50nm
Thickness with about 5nm.
Fig. 5 shows deposition the first barrier material layer (such as 181) and is open in (such as 161) as a result, first hinders first
Obstructing material layer is conformal with metal oxide layer and contacts, and the side and bottom surface of the first barrier material layer and the first opening are conformal simultaneously
Contact, wherein metal oxide layer is located on the first upper surface of the first interlayer conductor.In one embodiment, the first barrier material layer
(such as 181) can have the thickness of about 10nm in the range of 1nm to 50nm.First barrier material layer (such as 181) can be with
One layer or more including different materials, different materials include selected from by titanium, titanium nitride, tungsten, aluminium copper, tantalum nitride, copper, hafnium,
Tantalum, gold, platinum, silver and other it is compatible with CMOS and not will cause metal oxide layer variation electrical resistance property metal composed by
One or more elements in group.It is covered by subsequent fabrication steps with being formed and then removing the etching being located on metal oxide layer
Mould, the first barrier material layer can protect metal oxide layer and damage from current potential, thus provide metal oxide layer and top electrode it
Between preferable interface.
The minimum widith of first opening is based on manufacturing technology.The width (such as W1) of first opening (such as 161) can be big
In the width (such as W2) of the first interlayer conductor (such as 131).For example, if the first interlayer conductor include tungsten (tungsten,
W) and the width with about 100nm, then the first opening can have width greater than 120nm.
Fig. 6 shows the second interlayer conductor (example in array of the etching isolation layer (such as 150) to define corresponding interlayer conductor
Such as the second opening (such as 162) 132), wherein etch stop is in the second upper surface (such as 132T) of the second interlayer conductor.It is heavy
It carries out after the first as shown in Figure 5 barrier material layer of product to define this etching step of the second opening, and is etched through the
One barrier material layer (such as 181).It is formed in the embodiment of diffusion barrier layer, the etching to define the second opening also etches logical
Diffusion barrier layer is crossed, and stops at the upper surface of the second interlayer conductor in the second opening.In one embodiment, the second opening
The width of (such as 162) can match the width of the first opening (such as 161).
It is formed in the existing method of metal oxide layer, need to such as be splashed by technique on the second upper surface of the second interlayer conductor
Plating removes metal oxide layer, thus may cause the pollution of the side wall of the second opening in insulating layer.For example, if the second interlayer
Conductor includes copper (copper, Cu) and metal oxide layer includes copper oxide (CuOx), when removing metal oxide layer, copper may be splashed
It is plating on the side wall of the second opening.
In an embodiment of the present invention, because metal oxide layer is not present in the of the second interlayer conductor (such as 132)
On two upper surfaces (such as 132T) and etch stop is in the second upper surface (such as 132T) of the second interlayer conductor (such as 132),
The pollution of the side wall of the second opening can be reduced to minimum in the insulating layer that may occur along with existing method.
In manufacturing step to define the second opening, the second etching mask (such as 610) such as anti-light erosion can be used and cover
Mould is on insulating layer (such as 150) and the first barrier material layer (such as 181), wherein the second etching mask has corresponding first to open
The spacer region of the masks area of mouth (such as 161) and corresponding second opening (such as 162).Therefore, in this manufacturing step, lead to
Cross in the first barrier material layer and the second etching mask masks area protection first opening in metal oxide layer (such as
170)。
Fig. 7 is shown using after the second opening (such as 162) of the second etching mask definition, removes as shown in FIG. 6 second
The result of etching mask (such as 610).In stripping process, by the first opening of the first barrier material layer (such as 181) protection
Metal oxide layer (such as 170).
In the preliminary process for depositing the second barrier material layer, by using the plasma-based for having energy generated from gaseous matter,
Plasma-based cleaning can be used with from the second upper surface (such as 132T) removal of impurity of the second interlayer conductor, pollutant and natural
Oxide.For example, gaseous matter may include argon gas, and plasma-based cleaning can etch the depth from about 1nm to 20nm.
Plasma-based cleaning during, by the first barrier material layer (such as 181) protection first opening in metal oxide layer (such as
170)。
Fig. 8 is illustrated in the result that the second barrier material layer (such as 182) are deposited in the first opening and the second opening.First opens
The second barrier material layer in mouthful is conformal with the first barrier material layer (such as 181) and contacts, and second in the second opening stops
Material layer is conformal with the second upper surface (such as 132T) of the second interlayer conductor and contacts, and the second barrier material layer is opened with second
The side and bottom surface of mouth are conformal and contact.In one embodiment, the second barrier material layer (such as 182) is in 1nm to 50nm's
In range, the thickness of about 10nm can have.First barrier material layer (such as 181) and the second barrier material layer (such as 182)
May include the one layer or more of different materials, different materials include selected from by titanium, titanium nitride, tungsten, aluminium copper, tantalum nitride, copper,
Hafnium, tantalum, gold, platinum, silver and other it is compatible with CMOS and not will cause metal oxide layer variation electrical resistance property metal institute group
At group in one or more elements.
Then conductive material (such as 185) can be filled in the first opening and the second opening.For example, by filling out
The conductive material filled in the first opening can be electrically connected to the first access line (not shown) of metal oxide layer, and
First access line can be used as the bit line of storage unit.It for example, can by the conductive material being filled in the second opening
To be electrically connected to the second access line (not shown) of the second interlayer conductor, and the second access line can be used as storage
The source electrode line of unit.Being filled in the first opening (such as 161) and the conductive material in the second opening (such as 162) can be formed in
Metal layer 1 (ML1), and first and second access line can be formed in 2,3,4 or n of metal layer (ML2, ML3, ML4 or
...MLn).Furthermore first and second access line can be formed in different metal layers.For example, the first access line can
To be formed in metal layer 3 (ML3), and the second access line can be formed in metal layer 4 (ML4).
Fig. 9 shows resistive random access memory (the Resistive Random Access according to an embodiment
Memory, RRAM) array circuit diagram.RRAM array 900 includes the column and column of storage unit (such as 901,902,903),
In each storage unit include the first transistor (such as 901A), second transistor (such as 901B) and the storage for being connected to bit line
Element (such as 901M).First and second transistor can be N-type metal-oxide-semiconductor (MOS) (N-type metal oxide
Semiconductor, NMOS) transistor.Memory element may include metal oxide layer 170 as shown in Figure 8.Storage unit can
To include the first barrier material layer 181 and the second barrier material layer 182 on metal oxide layer 170 as shown in Figure 1.Storage unit
In the first terminal of first and second transistor be connected to one end of memory element in storage unit.Three storages shown are single
Member 901,902 and 903 indicates a block of cells of memory array, and memory array may include thousands of or millions of storage
Unit.
Multiple first access lines (such as 911,912 and 913) extend along a first direction and (do not show with bit line decoder
Out) and the memory element electrical communication of storage unit.It is led by the first interlayer being configured under memory element (such as 901M)
One end of body (such as 941M), the memory element in storage unit is connected to one first access line in multiple first access lines
Road, and the other end is connected to the first terminal of first and second transistor in storage unit.First interlayer conductor (such as 131)
Sectional view be illustrated in Fig. 8.Multiple first access lines can be used as bit line.
Multiple second access lines (such as 921,922 and 923) extend along a first direction, and terminate at source electrode line terminal
Circuit (not shown).By the second interlayer conductor (such as 941A and 941B), the second access line (such as 921) and storage unit
In first and second transistor (such as 901A and 901B) Second terminal electrical communication.Second interlayer conductor (such as 132)
Sectional view be illustrated in Fig. 8.Multiple second access lines can be used as source electrode line.
Multiple third access lines (such as 931 to 936) extend along the second direction for being orthogonal to first direction.Third is deposited
Line taking road and word-line decoder (not shown) electrical communication, and can be used as wordline.First and second crystal in storage unit
The gate terminal of pipe (such as 901A and 901B) is each attached to third access line.Bit line decoder and word-line decoder can be with
Including Complementary MOS (Complementary Metal Oxide Semiconductor, CMOS) circuit.
Figure 10 shows the simplification design drawing according to the storage unit of embodiment illustrated in fig. 9.With with attached drawing mark similar in Fig. 9
Note indicates similar element in Figure 10.The layout of storage unit can repeat in vertical and horizontal direction.To put it more simply, not showing
Insulating materials out, for example, the insulating materials between first, second and third access line.
This design drawing shows the first access line 911 and 912 and is used as bit line (Bit Lines, BL), the second access line
921 and 922 are used as source electrode line (Source Lines, SL), and third access line 931,932 and 933 is used as wordline (Word
Lines, WL).In one embodiment, the first access line and the second access line can be configured in metal layer 1.The first,
Second is connected to storage unit (such as 901 and 904) with third access line, as depicted in figure 9.Storage unit includes storage member
Part (such as 901M), memory element may include metal oxide layer 170 as shown in Figure 8.Storage unit may include such as Fig. 1 institute
Show the first barrier material layer 181 and the second barrier material layer 182 on metal oxide layer.
Figure 11 shows resistive random access memory (the Resistive Random Access according to second embodiment
Memory, RRAM) array circuit diagram.The column of RRAM array 1100 including storage unit (such as 1101,1102 and 1103) and
Column, wherein each storage unit includes the first transistor (such as 1101A), second transistor (such as 1101B) and memory element
(such as 1101M).First and second transistor can be N-type metal-oxide-semiconductor (MOS) (N-type metal oxide
Semiconductor, NMOS) transistor.Storage unit may include the first barrier material layer on memory element as shown in Figure 1
181 and second barrier material layer 182.Memory element may include metal oxide layer 170 as shown in Figure 8.In storage unit
The first terminal of first and second transistor is connected to one end of memory element in storage unit, and first and in storage unit
The Second terminal of two-transistor is connected to source electrode line (such as 1121).Three storage units 1101,1102 shown and 1103 tables
Show that a block of cells of memory array, memory array may include thousands of or millions of storage units.
Multiple first access lines (such as 1111,1112 and 1113) extend along a first direction, and and bit line decoder
(not shown) electrical communication.Multiple first access lines can be used as bit line.Multiple second access lines (such as 1121,1122
With 1123) extend along the second direction for being orthogonal to first direction, and terminate at source line termination circuit (not shown).Multiple
Two access lines can be used as source electrode line.
Storage unit includes the first interlayer conductor (such as 1141M) for being configured under memory element (such as 1101M), and first
Interlayer conductor (such as 1141M) connect memory element (such as 1101M) to first and second transistor (such as 1101A with
First terminal 1101B), and the second interlayer conductor (such as 1141A and 1141B) connects the second end of first and second transistor
Son is to source electrode line (such as 1121).The section of first interlayer conductor (such as 131) and the second interlayer conductor (such as 132) illustrates
In Fig. 8.
Multiple third access lines (such as 1131 to 1136) extend along a first direction.Third access line is translated with wordline
Code device (not shown) electrical communication, and can be used as wordline.In storage unit first and second transistor (such as 1101A with
Gate terminal 1101B) is each attached to third access line.Bit line decoder and word-line decoder may include complementary gold
Oxide-semiconductor (Complementary Metal Oxide Semiconductor, CMOS) circuit.
Figure 12 shows the simplification design drawing according to the storage unit of second embodiment shown in Figure 11.With similar with Figure 11
Appended drawing reference indicates similar element in Figure 12.The layout of storage unit can repeat in vertical and horizontal direction.To put it more simply,
Insulating materials is not showed that, for example, the insulating materials between first, second and third access line.
This design drawing shows the first access line (such as 1111) as bit line (Bit Lines, BL), the second access line
(such as 1121,1122 and 1123) be used as source electrode line (Source Lines, SL), third access line (such as 1131,1132 with
1133) it is used as wordline (Word Lines, WL).In one embodiment, the second access line can be configured in metal layer 1,
And the first access line can be configured in the metal layer 2 on metal layer 1.First, second is connected to storage with third access line
Unit (such as 1101,1102 and 1103), as depicted in figure 11.Storage unit includes memory element (such as 1101M), storage member
Part may include metal oxide layer 170 as shown in Figure 8.Storage unit may include on metal oxide layer as shown in Figure 1
One barrier material layer 181 and the second barrier material layer 182.
Figure 13 shows resistive random access memory (the Resistive Random Access according to 3rd embodiment
Memory, RRAM) array circuit diagram.RRAM array 1300 include storage unit (such as 1301,1302,1303,1304,
1305,1306,1307 and column and column 1308), wherein each storage unit includes a transistor (such as 1301A) and storage member
Part (such as 1301M).Transistor can be N-type metal-oxide-semiconductor (MOS) (N-type metal oxide semiconductor,
NMOS) transistor.Memory element may include metal oxide layer 170 as shown in Figure 8.Storage unit may include such as Fig. 1 institute
Show the first barrier material layer 181 and the second barrier material layer 182 on metal oxide layer 170.Transistor in storage unit
First terminal is connected to one end of memory element in storage unit.The storage unit shown indicates a cell of memory array
Block, memory array may include thousands of or millions of storage units.
Multiple first access lines (such as 1311,1312,1313 and 1314) extend along a first direction and translate with bit line
Code device (not shown) electrical communication, multiple first access lines are connected to the second end of memory element, and second end is relative to connection
The end of the first terminal of transistor into storage unit.Multiple first access lines can be used as bit line.Storage unit can be with
Including the first interlayer conductor (such as 1341M) being configured under memory element (such as 1301M), the first interlayer conductor (such as
1341M) connect the first terminal of memory element to transistor (such as 1301A).The sectional view of first interlayer conductor (such as 131)
It is illustrated in Fig. 8.
Multiple second access lines (such as 1321,1322,1323 and 1324) are along the second party for being orthogonal to first direction
To extension, and terminate at source line termination circuit (not shown).Multiple second access lines can be used as source electrode line.Storage unit
It may include connecting the Second terminal of transistor to the second interlayer conductor (such as 1341A) of source electrode line (such as 1321).Second
The sectional view of interlayer conductor (such as 132) is illustrated in Fig. 8.
Multiple third access lines (such as 1331 to 1334) extend along a first direction.Third access line is translated with wordline
Code device (not shown) electrical communication, and can be used as wordline.The gate terminal of transistor (such as 1301A) in storage unit is each
From being connected to third access line.Bit line decoder and word-line decoder may include Complementary MOS
(Complementary Metal Oxide Semiconductor, CMOS) circuit.
Figure 14 shows the simplification design drawing according to the storage unit of 3rd embodiment shown in Figure 13.With similar with Figure 13
Appended drawing reference indicates similar element in Figure 14.The layout of storage unit can repeat in vertical and horizontal direction.To put it more simply,
Insulating materials is not showed that, for example, the insulating materials between first, second and third access line.
This design drawing shows the first access line 1311 and 1312 and is used as bit line (Bit Lines, BL), the second access line
1321,1322 and 1323 it is used as source electrode line (Source Lines, SL), third access line 1331 and 1132 is used as wordline
(Word Lines, WL).In one embodiment, the second access line can be configured in metal layer 1, and can configure first
Access line is in the metal layer 2 on metal layer 1.First, second is connected to storage unit (such as 1301 with third access line
To 1303 and 1305 to 1306), as illustrated in fig. 13.Storage unit includes memory element (such as 1301M), and memory element can be with
Including metal oxide layer 170 as shown in Figure 8.Storage unit may include the first blocking on metal oxide layer as shown in Figure 1
Material layer 181 and the second barrier material layer 182.
Figure 15 show according to use diode as the circuit diagram of the RRAM array of the embodiment of access device.Memory array
The matrixes of column 1500 including storage unit, a plurality of wordline (such as 1531,1532,1533 and 1534) and multiple bit lines (such as
1511,1512,1513 and 1514).Each storage unit (such as 1544) in exemplary memory array 1500 is in corresponding wordline
It sequentially include access diode (such as 1544D) and memory element between (such as 1534) and corresponding bit line (such as 1511)
(such as 1544M).Each memory element is electrically coupled to corresponding access diode.
Storage unit in memory array 1500 may include the first barrier material layer on memory element as shown in Figure 1
181 and second barrier material layer 182.Memory element in storage unit includes the metal oxygen in storage unit as shown in Figure 8
Change layer 170.
Multiple bit lines including bit line 1511,1512,1513 and 1514 extend in parallel along a first direction.Bit line and bit line
1510 electrical communication of decoder.Memory element can connect between the anode or cathode and bit line of diode.For example, it deposits
Storage element 1544M is connected between the cathode of diode 1544D and bit line 1511.Including wordline 1531,1532,1533 and 1534
A plurality of wordline extended in parallel along second direction.Wordline 1531,1532,1533 and 1534 and word-line decoder 1530 are electrically logical
Letter.The anode or cathode of diode can be connected to wordline.For example, the anode of diode 1544D is connected to wordline 1534.Position
Line decoder and word-line decoder may include Complementary MOS (Complementary Metal Oxide
Semiconductor, CMOS) circuit.It should be noted that 16 storage units in Figure 15 are to show for convenience of discussion and so,
However actually memory array may include thousands of or millions of this kind of storage units.
Figure 16 is shown according to using diode to set shown in Figure 15 as the simplification of the storage unit of the embodiment of access device
Meter figure.To indicate similar element in Figure 16 with appended drawing reference similar in Figure 15.The layout of storage unit can vertically with
Horizontal direction repeats.To put it more simply, not showing that insulating materials, for example, be located at first, second with third access line it
Between insulating materials.
This design drawing shows the first access line 1511,1512,1513 and 1514 as bit line (Bit Lines, BL), the
Two access lines 1531,1532,1533 and 1534 are used as wordline (Word Lines, WL).Second access line in storage unit
It may include the active area for diode (such as 1544D), and in order to which wordline picks up (pickup), the second access circuit can
To be connected to contact (such as 1551,1552,1553 and 1554).It in one embodiment, can be with configuration bit in metal layer 1
Line, the bit line in wordline may include polysilicon.First and second access line is connected to storage unit (such as 1544),
As depicted in figure 15.Storage unit includes memory element (such as 1541M, 1542M, 1543M and 1544M), and memory element can be with
Including metal oxide layer 170 as shown in Figure 8.Storage unit may include the first blocking material on memory element as shown in Figure 1
The bed of material 181 and the second barrier material layer 182.
17th illustrates the simplified flowchart of the embodiment of the method for manufacturing memory device.In step 1701, in layer
Between conductor array on form insulating layer.Diffusion resistance can be formed between insulating layer on the upper surface of the array of interlayer conductor
Barrier, diffusion barrier layer contact upper surface.In step 1702, etching isolation layer is to define the first interlayer conductor in corresponding array
First opening, wherein etch stop is in the first upper surface of the first interlayer conductor.When etching is to define the first opening, can make
With the first etching mask (such as 310) on insulating layer, wherein the first etching mask has the mask of corresponding second interlayer conductor
The spacer region of region and corresponding first opening (such as 161).
In step 1703, metal oxide layer is formed on the first upper surface of the first interlayer conductor in the first opening.Gold
The feature for belonging to oxide layer can be there is programmable resistance.In step 1704, deposition is opened with metal oxide layer and first
Mouthful surface is conformal and the first barrier material layer of contact, metal oxide layer is located on the first interlayer conductor.Pass through subsequent manufacture
For step to be formed and then remove the etching mask being located on metal oxide layer, the first barrier material layer can protect metal oxidation
Layer is damaged from current potential, thus provides preferable interface between metal oxide layer and top electrode.
In step 1705, etching isolation layer is led after depositing the first barrier material layer with defining corresponding second interlayer in array
Second opening of body, wherein etch stop is in the second upper surface of the second interlayer conductor.It, can when etching is to define the second opening
To use the second etching mask on insulating layer, wherein the second etching mask has the masks area of corresponding first opening and right
Answer the spacer region of the second opening.In step 1706, deposition with first be open in the first barrier material layer it is conformal and contact the
Two barrier material layers.For example, can also be deposited in same steps with second opening in the second interlayer conductor second on
Surface and second opening surface it is conformal and contact the second barrier material layer.
In step 1707, the first opening of conductive material filling is used.For example, conduction can also be used in same steps
The second opening of material filling, wherein metal oxide layer is not present between the second upper surface and the second barrier material layer.First opens
The width of mouth can be greater than the width of the first interlayer conductor.
First and second interlayer conductor can be respectively connected to first and second terminal of access device.Access device can be with
Including diode or transistor.The access device array for being coupled to the array of interlayer conductor can be formed, interlayer conductor includes the
One and the second interlayer conductor.
It will be understood that memory array is not limited to array structure shown in Figure 12, it can also be along with including above-mentioned
The storage unit of top electrode layer uses additional array structure.In addition, in some embodiments, it, can other than MOS transistor
Use bipolar transistor or diode as access device.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in protection of the invention
Within the scope of.
Claims (22)
1. a kind of method for manufacturing memory, comprising:
An insulating layer is formed on one first array of multiple interlayer conductors；
The insulating layer is etched to define one first opening, which corresponds to one first interlayer conductor in first array,
Etch stop is in one first upper surface of the first interlayer conductor；
A metal oxide layer is formed on first upper surface of the first interlayer conductor in first opening；
One first barrier material layer is deposited, first barrier material layer and the metal oxide layer on the first interlayer conductor are conformal
And it contacts, and first barrier material layer and multiple surfaces of first opening are conformal and contact, wherein first width being open
Degree is greater than the width of the first interlayer conductor；
The insulating layer is etched after preceding deposition first barrier material layer to define one second opening, which corresponds to
One second interlayer conductor in first array, etch stop is in one second upper surface of the second interlayer conductor；
One second barrier material layer is deposited, second barrier material layer and first barrier material layer in first opening are conformal
And it contacts；And
First opening is filled using a conductive material；
Wherein the first interlayer conductor and the second interlayer conductor be respectively connected to a first terminal of one first access device with
One Second terminal.
2. the method as described in claim 1, which is characterized in that further include:
A diffusion barrier layer is formed between the multiple upper surfaces and the insulating layer of first array of the interlayer conductor, the expansion
It dissipates barrier layer and contacts the upper surface.
3. the method as described in claim 1, which is characterized in that the step of aforementioned etching is to define first opening, comprising:
Using one first etching mask on the insulating layer, which has a masked area of corresponding second opening
One spacer region of domain and corresponding first opening.
4. the method as described in claim 1, which is characterized in that the step of aforementioned etching is to define second opening, comprising:
Using one second etching mask on the insulating layer, which has a masked area of corresponding first opening
One spacer region of domain and corresponding second opening.
5. the method as described in claim 1, which is characterized in that the step of preceding deposition second barrier material layer, comprising:
Deposit second barrier material layer, second barrier material layer and the second interlayer conductor in second opening this
Two upper surfaces are conformal and contact, and second barrier material layer is conformal with multiple surfaces of second opening and contacts；And
Second opening is filled using the conductive material.
6. the method as described in claim 1 characterized by comprising
One first access line is formed, which is electrically connected to the metal oxide layer；And
One second access line is formed, which is electrically connected to the second interlayer conductor.
7. the method as described in claim 1 characterized by comprising
A second array of multiple access devices is formed, which is coupled to first array of the interlayer conductor, and
The second array of the access device includes first access device.
8. the method as described in claim 1, which is characterized in that first access device includes a diode.
9. the method as described in claim 1, which is characterized in that first access device includes a transistor, comprising:
A third access line is formed, which is electrically connected to a gate terminal of the transistor.
10. the method as described in claim 1, which is characterized in that the metal oxide layer is characterized by a programmable electricity
Resistance.
11. the method as described in claim 1, which is characterized in that the first interlayer conductor is substantially made of a metal, and
The metal oxide layer includes the monoxide of the metal.
12. the method as described in claim 1, which is characterized in that the first interlayer conductor is substantially by a transition metal institute group
At, and the metal oxide layer includes the monoxide of the transition metal.
13. a kind of memory, comprising:
One patterned insulation layer, on one first array of multiple interlayer conductors, which opens including one first
Mouthful with one second opening, the first one first interlayer conductor being open in corresponding first array, second opening it is corresponding this
One second interlayer conductor in an array；
One metal oxide layer, on one first upper surface of the first interlayer conductor；
One first barrier layer, it is conformal with the metal oxide layer on the first interlayer conductor and contact, and first barrier layer with
Multiple surfaces of first opening are conformal and contact, and wherein the width of first opening is greater than the width of the first interlayer conductor；
One second barrier layer is located in second opening, and wherein the thickness on second barrier layer is less than the thickness on first barrier layer
Degree；And
One conductive material is filled in first opening；
Wherein the first interlayer conductor and the second interlayer conductor be respectively connected to a first terminal of one first access device with
One Second terminal.
14. memory as claimed in claim 13, which is characterized in that further include:
One diffusion barrier layer, positioned at the interlayer conductor first array multiple upper surfaces and the patterned insulation layer it
Between, and the diffusion barrier layer contacts the upper surface.
15. memory as claimed in claim 13, which is characterized in that further include:
Second barrier layer, it is conformal and contact with one second upper surface of the second interlayer conductor in second opening, and should
Second barrier layer is conformal with multiple surfaces of second opening and contacts；And
The conductive material fills second opening.
16. memory as claimed in claim 13, which is characterized in that further include:
One first access line, is electrically connected to the metal oxide layer；And
One second access line is electrically connected to the second interlayer conductor.
17. memory as claimed in claim 13, which is characterized in that further include:
One second array of multiple access devices, is coupled to first array of the interlayer conductor, and the access device
The second array includes first access device.
18. memory as claimed in claim 13, which is characterized in that first access device includes a diode.
19. memory as claimed in claim 13, which is characterized in that first access device includes a transistor, the storage
Device includes:
One third access line is electrically connected to a gate terminal of the transistor.
20. memory as claimed in claim 13, which is characterized in that the metal oxide layer is characterized by programmable one
Resistance.
21. memory as claimed in claim 13, which is characterized in that the first interlayer conductor is substantially by a metal institute group
At, and the metal oxide layer includes the monoxide of the metal.
22. memory as claimed in claim 13, which is characterized in that the first interlayer conductor is substantially by a transition metal institute
Composition, and the metal oxide layer includes the monoxide of the transition metal.
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