CN106159084A - The mosaic technology of resistive random access memory top electrode - Google Patents
The mosaic technology of resistive random access memory top electrode Download PDFInfo
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- CN106159084A CN106159084A CN201510151228.5A CN201510151228A CN106159084A CN 106159084 A CN106159084 A CN 106159084A CN 201510151228 A CN201510151228 A CN 201510151228A CN 106159084 A CN106159084 A CN 106159084A
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Abstract
The present invention provides the manufacture method of a kind of memorizer.Forming insulating barrier on the array of interlayer conductor, etching isolation layer is to define the first opening of the first interlayer conductor in corresponding array, and wherein etch stop is in the first upper surface of the first interlayer conductor.First upper surface is formed metal oxide layer.Deposit the first barrier material layer that is conformal with the surface of metal oxide layer and the first opening and that contact.Then etching isolation layer is to define the second opening of the second interlayer conductor in corresponding array, and wherein etch stop is in the second upper surface of the second interlayer conductor.Deposit the second barrier material layer that is conformal with the first barrier material layer in the first opening and that contact.Conductive material is used to fill the first opening.
Description
Technical field
The present invention relates to storage arrangement based on metal-oxide and manufacture method thereof.
Background technology
Resistive random access memory (Resistive Random Access Memory, RRAM) is
The type of a kind of non-volatility memorizer, it is provided that following advantages: little memory cell size, scalable
Property, ultrahigh speed operation, low-power operation, high-durability, good retentivity, big on-off ratio and
CMOS is compatible.One type of RRAM includes metal oxide layer, is applicable to collection by applying
Become the various degrees of electric pulse of enforcement in circuit, can produce metal oxide layer with change two or
Resistance between more steady resistance scopes.
When ic manufacturing technology is scaled, compared to line pattern, it is used for being formed
The mosaic technology of the top electrode of RRAM becomes relatively to be suitable for.RRAM memory element can include having
The first terminal and an access device of the second terminal, one first connector and contact of contact the first terminal
One second connector of the second terminal.This access device can be transistor or diode.One burning
Layer contacts the upper surface of the first connector and as the memory component in RRAM memory element.One is exhausted
Edge layer is configured on the first connector and the second connector, and has the of corresponding first connector and the second connector
One opening and the second opening.The first top electrode and second can be configured in the first opening and the second opening
Top electrode, and the first top electrode and the second top electrode be respectively connecting to bit line and source electrode line.
In the manufacture method of RRAM memory element, for example, form respective top electricity in the opening
Before pole, aoxidize the upper surface of the first connector and the second connector to form a metal oxide layer.When second
Connector be designed to be electrically connected with access device the second terminal to source electrode line, be positioned at the upper of the second connector
The metal oxide layer on surface will be etched.But, the second connector upper that etching is positioned in the second opening
The metal oxide layer on surface is likely to result in the infringement for the second connector, causes in the second connector higher
Resistance.Furthermore, the sidewall of the second opening in insulating barrier is potentially contaminated.For example, if
Two connectors include that copper (copper, Cu) and metal oxide layer include copper oxide (copper oxide, CuOx),
When etching the metal oxide layer in the second opening, copper may be sputtered on the sidewall of the second opening.
Additionally, etching the second opening in metal oxide layer time, use anti-light erosion mask to protect first
Metal oxide layer in opening.Peeling off anti-light erosion mask after etching, the process of stripping may infringement the
Metal oxide layer in one opening.
Therefore, in order to provide a kind of cost-effective manufacture method, it is desirable to provide a kind of storage is single
Unit and manufacture method thereof, it is possible to eliminate and be connected to inserting of source electrode line by what etching metal oxide layer caused
The infringement probability of plug and by the mask infringement probability that causes of stripping for metal oxide layer,
Wherein metal oxide layer is as programmable resistance element.
Summary of the invention
The present invention provides the manufacture method of a kind of memorizer.The present invention defines corresponding to the first interlayer conductor
First opening of (also known as connector), the upper surface of the first interlayer conductor in the first opening is formed
Metal oxide layer, stops material defining the front deposition first corresponding to the second opening of the second interlayer conductor
The bed of material is in the first opening.Therefore, by etching in the second opening during the method eliminates prior art
The infringement probability for the second interlayer conductor that metal oxide layer is caused, by etching the second opening
In metal oxide layer caused for the possibility of pollution of the sidewall of the second opening in insulating barrier with
And the infringement probability for the metal oxide layer in the first opening caused is peeled off by mask.
In embodiments, the array of interlayer conductor forms insulating barrier.Etching isolation layer is with definition
First opening of the first interlayer conductor in corresponding array, wherein etch stop is in the of the first interlayer conductor
One upper surface.Metal oxide layer is formed on first upper surface of the first interlayer conductor in the first opening.
Diffusion impervious layer, diffusion barrier can be formed between upper surface and the insulating barrier of the array of interlayer conductor
Layer contact upper surface, to prevent from being positioned at the array of interlayer conductor from the diffusion of interlayer conductor stopping
First opening of upper surface and the etching of the second opening.Deposition and metal oxide layer and the first opening
Surface conformal and contact the first barrier material layer, metal oxide layer is positioned on the first interlayer conductor.Logical
Cross subsequent fabrication steps and with formation and then remove the etching mask being positioned on metal oxide layer, the first resistance
Obstructing material layer can protect metal oxide layer to avoid current potential infringement, thus provides metal oxide layer and top electricity
Preferably interface between pole.The width of the first opening can be more than the width of the first interlayer conductor.Deposition
After first barrier material layer, etching isolation layer is to define in array the second of corresponding second interlayer conductor
Opening, wherein etch stop is in the second upper surface of the second interlayer conductor.In deposition and the first opening
First barrier material layer conformal and contact the second barrier material layer.Use conductive material to fill first to open
Mouthful.First and second interlayer conductor is respectively connecting to first and second terminal of access device.
When etching is to define the first opening, it is possible to use the first etching is masked on insulating barrier, wherein
First etching mask has between masks area and corresponding first opening of corresponding second interlayer conductor
Septal area.When etching is to define the second opening, it is possible to use the second etching is masked on insulating barrier, wherein
Second etching mask has masks area and the spacer of corresponding second opening of corresponding first opening.
Second upper surface of the second interlayer conductor in deposition and the second opening and the table of the second opening
Face conformal and contact the second barrier material layer, conductive material can also be used to fill the second opening, its
Middle metal oxide layer is not present between the second upper surface and the second barrier material layer.
Can be electrically connected to metal oxide layer and can be as the first access line of bit line.Can
To be electrically connected to the second interlayer conductor and can be as the second access line of source electrode line.
Can form the access device array of the array coupleding to interlayer conductor, access device array includes
Aforesaid first access device.Aforesaid first access device can include diode or transistor.?
Aforesaid first access device includes, in the embodiment of transistor, can being electrically connected to transistor
The 3rd access line of gate terminal.
The feature of metal oxide layer can be have programmable resistance.First interlayer conductor can be real
It is made up of metal in matter, and metal oxide layer can be included the oxide of metal.First interlayer conductor
Substantially can be made up of transition metal, and metal oxide layer can be included the oxide of transition metal.
Accompanying drawing explanation
Fig. 1 illustrates the profile of the memory element according to an embodiment；
Fig. 2-8 illustrates the exemplary steps manufacturing memory element as shown in Figure 1；
Fig. 9 illustrates resistive random access memory (the Resistive Random according to an embodiment
Access Memory, RRAM) circuit diagram of array；
Figure 10 illustrates the simplification design drawing of the memory element according to the embodiment shown in Fig. 9；
Figure 11 illustrates the circuit diagram of the RRAM array according to the second embodiment；
Figure 12 illustrates the simplification design drawing of the memory element according to the second embodiment shown in Figure 11；
Figure 13 illustrates the circuit diagram of the RRAM array according to the 3rd embodiment；
Figure 14 illustrates the simplification design drawing of the memory element according to the 3rd embodiment shown in Figure 13；
Figure 15 illustrates according to using the diode electricity as the RRAM array of the embodiment of access device
Lu Tu；
Figure 16 illustrates according to using diode as the storage list of the embodiment of access device shown in Figure 15
The simplification design drawing of unit；
The 17th simple flow figure illustrating the embodiment of the method for manufacturing storage arrangement.
[description of reference numerals]
100: memory element
111: the first terminal
112: the second terminals
120: dielectric layer
131, the 941M, 1141M, 1341M: first interlayer conductor
131T: the first upper surface
132, the 941A, 941B, 1141A, 1141B, 1341A: second interlayer conductor
132T: the second upper surface
140: diffusion impervious layer
150: insulating barrier
161: the first openings
162: the second openings
170: metal oxide layer
180: the first barrier layers
181: the first barrier material layers
182: the second barrier material layers
185: conductive material
310: the first etching masks
610: the second etching masks
900,1100,1300,1500:RRAM array
901、902、903、904、1101、1102、1103、1301、1302、1303、1304、
1305,1306,1307,1308,1544: memory element
901A, 1101A: the first transistor
901B, 1101B: transistor seconds
901M, 1101M, 1301M, 1541M, 1542M, 1543M, 1544M: storage unit
Part
911,912,913,1111,1112,1113,1311,1312,1313,1314: the first
Access line
921,922,923,1121,1122,1123,1321,1322,1323,1324: the
Two access lines
931、932、933、934、935、936、1131、1132、1133、1134、1135、
1136,1331,1332,1333,1334: the three access line
1301A: transistor
1511,1512,1513,1514: bit line
1531,1532,1533,1534: wordline
1544D: diode
1510: bit line decoder
1530: word-line decoder
1551,1552,1553,1554: contact
1701,1702,1703,1704,1705,1706,1707: step
W1, W2: width
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with concrete real
Execute example, and referring to the drawings, the present invention is described in further detail.
It should be understood that the embodiments and methods being not intended to limit the invention to specifically disclose, permissible
Further feature, element, method and embodiment is used to implement the present invention.Describe preferred embodiment with
The present invention being described rather than limits its scope, this scope is defined by the claims.Skill belonging to the present invention
The change of the various equivalences that skilled person will appreciate that following narration in art field.In various embodiments
Similar element is generally of similar reference.
Fig. 1 illustrates the profile of the memory element (such as 100) according to an embodiment.At interlayer conductor
Patterned insulation layer (such as 150) is configured on the array of (such as 131,132).Patterned insulation layer (example
Such as 150) include first opening (such as 161) of the first interlayer conductor (such as 131) in corresponding array with
And second opening (such as 162) of the second interlayer conductor (such as 132) in correspondence array.First opening
Extend through patterned insulation layer with the second opening, and stop at the first interlayer conductor (such as 131)
Second upper surface of the first upper surface (such as 131T) and the second interlayer conductor (such as 132) is (such as
132T)。
First interlayer conductor (such as 131) and the second interlayer conductor (such as 132) include conducting element.Lift
For example, interlayer conductor is selected from by titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (Al), hafnium (Hf), tantalum
(Ta), copper (Cu), platinum (Pt), iridium (Ir), lanthanum (La), nickel (Ni), nitrogen (N), oxygen (O) and ruthenium (Ru) institute group
One or more element in the group become and combinations thereof thing, can include in certain embodiments more than one layer.
In one embodiment, first and second interlayer conductor substantially can be made up of metal, and metal
Oxide layer can include the oxide of metal.In another embodiment, first and second interlayer conductor
Substantially can be made up of transition metal, and metal oxide layer can be included the oxide of transition metal.
Metal oxide layer (such as 170) is configured at the first upper surface of the first interlayer conductor (such as 131)
On (such as 131T), and metal oxide layer is not present in the second of the second interlayer conductor (such as 132)
On upper surface (such as 132T).The feature of metal oxide layer can be have programmable resistance, makes
Obtain metal oxide layer and be programmable at least two resistance states.For example, metal oxide layer can include
One or more tungsten-oxygen compound (WOX), such as WO3、W2O5、WO2In one or more.Metal
Oxide layer can have and includes WO3、W2O5And WO2Gradient map, in such metal oxide layer
Oxygen ratio reduces to the first interlayer conductor (such as 131) from the first opening (such as 161).
Shown in embodiment, by aoxidizing the burning that the upper surface of the first interlayer conductor 131 is formed
Layer 170 can be simple layer, and therefore metal oxide layer 170 is self-aligned to the first interlayer conductor 131.
Because the volumetric expansion during formation metal oxide layer, metal oxide layer can be led from the first interlayer
First upper surface of body projects to the first opening.In alternate embodiments, metal oxide layer 170 can
Including other metal-oxides, for example selected from nickel oxide, aluminium oxide, magnesium oxide, cobalt oxide,
Metal-oxide in titanium oxide, titanium oxide-nickel, zirconium oxide and copper oxide group.
Diffusion barrier can be configured between upper surface and the patterned insulation layer of the array of interlayer conductor
Layer (such as 140).Diffusion impervious layer (such as 140) is possible to prevent the diffusion from interlayer conductor.Citing
For, interlayer conductor can include the material such as copper (copper, Cu) of high diffusibility, and this may cause can
By degree problem.Diffusion impervious layer (such as 140) can include silicon nitride (silicon nitride, SiN).?
The upper surface of the array of interlayer conductor, diffusion impervious layer (such as 140) can also stop the first opening with
The etching of the second opening.Thicker diffusion impervious layer can increase the electric capacity of RRAM memory element, and
Relatively thin diffusion impervious layer may be not enough to prevent diffusion or possibility from interlayer conductor from cannot stop
The etching of first and second opening of the upper surface of interlayer conductor.In one embodiment, in 10 nanometers
(nanometer, nm), in the range of 100nm, diffusion impervious layer (such as 140) can have about 30
The thickness of nm, to prevent the diffusion from interlayer conductor, does not cause excessive electric capacity simultaneously.
With on the surface of the first opening on the first interlayer conductor, configure and metal oxide layer (such as 170)
The first barrier layer (such as 180) that is conformal and that contact, wherein the surface of the first opening includes the first opening
Side and bottom surface.First barrier layer (such as 180) can include the first barrier material layer (such as 181)
And conformal and second barrier material layer (such as 182) of contact the first barrier material layer.Implement one
In example, in the range of 1nm to 50nm, first barrier material layer (such as 181) on the first barrier layer
And second barrier material layer (such as 182) can have the thickness of about 10nm.
Second barrier layer can include the second barrier material layer (such as 182), configures in the second opening
Second barrier layer is conformal with the second upper surface of the second interlayer conductor (such as 132) (such as 132T) and connects
Touch, and configuration the second barrier layer is conformal with the side of the second opening and bottom surface and contacts.Second barrier layer
Thickness less than the thickness on the first barrier layer 180.In one embodiment, including the second barrier material layer
Second barrier layer of (such as 182), in the range of 1nm to 50nm, can have about 10nm's
Thickness.
Using conductive material (such as 185) to fill the first opening, conductive material is (such as in the first opening
185) the first barrier layer (such as 180) is contacted.Conductive material (such as 185) is used to fill the second opening,
Conductive material (such as 185) contacts the second barrier layer in the second opening.First barrier material layer is (such as
181) one layer or more of different materials, different materials can be included with the second barrier material layer (such as 182)
Including select free titanium (Ti), titanium nitride (TiN), tungsten (W), aluminium copper (AlCu), tantalum nitride (TaN),
Copper (Cu), hafnium (Hf), tantalum (Ta), gold (Au), platinum (Pt), silver (Ag) and other are compatible with CMOS
And one or many in the group that formed of metal of the variation electrical resistance property not resulting in metal oxide layer
Plant element.
First interlayer conductor (such as 131) and the second interlayer conductor (such as 132) are respectively connecting to access dress
The first terminal (such as 111) put and the second terminal (such as 112).The first terminal of access device and
Two-terminal be configured at dielectric layer relative to the first opening and the side of the second opening.
The array of interlayer conductor extends through dielectric layer (such as 120).Dielectric layer (such as 120) can wrap
Include oxide material such as plasma-based auxiliary (plasma enhanced, PE) oxide, plasma-based auxiliary tetraethoxy
Silane (plasma enhanced tetraethyl orthosilicate, PETEOS) oxide, low pressure four ethoxy
Base silane (low pressure tetraethyl orthosilicate, LPTEOS) oxide, high-density electric slurry
(high density plasma, HDP) oxide, bpsg film (borophosphosilicate
Glass film, BPSG), phosphosilicate glass thin film (phosphosilicate glass film, PSG), fluorine
Silicate glass thin film (fluorosilicate glass film, FSG), low-k (low k) material etc.
Deng.
For example, the conductive material by being filled in the first opening can be electrically connected with the first access
Circuit (not shown) is to metal oxide layer, and the first access line can be as the bit line of memory element.
For example, the conductive material by being filled in the second opening can be electrically connected with the second access line
(not shown) is to the second interlayer conductor, and the second access line can be as the source electrode line of memory element.
First access line and the second access line can include one or more element, and these a little elements include titanium
(Ti), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), tantalum nitride (TaN), hafnium (Hf), tantalum (Ta) and
Nickel (Ni).First access line can include the material identical or different with the second access line.Fill
Conductive material in the first opening (such as 161) with the second opening (such as 162) can be formed at metal
Layer 1 (ML1), and first and second access line can be formed at metal level 2,3,4 or n (ML2,
ML3, ML4 or ... MLn).Furthermore, first and second access line can be formed at different gold
Belong to layer.For example, the first access line can be formed at metal level 3 (ML3), and second accesses
Circuit can be formed at metal level 4 (ML4).
Access device can include diode or transistor.An enforcement of transistor is included at access device
In example, the 3rd access line (not shown) can be electrically connected to the gate terminal of transistor, and the 3rd
Access line can be as the wordline of memory element.
In operation, by metal oxide layer 170 and the first barrier layer 180, first is put on
Voltage between access line and the first interlayer conductor 131 will result in electric current and flows in the first access line
And between the first interlayer conductor 131.This electric current can promote in the resistance of metal oxide layer 170 can
Programming change, this resistance represents the data value being stored in memory element 100.In certain embodiments,
The metal oxide layer 170 of memory element 100 can store the data of two or more.
Fig. 2-8 illustrates the exemplary steps manufacturing memory element as shown in Figure 1.Fig. 2 illustrates with section
Go out to be formed the array of the interlayer conductor extending through dielectric layer and form insulating barrier (such as 150) at layer
Between conductor array on result, wherein interlayer conductor includes the first interlayer conductor (such as 131) and the
Two interlayer conductors (such as 132).In an embodiment, diffusion impervious layer (such as 140) can be formed at absolutely
Between edge layer and dielectric layer, and the upper surface (such as 131T, 132T) of the array of contact interlayer conductor
To stop being positioned at the first opening of the array upper surface of interlayer conductor and the etching of the second opening and protecting
The upper surface of interlayer conductor avoids oxidation.Dielectric layer can include silicon dioxide.Insulating barrier will be by pattern
Change the top electrode forming memory element.First and second interlayer conductor is connected to the first of access device
Terminal and the second terminal (111 in such as Fig. 1 and 112), wherein the first terminal and the second terminal are positioned at
The side relative to insulating barrier of dielectric layer.
Fig. 3 illustrates that etching isolation layer is to define in array the of corresponding first interlayer conductor (such as 131)
One opening (such as 161), wherein etch stop is in first upper surface (such as 131T) of the first interlayer conductor.
In the embodiment forming diffusion impervious layer, also it is etched through diffusion in order to define the etching of the first opening
Barrier layer and stop at the upper surface of the first interlayer conductor in the first opening.At this manufacturing step, right
The opening answering the second interlayer conductor in the array of interlayer conductor is not present in insulating barrier.Citing comes
Say, when etching is to define the first opening, it is possible to use the first etching mask (such as 310) is such as anti-light erosion
Be masked on insulating barrier, wherein the first etching mask have the masks area of corresponding second interlayer conductor with
And the spacer of corresponding first opening (such as 161).
Fig. 4 illustrates the upper shape of the first upper surface (such as 131T) of the first interlayer conductor in the first opening
Become metal oxide layer.Various depositions can be used to form metal oxide layer with oxidation technology, such as Rapid Thermal
Oxidation (Rapid Thermal Oxidation, RTO), photooxidation (photo-oxidation), direct plasma-based
Aoxidize, blow formula plasma-based (down-stream oxidation) oxidation, sputter and reactive sputter.Citing
For, use RTO with tungsten oxide (tungsten, W) or copper (copper, Cu), oxygen or oxygen/
In the environment of nitrogen temperature can from 200 DEG C to 1100 DEG C, process the time can from 5 seconds to 500 seconds,
Typically 30 seconds to 60 seconds.In the first interlayer conductor includes the embodiment of tungsten (tungsten, W),
Electric slurry oxide can cause the W with gradientXOY, its have along with expose with oxidation surface away from
Tungsten-oxygen compound concentration distribution from variation.For example, metal-oxide (such as 170) can have
Have and include WO3、W2O5、WO2Gradient map, the oxygen ratio in such metal oxide layer is from
One opening (such as 161) reduces to the first interlayer conductor (such as 131).Because forming metal oxide layer
During volumetric expansion, metal oxide layer can project to from the first upper surface of the first interlayer conductor
First opening.
Using in the embodiment of RTO oxidation technology, metal oxide layer is 1nm's to 300nm
In the range of can have the thickness of about 50nm.Use in the another embodiment of electric slurry oxide technology,
Metal oxide layer can have the thickness of about 5nm in the range of 1nm to 50nm.
Fig. 5 illustrates the deposition the first barrier material layer (such as 181) knot in the first opening (such as 161)
Really, the first barrier material layer is conformal with metal oxide layer and contacts, and the first barrier material layer and first
The side of opening and bottom surface are conformal and contact, and wherein metal oxide layer is positioned at the of the first interlayer conductor
On one upper surface.In one embodiment, the first barrier material layer (such as 181) is at 1nm to 50nm
In the range of, can have the thickness of about 10nm.First barrier material layer (such as 181) can wrap
Include the one layer or more of different materials, different materials include selecting free titanium, titanium nitride, tungsten, aluminium copper,
Tantalum nitride, copper, hafnium, tantalum, gold, platinum, silver and other are compatible with CMOS and do not result in metal
One or more element in the group that the metal of the variation electrical resistance property of oxide layer is formed.By follow-up
Manufacturing step is to be formed and then to remove the etching mask being positioned on metal oxide layer, the first barrier material
Layer can protect metal oxide layer to avoid current potential infringement, thus provides between metal oxide layer and top electrode
Preferably interface.
The minimum widith of the first opening is based on manufacturing technology.The width of the first opening (such as 161) is (such as
W1) can be more than the width (such as W2) of the first interlayer conductor (such as 131).For example, if
One interlayer conductor includes tungsten (tungsten, W) and has the width of about 100nm, then the first opening is permissible
There is the width more than 120nm.
Fig. 6 illustrates that etching isolation layer (such as 150) is to define second in the array of corresponding interlayer conductor
Second opening (such as 162) of interlayer conductor (such as 132), wherein etch stop is in the second interlayer conductor
The second upper surface (such as 132T).Use after deposition the first barrier material layer as shown in Figure 5
To define this etching step of the second opening, and it is etched through the first barrier material layer (such as 181).
Formed in the embodiment of diffusion impervious layer, be also etched through diffusion resistance in order to define the etching of the second opening
Barrier, and stop at the upper surface of the second interlayer conductor in the second opening.In one embodiment,
The width of the second opening (such as 162) can mate the width of the first opening (such as 161).
Second upper surface of the second interlayer conductor is formed in the existing method of metal oxide layer, need to lead to
Cross technique such as sputter and remove metal oxide layer, thus be likely to result in the sidewall of the second opening in insulating barrier
Pollute.For example, if the second interlayer conductor includes that copper (copper, Cu) and metal oxide layer include oxygen
Change copper (CuOx), when removing metal oxide layer, copper may be sputtered on the sidewall of the second opening.
In an embodiment of the present invention, because metal oxide layer is not present in the second interlayer conductor (such as
132) the second upper surface (such as 132T) is upper and etch stop is in the second interlayer conductor (such as 132)
Second upper surface (such as 132T), along with the second opening in the contingent insulating barrier of existing method
The pollution of sidewall can be reduced to minimum.
In order to define in the manufacturing step of the second opening, it is possible to use the second etching mask (such as 610)
As anti-light erosion is masked on insulating barrier (such as 150) and the first barrier material layer (such as 181), Qi Zhong
Two etching masks have the masks area of corresponding first opening (such as 161) and corresponding second opening (example
Such as 162) spacer.Therefore, in this manufacturing step, by the first barrier material layer and the second erosion
The masks area carved in mask protects the metal oxide layer (such as 170) in the first opening.
After Fig. 7 is shown with second etching mask definition the second opening (such as 162), peel off such as Fig. 6
The result of the second shown etching mask (such as 610).In stripping process, by the first barrier material
Layer (such as 181) protects the metal oxide layer (such as 170) in the first opening.
Deposit in the preliminary procedure of the second barrier material layer, have energy by using from what gaseous matter produced
The plasma-based of amount, it is possible to use plasma-based cleans with from second upper surface (such as 132T) of the second interlayer conductor
Removal of impurity, pollutant and natural oxide.For example, gaseous matter can include argon,
And plasma-based cleaning can etch the degree of depth from about 1nm to 20nm.During plasma-based cleaning, pass through
First barrier material layer (such as 181) protects the metal oxide layer (such as 170) in the first opening.
Fig. 8 is illustrated in the first opening and the second opening and deposits the second barrier material layer (such as 182)
Result.The second barrier material layer in first opening and the first barrier material layer (such as 181) is conformal and
Contact, the second barrier material layer in the second opening and the second upper surface of the second interlayer conductor are (such as
132T) conformal and contact, and the second barrier material layer and the side of the second opening and bottom surface is conformal and
Contact.In one embodiment, the second barrier material layer (such as 182) is in the scope of 1nm to 50nm
In, can have the thickness of about 10nm.First barrier material layer (such as 181) stops material with second
The bed of material (such as 182) can include the one layer or more of different materials, different materials include selecting free titanium,
Titanium nitride, tungsten, aluminium copper, tantalum nitride, copper, hafnium, tantalum, gold, platinum, silver and other with
CMOS is compatible and does not results in the group that the metal changing electrical resistance property of metal oxide layer is formed
In one or more element.
Then conductive material (such as 185) can be filled in the first opening and the second opening.Citing
For, can be electrically connected to metal oxide layer by the conductive material being filled in the first opening
The first access line (not shown), and the first access line can be as the bit line of memory element.Lift
For example, can be electrically connected to the second interlayer by the conductive material being filled in the second opening
Second access line (not shown) of conductor, and the second access line can be as the source electrode of memory element
Line.Being filled in the first opening (such as 161) can be with shape with the conductive material in the second opening (such as 162)
Become metal level 1 (ML1), and first and second access line can be formed at metal level 2,3,4
Or n (ML2, ML3, ML4 or ... MLn).Furthermore, first and second access line can be formed
In different metal levels.For example, the first access line can be formed at metal level 3 (ML3),
And the second access line can be formed at metal level 4 (ML4).
Fig. 9 illustrates resistive random access memory (the Resistive Random according to an embodiment
Access Memory, RRAM) circuit diagram of array.RRAM array 900 includes memory element (example
Such as 901,902,903) row and hurdle, the most each memory element include the first transistor (such as 901A),
Transistor seconds (such as 901B) and be connected to the memory element (such as 901M) of bit line.First with
Transistor seconds can ShiNXing metal-oxide-semiconductor (MOS) (N-type metal oxide semiconductor,
NMOS) transistor.Memory element can include metal oxide layer 170 as shown in Figure 8.Storage is single
Unit can include that the first barrier material layer 181 on metal oxide layer 170 as shown in Figure 1 hinders with second
Obstructing material layer 182.It is single that the first terminal of first and second transistor in memory element is connected to storage
One end of memory element in unit.Three memory element 901,902 and 903 illustrated represent memorizer
One block of cells of array, memory array can include thousands of or millions of memory element.
Multiple first access lines (such as 911,912 and 913) extend and and bit line along a first direction
The memory element electrical communication of decoder (not shown) and memory element.By being configured at memory element
The first interlayer conductor (such as 941M) under (such as 901M), of the memory element in memory element
One first access line that end is connected in multiple first access line, and the other end is connected to storage list
The first terminal of first and second transistor in unit.The profile of the first interlayer conductor (such as 131)
It is illustrated in Fig. 8.Multiple first access lines can be as bit line.
Multiple second access lines (such as 921,922 and 923) extend along a first direction, and terminate
In source line termination circuit (not shown).By the second interlayer conductor (such as 941A and 941B), the
First and second transistor in two access lines (such as 921) and memory element (such as 901A with
The second terminal electrical communication 901B).The profile of the second interlayer conductor (such as 132) is illustrated in Fig. 8
In.Multiple second access lines can be as source electrode line.
Multiple 3rd access lines (such as 931 to 936) are along the second direction being orthogonal to first direction
Extend.3rd access line and word-line decoder (not shown) electrical communication, and can be as wordline.
The gate terminal of first and second transistor (such as 901A with 901B) in memory element is each connected
To the 3rd access line.Bit line decoder and word-line decoder can include CMOS
(Complementary Metal Oxide Semiconductor, CMOS) circuit.
Figure 10 illustrates the simplification design drawing of the memory element according to embodiment illustrated in fig. 9.With with Fig. 9
In similar reference represent element similar in Figure 10.The layout of memory element can be vertically
Repeat with horizontal direction.To put it more simply, do not show that insulant, for example, be positioned at first,
Second and the 3rd insulant between access line.
This design drawing illustrate the first access line 911 and 912 as bit line (Bit Lines, BL), second
Access line 921 and 922 is as source electrode line (Source Lines, SL), the 3rd access line 931,932
With 933 as wordline (Word Lines, WL).In one embodiment, permissible in metal level 1
Configure the first access line and the second access line.First, second is connected to deposit with the 3rd access line
Storage unit (such as 901 and 904), as depicted in figure 9.Memory element includes that memory element is (such as
901M), memory element can include metal oxide layer 170 as shown in Figure 8.Memory element is permissible
Including the first barrier material layer 181 and the second barrier material layer on metal oxide layer as shown in Figure 1
182。
Figure 11 illustrates the resistive random access memory (Resistive according to the second embodiment
Random Access Memory, RRAM) circuit diagram of array.RRAM array 1100 includes depositing
The row of storage unit (such as 1101,1102 and 1103) and hurdle, the most each memory element includes first crystal
Pipe (such as 1101A), transistor seconds (such as 1101B) and memory element (such as 1101M).The
One with transistor seconds can ShiNXing metal-oxide-semiconductor (MOS) (N-type metal oxide semiconductor,
NMOS) transistor.Memory element can include the first barrier material on memory element as shown in Figure 1
Layer 181 and the second barrier material layer 182.Memory element can include burning as shown in Figure 8
Layer 170.The first terminal of first and second transistor in memory element is connected in memory element deposit
One end of storage element, and in memory element, the second terminal of first and second transistor is connected to source electrode line
(such as 1121).Three memory element 1101,1102 and 1103 illustrated represent memory array
One block of cells, memory array can include thousands of or millions of memory element.
Multiple first access lines (such as 1111,1112 and 1113) extend along a first direction, and with
Bit line decoder (not shown) electrical communication.Multiple first access lines can be as bit line.Multiple
Two access lines (such as 1121,1122 and 1123) extend along the second direction being orthogonal to first direction,
And terminate at source line termination circuit (not shown).Multiple second access lines can be as source electrode line.
Memory element includes being configured at the first interlayer conductor under memory element (such as 1101M) (such as
1141M), the first interlayer conductor (such as 1141M) connect memory element (such as 1101M) to first with
The first terminal of transistor seconds (such as 1101A and 1101B), and the second interlayer conductor is (such as
1141A with 1141B) it is connected the second terminal of first and second transistor to source electrode line (such as 1121).
First interlayer conductor (such as 131) is illustrated in Fig. 8 with the profile of the second interlayer conductor (such as 132).
Multiple 3rd access lines (such as 1131 to 1136) extend along a first direction.3rd access line
Road and word-line decoder (not shown) electrical communication, and can be as wordline.In memory element first
It is each attached to the 3rd access line with the gate terminal of transistor seconds (such as 1101A and 1101B).
Bit line decoder and word-line decoder can include CMOS (Complementary
Metal Oxide Semiconductor, CMOS) circuit.
Figure 12 illustrates the simplification design drawing according to the memory element of the second embodiment shown in Figure 11.With with
Reference similar in Figure 11 represents element similar in Figure 12.The layout of memory element can be
Vertical and horizontal direction is repeated.To put it more simply, do not show that insulant, for example, be positioned at
One, the second and the 3rd insulant between access line.
This design drawing illustrate the first access line (such as 1111) as bit line (Bit Lines, BL), second
Access line (such as 1121,1122 and 1123) is as source electrode line (Source Lines, SL), and the 3rd deposits
Line taking road (such as 1131,1132 and 1133) is as wordline (Word Lines, WL).An embodiment party
In case, metal level 1 can configure the second access line, and can configure the first access line in
Metal level 2 on metal level 1.First, second and the 3rd access line be connected to memory element (such as
1101,1102 and 1103), as depicted in figure 11.Memory element includes memory element (such as 1101M),
Memory element can include metal oxide layer 170 as shown in Figure 8.Memory element can include such as figure
The first barrier material layer 181 and the second barrier material layer 182 on metal oxide layer shown in 1.
Figure 13 illustrates the resistive random access memory (Resistive according to the 3rd embodiment
Random Access Memory, RRAM) circuit diagram of array.RRAM array 1300 includes depositing
The row of storage unit (such as 1301,1302,1303,1304,1305,1306,1307 and 1308)
With hurdle, the most each memory element includes a transistor (such as 1301A) and memory element is (such as
1301M).Transistor can ShiNXing metal-oxide-semiconductor (MOS) (N-type metal oxide semiconductor,
NMOS) transistor.Memory element can include metal oxide layer 170 as shown in Figure 8.Storage is single
Unit can include that the first barrier material layer 181 on metal oxide layer 170 as shown in Figure 1 hinders with second
Obstructing material layer 182.The first terminal of the transistor in memory element is connected in memory element storage unit
One end of part.The memory element illustrated represents a block of cells of memory array, and memory array can
To include thousands of or millions of memory element.
Multiple first access lines (such as 1311,1312,1313 and 1314) prolong along a first direction
Stretch and with bit line decoder (not shown) electrical communication, multiple first access lines are connected to memory element
The second end, the second end is relative to being connected to the end of the first terminal of transistor in memory element.Many
Individual first access line can be as bit line.Memory element can include being configured at memory element (such as
The first interlayer conductor (such as 1341M) under 1301M), the first interlayer conductor (such as 1341M) connects
Memory element is to the first terminal of transistor (such as 1301A).Cuing open of first interlayer conductor (such as 131)
Face illustrates in Fig. 8.
Multiple second access lines (such as 1321,1322,1323 and 1324) are along being orthogonal to first
The second direction in direction extends, and terminates at source line termination circuit (not shown).Multiple second accesses
Circuit can be as source electrode line.Memory element can include that the second terminal connecting transistor is to source electrode line
The second interlayer conductor (such as 1341A) of (such as 1321).The section of the second interlayer conductor (such as 132)
Diagram is in Fig. 8.
Multiple 3rd access lines (such as 1331 to 1334) extend along a first direction.3rd access
Circuit and word-line decoder (not shown) electrical communication, and can be as wordline.Crystalline substance in memory element
The gate terminal of body pipe (such as 1301A) is each attached to the 3rd access line.Bit line decoder and word
Line decoder can include CMOS (Complementary Metal Oxide
Semiconductor, CMOS) circuit.
Figure 14 illustrates according to the simplification design drawing of the memory element of the 3rd embodiment shown in Figure 13.With with
Reference similar in Figure 13 represents element similar in Figure 14.The layout of memory element can be
Vertical and horizontal direction is repeated.To put it more simply, do not show that insulant, for example, be positioned at
One, the second and the 3rd insulant between access line.
This design drawing illustrate the first access line 1311 and 1312 as bit line (Bit Lines, BL),
Two access lines 1321,1322 and 1323 are as source electrode line (Source Lines, SL), the 3rd access
Circuit 1331 and 1132 is as wordline (Word Lines, WL).In one embodiment, at metal level
The second access line can be configured in 1, and first access line gold on metal level 1 can be configured
Belong in layer 2.First, second and the 3rd access line be connected to memory element (such as 1301 to 1303
With 1305 to 1306), as illustrated in fig. 13.Memory element includes memory element (such as 1301M),
Memory element can include metal oxide layer 170 as shown in Figure 8.Memory element can include such as figure
The first barrier material layer 181 and the second barrier material layer 182 on metal oxide layer shown in 1.
Figure 15 shows according to using the diode electricity as the RRAM array of the embodiment of access device
Lu Tu.Memory array 1500 include the matrix of memory element, a plurality of wordline (such as 1531,1532,
1533 and 1534) and multiple bit lines (such as 1511,1512,1513 and 1514).Exemplary memory
Each memory element (such as 1544) in array 1500 is in corresponding wordline (such as 1534) and corresponding position
Sequentially include between line (such as 1511) accessing diode (such as 1544D) with memory element (such as
1544M).Each memory element is electrically coupled to the access diode of correspondence.
Memory element in memory array 1500 can include on memory element as shown in Figure 1
One barrier material layer 181 and the second barrier material layer 182.Memory element in memory element include as
Metal oxide layer 170 in memory element shown in Fig. 8.
Prolong including bit line 1511,1512,1513 is the most parallel with the multiple bit lines of 1514
Stretch.Bit line and bit line decoder 1510 electrical communication.Memory element can be connected to the sun of diode
Between pole or negative electrode and bit line.For example, memory element 1544M is connected to diode 1544D
Negative electrode and bit line 1511 between.A plurality of word including wordline 1531,1532,1533 and 1534
Line extends in parallel along second direction.Wordline 1531,1532,1533 and 1534 and word-line decoder
1530 electrical communication.The male or female of diode is connectable to wordline.For example, diode
The anode of 1544D is connected to wordline 1534.Bit line decoder can include complementary with word-line decoder
Metal-oxide-semiconductor (MOS) (Complementary Metal Oxide Semiconductor, CMOS) circuit.Should note
16 memory element being intended in 15 are to illustrate for convenience of discussion and so, but actually deposit
Memory array can include thousands of or millions of this kind of memory element.
Figure 16 illustrates according to using diode as the storage list of the embodiment of access device shown in Figure 15
The simplification design drawing of unit.Element similar in Figure 16 is represented with the reference similar to Figure 15.
The layout of memory element can repeat in vertical and horizontal direction.To put it more simply, do not show that insulation material
Material, for example, at first, second and the 3rd insulant between access line.
This design drawing illustrates that the first access line 1511,1512,1513 and 1514 is as bit line (Bit
Lines, BL), the second access line 1531,1532,1533 and 1534 as wordline (Word Lines,
WL).In memory element, the second access line can include the active for diode (such as 1544D)
Region, and in order to wordline pick up (pickup), the second access circuit can be connected to contact (such as 1551,
1552,1553 and 1554).In one embodiment, metal level 1 can configure bit line, position
Bit line in wordline can include polysilicon.First and second access line is connected to memory element (example
Such as 1544), as depicted in figure 15.Memory element include memory element (such as 1541M, 1542M,
1543M and 1544M), memory element can include metal oxide layer 170 as shown in Figure 8.Deposit
Storage unit can include that the first barrier material layer 181 and second on memory element as shown in Figure 1 stops
Material layer 182.
The 17th simple flow figure illustrating the embodiment of the method for manufacturing storage arrangement.In step
Rapid 1701, the array of interlayer conductor is formed insulating barrier.On the upper surface of the array of interlayer conductor
And diffusion impervious layer, diffusion impervious layer contact upper surface can be formed between insulating barrier.In step 1702,
Etching isolation layer to define the first opening of the first interlayer conductor in corresponding array, wherein etch stop in
First upper surface of the first interlayer conductor.When etching is to define the first opening, it is possible to use the first erosion
Mask at quarter (such as 310), wherein the first etching mask had corresponding second interlayer conductor on insulating barrier
Masks area and the spacer of corresponding first opening (such as 161).
Step 1703, the first upper surface of the first interlayer conductor in the first opening are formed metal
Oxide layer.The feature of metal oxide layer can be have programmable resistance.In step 1704, heavy
The first barrier material layer that is long-pending conformal with the surface of metal oxide layer and the first opening and that contact, metal
Oxide layer is positioned on the first interlayer conductor.It is positioned at gold to be formed with then removing by subsequent fabrication steps
Belonging to the etching mask in oxide layer, the first barrier material layer can be protected metal oxide layer to avoid current potential and damage
Evil, thus preferably interface between offer metal oxide layer and top electrode.
In step 1705, after depositing the first barrier material layer, etching isolation layer is corresponding to define in array
Second opening of the second interlayer conductor, wherein etch stop is in the second upper surface of the second interlayer conductor.
When etching is to define the second opening, it is possible to use the second etching is masked on insulating barrier, wherein second
Etching mask has masks area and the spacer of corresponding second opening of corresponding first opening.In step
Rapid 1706, deposit the second barrier material that is conformal with the first barrier material layer in the first opening and that contact
Layer.For example, same steps can also deposit with the second interlayer conductor in the second opening
The surface of two upper surfaces and the second opening conformal and contact the second barrier material layer.
In step 1707, conductive material is used to fill the first opening.For example, in same steps also
Conductive material can be used to fill the second opening, wherein metal oxide layer be not present in the second upper surface with
Between second barrier material layer.The width of the first opening can be more than the width of the first interlayer conductor.
First and second interlayer conductor can be respectively connecting to first and second terminal of access device.Deposit
Fetching is put and can be included diode or transistor.The access of the array coupleding to interlayer conductor can be formed
Apparatus array, interlayer conductor includes first and second interlayer conductor.
It will be appreciated that memory array is not limited to the array structure shown in Figure 12, can also be adjoint
And include that the memory element of above-mentioned top electrode layer uses extra array structure.Additionally, it is real at some
Execute in example, in addition to MOS transistor, bipolar transistor or diode can be used as access
Device.
Particular embodiments described above, is carried out the purpose of the present invention, technical scheme and beneficial effect
Further describe it should be understood that the foregoing is only the specific embodiment of the present invention,
Be not limited to the present invention, all within the spirit and principles in the present invention, any amendment of being made,
Equivalent, improvement etc., should be included within the scope of the present invention.
Claims (22)
1. the method manufacturing memorizer, including:
Form an insulating barrier on an array of multiple interlayer conductors；
Etch this insulating barrier to define one first opening, this first opening to should in array one first
Interlayer conductor, etch stop is in one first upper surface of this first interlayer conductor；
Form this of the metal oxide layer this first interlayer conductor in this first opening table on first
On face；
Deposit one first barrier material layer, this first barrier material layer and being somebody's turn to do on this first interlayer conductor
Metal oxide layer is conformal and contacts, and multiple surfaces of this first barrier material layer and this first opening are altogether
Shape and contact, wherein the width of this first opening is more than the width of this first interlayer conductor；
At this insulating barrier of after etching of this first barrier material layer of preceding deposition to define one second opening,
This second opening to should one second interlayer conductor in array, etch stop is in this second interlayer conductor
One second upper surface；
Deposit one second barrier material layer, in this second barrier material layer and this first opening this first
Barrier material layer is conformal and contacts；And
A conductive material is used to fill this first opening；
Wherein this first interlayer conductor and this second interlayer conductor are respectively connecting to the one of an access device
The first terminal and one second terminal.
2. the method for claim 1, it is characterised in that also include:
Form a diffusion impervious layer in multiple upper surfaces and this insulation of this array of described interlayer conductor
Between Ceng, this diffusion impervious layer contacts described upper surface.
3. the method for claim 1, it is characterised in that aforementioned etching with define this first
The step of opening, including:
Using one first etching to be masked on this insulating barrier, this first etching mask has should second
One masks area of opening and to should a spacer of the first opening.
4. the method for claim 1, it is characterised in that aforementioned etching with define this second
The step of opening, including:
Using one second etching to be masked on this insulating barrier, this second etching mask has should first
One masks area of opening and to should a spacer of the second opening.
5. the method for claim 1, it is characterised in that this second stop material of preceding deposition
The step of the bed of material, including:
Deposit this second barrier material layer, in this second barrier material layer and this second opening this second
This second upper surface of interlayer conductor is conformal and contacts, and this second barrier material layer and this second opening
Multiple surfaces conformal and contact；And
This conductive material is used to fill this second opening.
6. the method for claim 1, it is characterised in that including:
Forming one first access line, this first access line is electrically connected to this metal oxide layer；With
And
Forming one second access line, this second access line is electrically connected to this second interlayer conductor.
7. the method for claim 1, it is characterised in that including:
Forming an array of multiple access device, this array coupled to this array of described interlayer conductor,
And this array of described access device includes this access device of mentioning for the first time.
8. the method for claim 1, it is characterised in that this access dress mentioned for the first time
Put and include a diode.
9. the method for claim 1, it is characterised in that this access dress mentioned for the first time
Put and include a transistor, including:
Forming one the 3rd access line, the 3rd access line is electrically connected to a grid of this transistor
Terminal.
10. the method for claim 1, it is characterised in that the feature of this metal oxide layer is
There is a programmable resistance.
11. the method for claim 1, it is characterised in that this first interlayer conductor is substantially
It is made up of a metal, and this metal oxide layer is included the monoxide of this metal.
12. the method for claim 1, it is characterised in that this first interlayer conductor is substantially
It is made up of a transition metal, and this metal oxide layer is included the monoxide of this transition metal.
13. 1 kinds of memorizeies, including:
One patterned insulation layer, is positioned on an array of multiple interlayer conductor, this patterned insulation layer bag
Include one first opening and one second opening, this first opening to should one first interlayer conductor in array,
This second opening is to should one second interlayer conductor in array；
One metal oxide layer, is positioned on one first upper surface of this first interlayer conductor；
One first barrier layer, conformal with this metal oxide layer on this first interlayer conductor and contact, and
This first barrier layer is conformal with multiple surfaces of this first opening and contacts, the wherein width of this first opening
Degree is more than the width of this first interlayer conductor；
One second barrier layer, is positioned on this second opening, and wherein the thickness on this second barrier layer is less than being somebody's turn to do
The thickness on the first barrier layer；And
One conductive material, is filled in this first opening；
Wherein this first interlayer conductor and this second interlayer conductor are respectively connecting to the one of an access device
The first terminal and one second terminal.
14. memorizeies as claimed in claim 13, it is characterised in that also include:
One diffusion impervious layer, is positioned at multiple upper surfaces and this patterning of this array of described interlayer conductor
Between insulating barrier, and this diffusion impervious layer contacts described upper surface.
15. memorizeies as claimed in claim 13, it is characterised in that also include:
One second upper surface of this second interlayer conductor in this second barrier layer, with this second opening is altogether
Shape also contacts, and this second barrier layer is conformal with multiple surfaces of this second opening and contacts；And
This conductive material, fills this second opening.
16. memorizeies as claimed in claim 13, it is characterised in that also include:
One first access line, is electrically connected to this metal oxide layer；And
One second access line, is electrically connected to this second interlayer conductor.
17. memorizeies as claimed in claim 13, it is characterised in that also include:
An array of multiple access devices, coupled to this array of described interlayer conductor, and described access
This array of device includes this access device mentioned for the first time.
18. memorizeies as claimed in claim 13, it is characterised in that this mentioned for the first time is deposited
Fetching is put and is included a diode.
19. memorizeies as claimed in claim 13, it is characterised in that this mentioned for the first time is deposited
Fetching is put and is included a transistor, and this memorizer includes:
One the 3rd access line, is electrically connected to a gate terminal of this transistor.
20. memorizeies as claimed in claim 13, it is characterised in that the spy of this metal oxide layer
Levy as having a programmable resistance.
21. memorizeies as claimed in claim 13, it is characterised in that this first interlayer conductor is real
It is made up of a metal in matter, and this metal oxide layer is included the monoxide of this metal.
22. memorizeies as claimed in claim 13, it is characterised in that this first interlayer conductor is real
It is made up of a transition metal in matter, and this metal oxide layer is included the monoxide of this transition metal.
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