CN106158847B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN106158847B CN106158847B CN201510150344.5A CN201510150344A CN106158847B CN 106158847 B CN106158847 B CN 106158847B CN 201510150344 A CN201510150344 A CN 201510150344A CN 106158847 B CN106158847 B CN 106158847B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 300
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 229910044991 metal oxide Inorganic materials 0.000 claims description 85
- 150000004706 metal oxides Chemical class 0.000 claims description 85
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 description 130
- 239000012535 impurity Substances 0.000 description 26
- 230000003068 static effect Effects 0.000 description 20
- 230000005611 electricity Effects 0.000 description 16
- 230000008878 coupling Effects 0.000 description 10
- 238000010168 coupling process Methods 0.000 description 10
- 238000005859 coupling reaction Methods 0.000 description 10
- 230000005540 biological transmission Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 230000012447 hatching Effects 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 150000002927 oxygen compounds Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical group [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000007306 turnover Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BMSYAGRCQOYYMZ-UHFFFAOYSA-N [As].[As] Chemical compound [As].[As] BMSYAGRCQOYYMZ-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- VRAIHTAYLFXSJJ-UHFFFAOYSA-N alumane Chemical compound [AlH3].[AlH3] VRAIHTAYLFXSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices.The semiconductor device includes the first metal-oxide-semiconductor structure, the second metal-oxide-semiconductor structure and bipolar junction structure.First metal-oxide-semiconductor structure includes the first drain region, first passage area and the first source area, is successively arranged along first direction.First metal-oxide-semiconductor structure further includes drain electrode, is formed on the first drain region and is electrically coupled to the first drain region and body zone, is formed under first passage area and is electrically coupled to first passage area.Second metal-oxide-semiconductor structure includes the second drain region, second channel area and the second source area, is successively arranged in a second direction, and second direction is different from first direction.Bipolar junction structure includes emitter region, base region and collector region.The first common semiconductor area is shared in first source area and the second drain region in a substrate.The second common semiconductor area is shared in drain electrode and base region in a substrate.Body zone and collector region share third common semiconductor area in a substrate.
Description
Technical field
The invention relates to a kind of semiconductor devices, and in particular to a kind of static discharge
(electrostatic discharge, ESD) protective device.
Background technique
Double carriers-complementary metal oxide semiconductor-double-diffusing metal dioxide semiconductor (Bipolar-
CMOS-DMOS (BCD), wherein CMOS represents " complementary metal oxide semiconductor (complementary metal-oxide-
Semiconductor) ", DMOS represents " double-diffusing metal dioxide semiconductor (double-diffused metal-
Oxide-semiconductor) ") high pressure has been widely used for triple-well process technology (triple well process)
Using, such as electrostatic discharge protective (ESD protection).In general, the static discharge of high voltage electrostatic discharge protective device
The efficiency of protection is depending on the overall width of grid of device and the surface of device or lateral dimension (lateral rule).For
The lesser high voltage electrostatic discharge protective device of size, surface-volume ratio (surface-bulk ratio) compared to size compared with
Big device is larger, thus the surface area of the lesser device of size has in the efficiency of device compared to larger-size device
Large effect power.Therefore, excellent electrostatic discharge protective efficiency is obtained in the lesser device of relative size with more challenge
Property.Furthermore since the operation voltage of device increases, the design of the electrostatic discharge protective of (on-chip) also becomes to have more on chip
Challenge.
High voltage electrostatic discharge protective device usually has low on-resistance (on-state resistance, RDS-on) spy
Property.When static discharge generates, the electric current of static discharge is easy the surface concentrated on close to high voltage protection device or drains it
Place, thus lead to high current density and electric field in surface tie region (surface junction region), and in these regions
Cause physical destruction.Therefore, compared to the device with larger conducting resistance, the surface area of high voltage protection device is for it
Efficiency may have large effect, therefore surface and lateral dimension may have large effect in high voltage protection device.
Other characteristics of high voltage protection device include such as high-breakdown-voltage (high breakdown voltage), breakdown
Voltage is usually above the operation voltage of high voltage protection device.In addition, the trigger voltage V of high-pressure installationt1(trigger voltage,
Vt1) it is typically much higher than the breakdown voltage of high-pressure installation.Therefore, during static discharge, high voltage protection device be connected with
Before electrostatic protection is provided, it may be met by the device or internal circuit (protective device/circuit here also called) protected
Face the risk of damage.In general, in order to reduce the trigger voltage of high voltage protection device, it may be necessary to construct again one it is additional
External electrostatic discharges circuit for detecting.
High voltage protection device usually has the characteristic of low hold voltage (low holding voltage).Low hold voltage
High voltage protection device be may cause by undesired noise or booting crest voltage (power-on peak voltage) or dashed forward
Wave voltage (surge voltage) is triggered, thus latch (latch-up) effect may occur in course of normal operation.
Furthermore high voltage protection device may have field plate effect (field plate effect).It is, high voltage protection
In device the distribution of electric field for be connected to different device or be connected to device different piece route wiring (routing)
It is sensitive.As a result, as indicated above, the electric current of static discharge be easier to concentrate on surface close to high-pressure installation or
Drain electrode place.
Summary of the invention
A kind of semiconductor device provided according to the present invention, including a substrate, one first metal oxygen being formed in substrate
Compound semiconductor structure, one second metal-oxide semiconductor (MOS) and a bipolar junction (Bipolar Junction, BJ) structure.
First metal-oxide-semiconductor structure includes one first drain region (drain region), a first passage area (channel
Region) and one first source area (source region), successively arranged along a first direction.First metal oxide half
Conductor structure further includes a drain electrode (drain electrode), is formed on the first drain region and is electrically coupled to
One drain region and a body zone (body region), are formed under first passage area and are electrically coupled to first passage area.
Second metal-oxide-semiconductor structure includes one second drain region, a second channel area and one second source area, successively edge
The arrangement of one second direction, second direction are different from first direction.Bipolar junction structure include an emitter region (emitter region),
One base region (base region) and a collector region (collector region).First source area and the second drain region exist
One first common semiconductor area is shared in substrate.One second common semiconductor area is shared in drain electrode and base region in a substrate.
Body zone and collector region share a third common semiconductor area in a substrate.
In addition, a kind of semiconductor device is also provided according to the present invention, including a substrate, the high pressure gold being formed in substrate
Belong to oxide semiconductor (High-Voltage Metal-Oxide-Semiconductor, HV MOS) structure, a low pressure metal
Oxide semiconductor (Low-Voltage Metal-Oxide-Semiconductor, LV MOS) structure and a bipolar junction
Structure.High-voltage metal oxide semiconductor structure include one first semiconductor region, one second semiconductor region, a third semiconductor region with
And one the 4th semiconductor region.First semiconductor region has a first conductive type and one first doping level (doping level).
Second semiconductor region is formed on the first semiconductor region, and has the first conductive type and one second doping level, the second doping
Degree is higher than the first doping level.Third semiconductor region has a second conductive type, and the 4th semiconductor region has the first conduction
Type.First semiconductor region is a drain region of high-voltage metal oxide semiconductor structure.Second semiconductor region is high-pressure metal oxygen
One drain electrode of compound semiconductor structure and the drain region for being electrically coupled to high-voltage metal oxide semiconductor structure.Third half
Conductor region includes a channel region of high-voltage metal oxide semiconductor structure.4th semiconductor region is that high pressure metal oxide is partly led
The source region of body structure.First semiconductor region, third semiconductor region and the 4th semiconductor region are successively arranged along a first direction.
Low pressure metal oxide-semiconductor structure includes the 4th semiconductor region, one the 5th semiconductor region and one the 6th semiconductor region.The
Five semiconductor regions have the second conductive type, and the 6th semiconductor region has the first conductive type.4th semiconductor region is low pressure metal
One drain region of oxide-semiconductor structure.5th semiconductor region is a channel region of low pressure metal oxide-semiconductor structure.
6th semiconductor region is the source region of low pressure metal oxide-semiconductor structure.4th semiconductor region, the 5th semiconductor region with
6th semiconductor region is successively arranged along a second direction, and second direction is different from first direction.Bipolar junction structure includes the second half
Conductor region, one the 7th semiconductor region and one the 8th semiconductor region.7th semiconductor region be formed on the first semiconductor region and
It is contacted with the second semiconductor region, and the 8th semiconductor region is formed under third semiconductor region and has the second conductive type.7th
Semiconductor region has the second conductive type and is an emitter region of bipolar junction structure.8th semiconductor region is a collection of bipolar junction structure
Polar region and also be high-voltage metal oxide semiconductor structure a body zone.Third semiconductor region and the 8th semiconductor region be with
Multiple portions in one continuity trap of the second conductive type.
In addition, also providing a kind of semiconductor device according to the present invention, comprising: a substrate, one first trap are formed in substrate
In, one first heavily doped region, be formed in the first trap, one second trap, be formed in substrate, one second heavily doped region, be formed in
In second trap, a third heavily doped region, be formed in the first trap and one the 4th heavily doped region, be formed in the second trap.First
Trap has a first conductive type and one first doping level.First heavily doped region has the first conductive type and one second doping journey
Degree, the second doping level are higher than the first doping level.One second trap has a second conductive type and a third doping level.Second
Heavily doped region has the first conductive type and one the 4th doping level, and the 4th doping level is higher than the first doping level.Third is heavily doped
Miscellaneous area has the second conductive type and one the 5th doping level, and the 5th doping level is higher than third doping level.The third heavy doping
Area is contacted with the first heavily doped region.4th heavily doped region has the first conductive type and one the 6th doping level, the 6th doping level
Higher than the first doping level.Second trap includes a side, is formed between the first trap and the second heavily doped region and a top, shape
At between the second heavily doped region and the 4th heavily doped region.First trap, side and the second heavily doped region are successively along a first party
To arrangement.Second heavily doped region, top and the 4th heavily doped region are successively arranged along a second direction, and second direction is different from the
One direction.
Feature and advantage consistent with the present invention illustrates part below, and partial feature and advantage is in following
Be in description it will be apparent that or can practical application through the invention and learn.These feature and advantage will be by appended
Claim specifically noted by device and combinations thereof and be achieved and reach.
Reason is it should be understood that above general description is with the embodiment of following detailed description all only to make
To demonstrate and explaining, and it is not intended to limit the invention.
Appended attached drawing includes in the description, and to constitute part of specification, appended attached drawing depicts of the invention
Several embodiments, and with narration principle for explaining the present invention together.
More preferably understand to have to the above-mentioned and other aspect of this creation, preferred embodiment is cited below particularly, and cooperates institute
Attached drawing is described in detail below:
Detailed description of the invention
Fig. 1 is the equivalent circuit diagram of an electrostatic discharge protective device of an exemplary embodiment according to the present invention
(equivalent circuit)。
Fig. 2 is the plan view of the electrostatic discharge protective device of a part of an exemplary embodiment according to the present invention.
Fig. 3 A to Fig. 3 D is the sectional view of the electrostatic discharge protective device in Fig. 2.
Fig. 4 A to Fig. 4 C is the electrostatic discharge protective device of a part of another exemplary embodiment according to the present invention
Sectional view.
Fig. 5 A and Fig. 5 B is the plan view and sectional view for being painted the traditional type electrostatic discharge protective device of a part respectively.
Fig. 6 A and Fig. 6 B shows that the static discharge of traditional type electrostatic discharge protective device and embodiment according to the present invention is anti-
The current -voltage curve figure of the measurement of protection unit.
Fig. 7 A and Fig. 7 B shows the ESD protection device of traditional type electrostatic discharge protective device and embodiment according to the present invention
Measurement transmission line pulse curve graph (transmission line pulse curves).
Fig. 8 shows the electrostatic discharge protective device of traditional type electrostatic discharge protective device and embodiment according to the present invention
The electricity area of safety operaton curve graph (electrical safe-operating area curves, ESOA) of measurement.
[symbol description]
100,200,400: electrostatic discharge protective device
102: high-voltage metal oxide semiconductor structure
102a: the first sub- high-voltage metal oxide semiconductor structure
102b: the second sub- high-voltage metal oxide semiconductor structure
102-2: high voltage drain
102-4: high pressure grid
102-6: high pressure source electrode
102-8: high pressure bulk
104: low pressure metal oxide-semiconductor structure
104-2: low pressure drain electrode
104-4: low voltage gate
104-6: low pressure source electrode
104-8: low pressure body
106: bipolar junction structure
106a: the first bipolar junction structure of son
106b: the second bipolar junction structure of son
106-2: emitter-base bandgap grading
106-4: base stage
106-6: collector
108: power supply supplies terminal
110: circuit ground terminal
112: internal circuit
The one of 102a+104: the first sub- high-voltage metal oxide semiconductor structure and low pressure metal oxide-semiconductor structure
Total
The one of 102b+104: the second sub- high-voltage metal oxide semiconductor structure and low pressure metal oxide-semiconductor structure
Total
202: substrate
204: high-pressure N-shaped trap
204-1: the first high-pressure N-shaped trap part
204-2: the second high-pressure N-shaped trap part
206:P type trap
206-1:P type trap middle section
206-2: the first p-type trap side section
The type trap bottom 206-3:P point
206-4: the second p-type trap side section
Part on 206-5:P type trap
208-1: the first N-type trap
208-2: the second N-type trap
210-1: the one N+Area
210-2: the two N+Area
212: the three N+Area
214: the four N+Area
216: the one P+Area
218-1: the two P+Area
218-2: the three P+Area
220: polysilicon layer
220-1: the first polysilicon segment
220-2: the second polysilicon segment
220-3: third polysilicon segment
222: insulating layer
222-1: the first thin insulating part
222-2: the second thin insulating part
222-3: third thin insulating part
224-1: the first contact hole
224-2: the second contact hole
224-3: third contact hole
224-4: the four contact hole
402-1: the first shallow n-type trap
402-2: the second shallow n-type trap
500: traditional type electrostatic discharge protective device
Specific embodiment
The embodiment of the present invention includes a high voltage electrostatic discharge protective device.
Hereinafter, the embodiment of the present invention will be described with reference to the drawings, and phase is used as much as possible in all attached drawings
With symbolic device censure same or similar device.
Fig. 1 is painted the equivalent circuit of exemplary high voltage electrostatic discharge protective device 100 of the invention.Electrostatic discharge protective
Device 100 includes that the high-voltage metal oxide semiconductor structure 102 that is formed in a device, a low pressure metal oxide are partly led
Body structure 104 and a bipolar junction structure 106.It is, as described below, it is high-voltage metal oxide semiconductor structure 102, low
Metal-oxide-semiconductor structure 104 and bipolar junction structure 106 electric property coupling each other are pressed, without using other metal wire
Road.In example shown in Fig. 1, high-voltage metal oxide semiconductor structure 102 and low pressure metal oxide-semiconductor structure 104
It is all the structure of N channel metal-oxide semiconductor (MOS) (N channel MOS, NMOS), and bipolar junction structure 106 is that a PNP is bis-
Pole junction structure (wherein " N " and " P " refers respectively to N-type conductivity type and P-type conduction type).In some embodiments, high-pressure metal oxygen
Compound semiconductor structure 102 and low pressure metal oxide-semiconductor structure 104 are also possible to P channel metal-oxide semiconductor (MOS) (P
Channel MOS, PMOS) structure, and bipolar junction structure 106 can be the bipolar junction structure of a NPN.
In equivalent circuit depicted in Fig. 1, high-voltage metal oxide semiconductor structure 102 include one drain electrode (also referred to as "
High voltage drain ") 102-2, a grid (also referred to as " high pressure grid ") 102-4, a source electrode (also referred to as " high pressure source electrode ") 102-6 with
And ontology (also referred to as " high pressure bulk ") 102-8.To conduct the high-voltage metal oxide semiconductor structure 102 of electric current
One channel is formed in high pressure bulk 102-8 between high voltage drain 102-2 and high pressure source electrode 102-6.Low pressure metal oxygen
Compound semiconductor structure 104 includes drain electrode (also referred to as " low pressure drain electrode ") 104-2, a grid (also referred to as " low voltage gate ")
104-4, a source electrode (also referred to as " low pressure source electrode ") 104-6 and an ontology (also referred to as " low pressure body ") 104-8.To conduct
One channel of the low pressure metal oxide-semiconductor structure 104 of electric current between low pressure drain electrode 104-2 and low pressure source electrode 104-6 it
Between, and be formed in low pressure body 104-8.
Show as depicted in FIG. 1, bipolar junction structure 106 includes an emitter-base bandgap grading 106-2, a base stage 106-4 and a collector 106-6.
High voltage drain 102-2 and emitter-base bandgap grading 106-2 electric property coupling each other, and high voltage drain 102-2 and emitter-base bandgap grading 106-2 is also electrically coupled to
Terminal 108, terminal 108 can be connected to power supply unit (terminal 108 is also referred to as " power supply supply terminal ").Low pressure source electrode 104-6
With collector 106-6 electric property coupling each other, and low pressure source electrode 104-6 and collector 106-6 are also electrically coupled to terminal 110, terminal
110 can be connected to circuit ground (circuit ground) (terminal 110 is also referred to as " circuit ground terminal ").Base stage 106-4 is logical
It crosses a resistor (resistor) and is electrically coupled to power supply supply terminal 108, can be an internal resistor in semiconductor-based
In plate, wherein high-voltage metal oxide semiconductor structure 102, a low pressure metal oxide-semiconductor structure 104 and one are bipolar
Junction structure 106 is formed in semiconductor substrate.Show as depicted in FIG. 1, high pressure grid 102-4 and low voltage gate 104-4 are electrical each other
Coupling, and high pressure grid 102-4 and low voltage gate 104-4 are also electrically coupled to internal circuit 112, internal circuit 112 is by quiet
Discharge of electricity protective device 100 is protected.
In equivalent circuit shown in FIG. 1, high pressure source electrode 102-6 and low pressure drain electrode 104-2 electric property coupling each other.As under
The embodiment of the present invention of description, high pressure source electrode 102-6 and low pressure drain electrode 104-2 are physically shared static discharge and prevented by text
A common region in protection unit 100.In other words, a common semiconductor region in electrostatic discharge protective device 100
As the source area of high-voltage metal oxide semiconductor structure 102 and the drain region of low pressure metal oxide-semiconductor structure 104
The two.Therefore, in the circuit layout (circuit layout) in electrostatic discharge protective area 100, connection high pressure source electrode 102-6 with
The route (wiring) of low pressure drain electrode 104-2 can be omitted, and cause lesser stitching (footprint).Therefore, electrostatic is put
The size of electric protective device 100 can be contracted by.
In addition, in equivalent circuit shown in FIG. 1, high voltage drain 102-2 and base stage 106-4 electric property coupling each other.As
The embodiment of the present invention being described below, base stage 106-4 are also a drain electrode electricity of high-voltage metal oxide semiconductor structure 102
Pole, it is, the base stage 106-4 of bipolar junction structure 106 and the drain electrode of high-voltage metal oxide semiconductor structure 102 are object
Rationally share the common region in electrostatic discharge protective device 100.In addition, high pressure bulk 102-8, low pressure body 104-8
And collector 106-6 electric property coupling each other.Such as the embodiment of the present invention being described below, high pressure bulk 102-8, low pressure sheet
Body 104-8 and collector 106-6 is another common region physically shared in electrostatic discharge protective device 100.
Fig. 2 is the plan view of the electrostatic discharge protective device 200 of a part of exemplary embodiment according to the present invention.
Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D are that the static discharge in Fig. 2 respectively along A-A ', B-B ', C-C ' and D-D ' hatching is anti-
The sectional view of protection unit 200.As illustrated in Figure 2, A-A ', B-B ', C-C ' hatching extend in X direction, and D-D ' hatching edge
Y-direction extends.X-direction is perpendicular to Y-direction.Electrostatic discharge protective device 200 is corresponding etc. with one shown as depicted in FIG. 1
Imitate circuit.Corresponding high-voltage metal oxide semiconductor structure, low pressure metal oxide-semiconductor structure and bipolar junction
Structure is painted by dotted line is illustrated in Fig. 2, Fig. 3 A, in Fig. 3 C and Fig. 3 D.
Fig. 2 and Fig. 3 A to Fig. 3 D are please referred to, electrostatic discharge protective device 200 includes that a p-type substrate 202, one is high-pressure N-shaped
Trap (HV N-Well) 204 and a p-type trap (P-Well) 206.High-pressure N-shaped trap 204 is formed in p-type substrate 202.P-type trap
206 are formed in high-pressure N-shaped trap 204.As depicted in Fig. 2 and Fig. 3 A to Fig. 3 C, for the middle section 206-1 of p-type trap 206
For (below also referred to as " p-type trap middle section 206-1 "), electrostatic discharge protective device 200 has a symmetrical junction in X-direction
Structure.Therefore, in electrostatic discharge protective device 200, region or structure on the left of p-type trap middle section 206-1 have a phase
Corresponding region or structure are on the right side of p-type trap middle section 206-1.For example, as depicted in Fig. 2 and Fig. 3 C, high-pressure metal oxygen
Compound semiconductor structure 102 includes one first sub- high-voltage metal oxide semiconductor structure 102a and one second sub- high-pressure metal
Oxide-semiconductor structure 102b, for p-type trap middle section 206-1, the first sub- high-voltage metal oxide semiconductor knot
Structure 102a is almost asymmetrically formed each other with the second sub- high-voltage metal oxide semiconductor structure 102b.Similarly, bipolar junction
Structure 106 includes the one first son bipolar junction structure 106b of bipolar of junction structure 106a and one second, for p-type trap middle section
For 206-1, the first bipolar junction structure 106a of son is almost asymmetrically formed each other with the second bipolar junction structure 106b of son.Low pressure gold
Belong to oxide-semiconductor structure 104 to be formed on p-type trap middle section along Y-direction.In Fig. 3 A, label 102a+104 is represented
A total of first sub- high-voltage metal oxide semiconductor structure 102a and low pressure metal oxide-semiconductor structure 104,
And label 102b+104 represents the second sub- high-voltage metal oxide semiconductor structure 102b and low pressure metal oxide semiconductor knot
One total of structure 104.
Electrostatic discharge protective device 200 also includes one first N-type trap 208-1 and one second N-type trap 208-2.First N-type
Trap 208-1 and the second N-type trap 208-2 is formed in high-pressure N-shaped trap 204 and is electrically coupled to high-pressure N-shaped trap 204.For p-type trap
For the 206-1 of middle section, the first N type trap 208-1 and the second N-type trap 208-2 almost (about) is symmetrically arranged each other.One
First heavily doped N-type (heavily-doped N-type, N+) area 210-1 and one second heavily doped N-type area (the 2nd N+Area) 210-
2 are each formed among or on the first N-type trap 208-1 and the second N-type trap 208-2.First N+Area 210-1 and the 2nd N+Area
210-2 is respectively electrically coupled to the first N-type trap 208-1 and the second N-type trap 208-2, and for p-type trap middle section 206-1 and
Speech, the first N+Area 210-1 and the 2nd N+Area 210-2 is almost symmetrically arranged each other.In the present invention, a heavily doped region be can be
One region, has a doping level or impurity concentration is about 1 × 1015/ cubic centimetre is to about 1 × 1020/ cubic centimetre is higher.
Electrostatic discharge protective device 200 further includes third heavily doped N-type area (the 3rd N+Area) 212 with it is one the 4th heavily doped
Miscellaneous N-type region (the 4th N+Area) 214.3rd N+Area 212 and the 4th N+Area 214 is formed in p-type trap 206 along Y-direction.3rd N+Area
212 and the 4th N+Area 214 is similar to each other, in addition to one first heavily doped P-type (heavily-doped P-type, P+) 216 shape of area
Tetra- N of Cheng Yu+In area 214 (as depicted in Fig. 2 and Fig. 3 A), but the 3rd N is formed in without p-type trap+In area 212 (such as Fig. 2 with
Depicted in Fig. 3 C).As depicted in Fig. 3 A, the first P+Area 216 is to pass through the 4th N all the way+Area 214 is formed, and it is physical with it is electrical
It is contacted with p-type trap 206.Therefore, the 4th N+Area 214 includes left subregion (left sub region) right son of 214-1 and one
Region (right sub region) 214-2, left subregion 214-1 and right subregion 214-2 is respectively arranged in the first P+Area 216
Two sides, and for p-type trap middle section 206-1, left subregion 214-1 and right subregion 214-2 are almost symmetrical each other
Ground arrangement.
As depicted in Fig. 2, Fig. 3 A and Fig. 3 C, it is similar to p-type trap 206, the 3rd N+Area 212 and the 4th N+Area 214 is also along the side X
To the center for being arranged in electrostatic discharge protective device 200.Therefore, region or the knot of p-type trap middle section 206-1 are almost symmetrical with
Structure is also almost symmetrical with the 3rd N+Area 212 and the 4th N+Area 214.As depicted in Fig. 2, Fig. 3 A and Fig. 3 C, electrostatic discharge protective dress
Setting 200 further includes one second heavily doped P-type area (the 2nd P+Area) 218-1 and third heavily doped P-type area (the 3rd P+Area) 218-
2.2nd P+Area 218-1 and the 3rd P+Area 218-2 is each formed in the first N+Area 210-1 and the 2nd N+Among area 210-2, and it is each
Self-forming is on the first N-type trap 208-1 and the second N-type trap 208-2.As depicted in Fig. 3 A and Fig. 3 C, the 2nd P+Area 218-1
With the 3rd P+Area 218-2 respectively passes through the first N all the way+Area 210-1 and the 2nd N+Area 210-2 is formed, and is respectively contacted with first
N-type trap 208-1 and the second N-type trap 208-2.
In electrostatic discharge protective device 200, p-type substrate 202 can be an a p-type chip (such as P-type silicon chip (P-
Type silicon wafer)), be epitaxially grown in a P-type layer (the P-type layer epitaxially of growth substrate
Grown on a growth substrate) or a P-type silicon coating insulator substrate (P-type silicon-on-
insulator substrate).Impurity concentration (i.e. doping level) in p-type substrate is about 1 × 1010/ cubic centimetre is to about
1×1015/ cubic centimetre.In some embodiments, high-pressure N-shaped trap 204 can be for example, by being ion implantation (ion
Implantation) or N-type impurity is mixed in p-type substrate 202 and is formed by diffusion method (diffusion), and N-type impurity is for example
It is antimony (antimony), arsenic (arsenic) or phosphorus (phosphorou).In some embodiments, high-pressure N-shaped trap 204 can be with
It is formed by epitaxial growth one N-type semiconductor substrate in a p-type substrate 202.High-pressure N-shaped trap 204 also may include multiple heaps
Folded n type buried layer (N-type buried layer) together.In some embodiments, the impurity in high-pressure N-shaped trap 204 is dense
Spending (i.e. doping level) is about 1 × 1010/ cubic centimetre is to about 1 × 1016/ cubic centimetre.
P type impurity can be mixed high pressure N type trap 204 for example, by being ion implantation or diffusion method by p-type trap 206
It is formed, p type impurity is, for example, boron (boron), aluminium (aluminum) or gallium (gallium).In some embodiments, p-type trap
206 also may include multiple P type buried layers (P-type buried layer) being stacked together.In some embodiments, in p-type
Impurity concentration (i.e. doping level) in trap 206 is about 1 × 1012/ cubic centimetre is to about 1 × 1020/ cubic centimetre.
First N-type trap 208-1 and the second N-type trap 208-2 can be by mixing other N-type impurity in high-pressure N-shaped trap 204
To be formed.Therefore, the impurity concentration in the first N-type trap 208-1 and the second N-type trap 208-2 is higher than miscellaneous in high-pressure N-shaped trap 204
Matter concentration.In some embodiments, impurity concentration in the first N-type trap 208-1 and the second N-type trap 208-2 between about 1 ×
1010/ cubic centimetre is to about 1 × 1016Among the range of/cubic centimetre.First N+Area 210-1 and the 2nd N+Area 210-2 can pass through
Other N-type impurity is mixed respectively in the first N-type trap 208-1 and the second N-type trap 208-2 and is formed.In some embodiments,
First N+Area 210-1 and the 2nd N+Impurity concentration in area 210-2 is between about 1 × 1015/ cubic centimetre is to about 1 × 1020/ cube
Centimetre range among.
3rd N+Area 212 and the 4th N+Area 214 can be formed and mixing N-type impurity in p-type trap 206.In some implementations
In example, each 3rd N+Area 212 and the 4th N+Impurity concentration in area 214 is between about 1 × 1015/ cubic centimetre is to about 1 × 1020/
Among the range of cubic centimetre.In some embodiments, N+Region 210-1,210-2,212 and 214 are formed in identical mix
In miscellaneous step, e.g. identical ion implanting step or identical diffusing step.
First P+Area 216 can be by mixing the 4th N for p type impurity+It is formed in area 214.In some embodiments, the first P+Impurity concentration in area 216 is between about 1 × 1015/ cubic centimetre is to about 1 × 1020Among the range of/cubic centimetre.Similarly,
2nd P+Area 218-1 and the 3rd P+P type impurity can be by being mixed the first N by area 218-2 respectively+Area 210-1 and the 2nd N+Area
It is formed in 210-2.In some embodiments, the 2nd P+Area 218-1 and the 3rd P+Impurity concentration in area 218-2 is between about 1
×1015/ cubic centimetre is to about 1 × 1020Among the range of/cubic centimetre.In some embodiments, P+Region 216,218-1 with
And 218-2 is formed in identical doping step, e.g. identical ion implanting step or identical diffusing step.
As depicted in Fig. 2 and Fig. 3 A to Fig. 3 D, electrostatic discharge protective device 200 also includes a continuity polysilicon layer
(continuous polysilicon layer) 220 and insulating layer 222.Continuity polysilicon layer 220 is formed in high-pressure N-shaped
On trap 204 and p-type trap 206, and continuity insulating layer 222 is formed in polysilicon layer 220 and high-pressure N-shaped trap 204 or p-type trap
Between 206.The different parts of continuity polysilicon layer 220 are formed in the different metal oxygens of electrostatic discharge protective device 200
The gate electrode of compound semiconductor structure.In addition, the different parts of insulating layer 222 are constituted according to above-mentioned continuity polysilicon layer
Gate electrode gate dielectric film (gate dielectric films).Insulating layer 222 may, for example, be an oxide layer.
According to the present invention, above-mentioned different zones are as the first sub- high-voltage metal oxide semiconductor structure 102a and second
The element of the different function of sub- high-voltage metal oxide semiconductor structure 102b, low pressure metal oxide-semiconductor structure 104
The element of the different function of the element of different function and the bipolar junction structure 106b of bipolar of junction structure 106a and second of the first son
It will be detailed further below.
First sub- high-voltage metal oxide semiconductor structure 102a includes the first N-type trap 208-1, the first N+Area 210-1,
A part of high-pressure N-shaped trap 204 (below also referred to as " the first high-pressure N-shaped trap part 204-1 "), a part of p-type trap 206 are (below
Referred to as " the first p-type trap side section 206-2 "), another part p-type trap 206 (below also referred to as " 206-3 is divided in p-type trap bottom ") with
And the 3rd N+Area 212.First high-pressure N-shaped trap part 204-1 is between the first N-type trap 208-1 and p-type trap 206.First p-type
Trap side section 206-2 is between the first high-pressure N-shaped trap part 204-1 and the 3rd N+Between area 212.P-type trap bottom divides 206-3 to connect
To the first p-type trap side section 206-2 and the 3rd N+Area 212.According to the present invention, the first N-type trap 208-1, the first N+Area 210-1,
206-3 and the 3rd N is divided in first high-pressure N-shaped trap part 204-1, the first p-type trap side section 206-2, p-type trap bottom+Area 212
Drain electrode, drain electrode, drift region, channel region, ontology respectively as the first sub- high-voltage metal oxide semiconductor structure 102a
Area and source area.If a those skilled in the art understands, drift region means the region in a transistor unit,
This region is between the drain region of transistor and the channel region of transistor and/or is a region, this region is between transistor
Between source area and the channel region of transistor, wherein this region is usually relatively slightly to mix compared to drain region or source area
It is miscellaneous, and help to be promoted the breakdown voltage of transistor.
Similarly, the second sub- high-voltage metal oxide semiconductor structure 102b includes the second N-type trap 208-2, the 2nd N+Area
The high-pressure N-shaped trap 204 (below also referred to as " the second high-pressure N-shaped trap part 204-2 ") of 210-2, another part, another part p-type trap
206-3 and the 3rd N is divided in 206 (below also referred to as " the second p-type trap side section 206-4 "), p-type trap bottom+Area 212.Second is high
Press N-type trap part 204-2 between the second N-type trap 208-2 and p-type trap 206.Second p-type trap side section 206-4 is between second
High-pressure N-shaped trap part 204-2 and the 3rd N+Between area 212.According to the present invention, the second N-type trap 208-2, the 2nd N+Area 210-2,
206-3 and the 3rd N is divided in two high-pressure N-shaped trap part 204-2, the second p-type trap side section 206-4, p-type trap bottom+Distinguish in area 212
As the drain electrode of the second sub- high-voltage metal oxide semiconductor structure 102b, drain electrode, drift region, channel region, body zone with
And source area.
Low pressure metal oxide-semiconductor structure 104 includes the 3rd N+Area 212, another part p-type trap 206 are (following to be also referred to as
Make " part 206-5 on p-type trap "), p-type trap bottom divide 206-3 and the 4th N+Area 214.On p-type trap part 206-5 immediately in
The lower section of insulating layer 222, and between the 3rd N+Area 212 and the 4th N+Between area 212.According to the present invention, the 3rd N+Area 212, p-type
206-3 and the 4th N is divided in part 206-5, p-type trap bottom on trap+Area 212 is respectively as low pressure metal oxide semiconductor knot
Drain electrode, channel region, body zone and the source area of structure 104.
Show as depicted in FIG. 1, the ontology 102-8 and low pressure metal oxide half of high-voltage metal oxide semiconductor structure 102
The ontology 104-8 of conductor structure 104 electric property coupling each other, and also it is electrically coupled to circuit ground terminal 110.Such as Fig. 3 A to Fig. 3 D
Depicted and above-mentioned, the channel region and body zone of different metal-oxide-semiconductor structure 102a, 102b and 104 includes connecting
The different piece of continuous property p-type trap 206, thus electric property coupling each other.According to the present invention, it is physical with electrically contact to p-type trap
206 the first P+Area 216 is also metal-oxide-semiconductor structure 102a, 102b and a 104 bulk electrode (body
electrode)。
Depicted in e.g. Fig. 3 C, the first N-type trap 208-1, the first high-pressure N-shaped trap part 204-1, the first p-type trap side
Divide 206-2, the 3rd N+Area 212, the second p-type trap side section 206-4, the second high-pressure N-shaped trap part 204-2 and the second N-type trap
208-2 is arranged in X direction according to described sequence.In addition, for p-type trap middle section 206-1, the first N-type trap 208-1
It is almost symmetrically arranged each other with the second N-type trap 208-2.For p-type trap middle section 206-1, the first high-pressure N-shaped trap
Part 204-1 is almost symmetrically arranged each other with the second high-pressure N-shaped trap part 204-2.For p-type trap middle section 206-1
Speech, the first p-type trap side section 206-2 are almost symmetrically arranged each other with the 2nd P type trap side section 206-4.
As depicted in Fig. 3 D, the 3rd N+Part 206-5 and the 4th N in area 212, p-type trap+Area 214 is according to described sequence
It is arranged along Y-direction.
Depicted in e.g. Fig. 3 C and Fig. 3 C, polysilicon layer 220 includes one first polysilicon segment 220-1, more than one second
A crystal silicon part 220-2 and third polysilicon segment 220-3.First polysilicon segment 220-1 is as the first sub- high-pressure metal oxygen
A gate electrode of compound semiconductor structure 102a.Second polysilicon segment 220-2 is as the second sub- high pressure metal oxide half
A gate electrode of conductor structure 102b.Third polysilicon segment 220-3 is as low pressure metal oxide-semiconductor structure 104
One gate electrode.Correspondingly, insulating layer 222 includes one first thin insulating part 222-1, one second thin insulating part 222-2
With a third thin insulating part 222-3.First thin insulating part 222-1, the second thin insulating part 222-2 and third thin insulating portion
Divide 222-3 respectively as the first sub- high-voltage metal oxide semiconductor structure 102a, the second sub- high-voltage metal oxide semiconductor
The gate dielectric film of structure 102b and low pressure metal oxide-semiconductor structure 104.
Depicted in e.g. Fig. 3 A, the first bipolar junction structure 106a of son includes the 2nd P+Area 218-1, the first N+Area 210-1, P
Type trap 206 and the first P+Area 216.2nd P+Area 218-1, the first N+Area 210-1, p-type trap 206 and the first P+Area 216 divides
An emitter region, a base region, a collector region and a collector electrode not as the first bipolar junction structure 106a of son.Similarly,
The second bipolar junction structure 106b of son includes the 3rd P+Area 218-2, the 2nd N+Area 210-2, p-type trap 206 and the first P+Area 216.
3rd P+Area 218-2, the 2nd N+Area 210-2, p-type trap 206 and the first P+Area 216 is respectively as the second bipolar junction structure of son
An emitter region, a base region, a collector region and a collector electrode of 106b.
As illustrated in Figure 2, electrostatic discharge protective device 200 includes one first contact hole 224-1 and one second contact hole
224-2.First contact hole 224-1 is formed in the first N+Area 210-1 and the 2nd P+On area 218-1 and it is electrically coupled to the first N+
Area 210-1 and the 2nd P+Area 218-1.Second contact hole 224-2 is formed in the 2nd N+Area 210-2 and the 3rd P+On area 218-2
And it is electrically coupled to the 2nd N+Area 210-2 and the 3rd P+Area 218-2.In order to briefly describe, the first contact hole 224-1 connects with second
Touching window 224-2 is omitted in Fig. 3 A to Fig. 3 C.As depicted in Fig. 2 and Fig. 3 D, electrostatic discharge protective device 200 further includes one the
Three contact hole 224-3.Third contact hole 224-3 is formed in the 4th N+Area 214 and the first P+On area 216 and it is electrically coupled to
Four N+Area 214 and the first P+Area 216.As illustrated in Figure 2, electrostatic discharge protective device 200 also includes one the 4th contact hole 224-4.
4th contact hole 224-4 is formed on polysilicon layer 220 and is electrically coupled to polysilicon layer 220.
According to the present invention, the first contact hole 224-1 as the first sub- high-voltage metal oxide semiconductor structure 102a one
An emitter contact of drain contact and the first bipolar junction structure 106a of son are simultaneously electrically coupled to power supply supply terminal 108 and (are not painted
In Fig. 2).Second contact hole 224-2 as the second sub- high-voltage metal oxide semiconductor structure 102b a drain contact with
An emitter contact of the second bipolar junction structure 106b of son is simultaneously electrically coupled to power supply supply terminal 108.Third contact hole 224-3 makees
For a source contact and bipolar junction structure 106 (including the first bipolar junction structure of son of low pressure metal oxide-semiconductor structure 104
The bipolar junction structure 106b of of 106a and second) a collector contact and be electrically coupled to circuit ground terminal 110 and (be not illustrated in figure
In 2 and Fig. 3 D).4th contact hole 224-4 is partly led as high-voltage metal oxide semiconductor structure 102 and low pressure metal oxide
The gate contact of body structure 104 is simultaneously electrically coupled to internal circuit 112 (not being illustrated in Fig. 2).
Each first contact hole 224-1, the second contact hole 224-2, third contact hole 224-3 and the 4th contact hole 224-
4 can be by depositing a metal institute on corresponding lower layer region (corresponding underlying regions)
It is formed, metal is, for example, aluminium.In some embodiments, the first contact hole 224-1, the second contact hole 224-2, third contact hole
By one metal layer of deposition, then patterning is formed simultaneously 224-3 and the 4th contact hole 224-4 on entire substrate.
As above-mentioned, in electrostatic discharge protective device 200, high-voltage metal oxide semiconductor structure 102 (including the
The one sub- sub- high-voltage metal oxide semiconductor structure 102b of high-voltage metal oxide semiconductor structure 102a and second) it is formed in base
Among plate 202, there are the different functional areas arranged in X direction, and low pressure metal oxide-semiconductor structure 104 is formed in base
Among plate 202, have along the different functional areas that Y-direction arranges.Above-mentioned arrangement is illustrated in the plan view of Fig. 2.In addition, low
Pressure metal-oxide-semiconductor structure 104 is formed using the middle section of high-voltage metal oxide semiconductor structure 102.Cause
This, is not required to additional chip area to form low pressure metal oxide-semiconductor structure 104.Furthermore as above-mentioned, high-pressure metal
Oxide-semiconductor structure 102 and low pressure metal oxide-semiconductor structure 104 use common semiconductor region, also
It is the 3rd N+Area 212 is respectively as source area and drain region.Therefore, high-voltage metal oxide semiconductor structure 102 and low pressure
Electric property coupling is formed metal-oxide-semiconductor structure 104 without additional route, and without contact hole (contact) each other
In the 3rd N+On area 212 and it is electrically coupled to the 3rd N+Area 212.As above-mentioned arrangement is as a result, electrostatic discharge protective device
200 size is contracted by, and anti-compared to traditional only static discharge including high-voltage metal oxide semiconductor structure is manufactured
Protection unit does not need additional photoetching ablation shield to manufacture electrostatic discharge protective device 200.
Another high voltage electrostatic discharge protective device 400 of the embodiment of Fig. 4 A to Fig. 4 C display according to the present invention.Electrostatic is put
The plan view of electric protective device 400 is identical as the plan view of electrostatic discharge protective device 200 depicted in Fig. 2, therefore does not show
Show.Fig. 4 A to Fig. 4 C is respectively the cuing open along the electrostatic discharge protective device 200 of A-A ', B-B ' and C-C ' hatching in Fig. 2
Face figure.It is and static discharge in fig. 3d along the sectional view of the electrostatic discharge protective device 400 of D-D ' hatching in Fig. 2
The sectional view of protective device 200 is identical, therefore does not show.
Electrostatic discharge protective device 400 is similar to electrostatic discharge protective device 200, in addition to electrostatic discharge protective device 400
It further include one first shallow n-type trap 402-1 and one second shallow n-type trap 402-2.First shallow n-type trap 402-1 and the second shallow n-type trap
402-2 can be formed by mixing other N-type impurity in the first N-type trap 208-1 and the second N-type trap 208-2 respectively.Cause
This, the impurity concentration in the first shallow n-type trap 402-1 and the second shallow n-type trap 402-2 is higher than the first N-type trap 208-1 and the 2nd N
Impurity concentration in type trap 208-2.In this embodiment, the first N+Area 210-1 and the 2nd N+Area 210-2 can be by by other N
Type impurity is mixed in the first shallow n-type trap 402-1 and the second shallow n-type trap 402-2 respectively and is formed.Therefore the first shallow n-type trap 402-
1 and the second impurity concentration in shallow n-type trap 402-2 be lower than the first N+Area 210-1 and the 2nd N+Impurity concentration in area 210-2.
In some embodiments, the impurity concentration in the first shallow n-type trap 402-1 and the second shallow n-type trap 402-2 is between about 1 × 1015/ vertical
Square centimetre to about 1 × 1020Among the range of/cubic centimetre.According to the present invention, compared to depicted in Fig. 3 A to Fig. 3 D first
The son bipolar junction structure 106b of son of bipolar junction structure 106a and second, the first bipolar junction structure of son depicted in Fig. 4 A to Fig. 4 C
The bipolar junction structure 106b of of 106a and second has additional the first shallow n-type trap 402-1 and the second shallow n-type trap 402-2, Ke Yigeng
It is easy to be switched on.
Compared to traditional type device (such as traditional type electrostatic discharge protective device 500 depicted in Fig. 5 A and Fig. 5 B, wherein
Fig. 5 A is plan view and Fig. 5 B is in fig. 5 along E-E ' hatching being formed by sectional view), embodiment according to the present invention
Device (also referred to as following " new-type electrostatic discharge protective device), such as the static discharge depicted in Fig. 2, Fig. 3 A to Fig. 3 D
Protective device 200 or the electrostatic discharge protective device 400 depicted in Fig. 4 A to Fig. 4 C have the high pressure for being integrated in a device
Metal-oxide-semiconductor structure and low pressure metal oxide-semiconductor structure, and in addition to metal-oxide-semiconductor
Outside structure, also there is built-in bipolar junction structure.Only there is a high-pressure metal oxygen compared to traditional type electrostatic discharge protective device 500
Compound semiconductor structure.In this way, in the new-type electrostatic discharge protective device of embodiment according to the present invention, since metal aoxidizes
Object semiconductor structure and bipolar junction structure share the same substrate region of part, total required for new-type electrostatic discharge protective device
Substrate regions are almost and only with 500 phase of traditional type electrostatic discharge protective device of a high-voltage metal oxide semiconductor structure
Together.During operating new-type electrostatic discharge protective device, metal-oxide-semiconductor structure is simultaneously turned on bipolar junction structure,
Therefore static discharge current passes through both metal-oxide-semiconductor structure and bipolar junction structure.In the phase of electrostatic discharge event
Between, static discharge current can also flow the path deeper by bipolar junction structure.Therefore, new-type electrostatic discharge protective device has
Lower conducting resistance and improved area of safety operaton (safe-operating area, SOA).For example, compared to traditional type
Electrostatic discharge protective device 500, the conducting resistance of new-type electrostatic discharge protective device can be contracted by about 13.2% to about
17.6%, and the area of safety operaton of new-type electrostatic discharge protective device can be enhanced about 10.3% to about 31.8%.
The electric characteristics and electrostatic discharge protective device 200 and static discharge of traditional type electrostatic discharge protective device 500 are anti-
Be compared between the electric characteristics of protection unit 400 as the result is shown in Fig. 6 A, Fig. 6 B, Fig. 7 A, Fig. 7 B and Fig. 8.
Particularly, Fig. 6 A and Fig. 6 B show traditional type electrostatic discharge protective device 500 and electrostatic discharge protective device 200 and
Drain current versus drain voltage (the I of the actual measurement of electrostatic discharge protective device 400DS-VDS) curve (wherein " IDS" be referred to as and leak
Electrode current, " VDS" be referred to as drain voltage).Fig. 6 A shows the linear zone (linear of drain current versus drain voltage curve
Regions), the linear zone and saturation region (saturation regions) of Fig. 6 B display drain current versus drain voltage curve
The two.As shown in Figure 6A, in linear zone, under identical drain voltage, electrostatic discharge protective device 200 and electrostatic are put
The drain current of electric protective device 400 is greater than the drain current of traditional type electrostatic discharge protective device 500.In addition, when drain electrode electricity
Pressure increases, and compared to the drain current of traditional type electrostatic discharge protective device 500, electrostatic discharge protective device 200 and electrostatic are put
The drain current of electric protective device 400 increases very fast.Such situation indicates that electrostatic discharge protective device 200 and static discharge are anti-
The conducting resistance of protection unit 400 is less than the conducting resistance of traditional type electrostatic discharge protective device 500.Furthermore as shown in Fig. 6 B,
When device enters saturation region, the drain current of electrostatic discharge protective device 200 and electrostatic discharge protective device 400, which is higher than, to be passed
The drain current of system formula electrostatic discharge protective device 500.It is, electrostatic discharge protective device 200 and electrostatic discharge protective dress
Set 400 saturation current (IDS-sat) it is higher than the saturation current of traditional type electrostatic discharge protective device 500.In conclusion such as Fig. 6 A
With shown in Fig. 6 B, when electrostatic discharge event occurs, compared to traditional type electrostatic discharge protective device 500, static discharge is anti-
Protection unit 200 and electrostatic discharge protective device 400 are capable of handling biggish electric current.
Transmission line pulse (Transmission Line Pulse, TLP) test is carried out to assess electrostatic discharge protective device
200 and electrostatic discharge protective device 400 and traditional type electrostatic discharge protective device 500 electrostatic discharge protective efficiency.Fig. 7 A
Show the transmission of traditional type electrostatic discharge protective device 500 and electrostatic discharge protective device 200 and electrostatic discharge protective device 400
Line pulse curve.Fig. 7 B is the enlarged drawing of transmission line pulse curve, and the details of the part of turnover (snapback) occurs for display,
It is exactly to be triggered in device with the part (region being circled in Fig. 7 A) of conducting.In Fig. 7 A and Fig. 7 B, trunnion axis generation
Table drain voltage and vertical axis represents drain current.As shown in Fig. 7 A and Fig. 7 B, when turnover occurs, electrostatic discharge protective dress
Set 200 and electrostatic discharge protective device 400 drain current be higher than traditional type electrostatic discharge protective device 500 drain current.
In other words, the trigger current of each electrostatic discharge protective device 200 and electrostatic discharge protective device 400 is higher than traditional type electrostatic
The trigger current of electric discharge protective device 500.Particularly, the trigger current of electrostatic discharge protective device 200 is higher than traditional type electrostatic
About 3 times of trigger current of electric discharge protective device 500, and the trigger current of electrostatic discharge protective device 400 is higher than traditional type electrostatic
About 5 times of trigger current of electric discharge protective device 500.In view of higher trigger current, compared to traditional type electrostatic discharge protective
Device 500 is less prone to that latch-up occurs in electrostatic discharge protective device 200 and electrostatic discharge protective device 400.
Fig. 8 shows traditional type electrostatic discharge protective device 500 and electrostatic discharge protective device 200 and electrostatic discharge protective
The measurement result of the electricity area of safety operaton of device 400.The electricity area of safety operaton of one device determines a current-voltage side
Boundary, wherein device can be switched safely, that is, if applying a voltage is more than drain voltage to device, device may be burnt
It ruins, that is, damages.Therefore, the device with biggish electricity area of safety operaton can be safe under higher application voltage
Ground running.In general, the electricity area of safety operaton of device can be measured in a manner of being similar to transmission line pulse test, but
It is the grid (such as no-voltage applies so far grid) that device is applied to using fixed voltage.Show as depicted in figure 8, Mei Gejing
The electricity area of safety operaton of discharge of electricity protective device 200 and electrostatic discharge protective device 400 is anti-higher than traditional type static discharge
The electricity area of safety operaton of protection unit 500.Particularly, the electricity area of safety operaton of electrostatic discharge protective device 200 is higher than
About 1.3 times of the electricity area of safety operaton of traditional type electrostatic discharge protective device 500, and the electricity of electrostatic discharge protective device 400
Learn about 1.2 times of electricity area of safety operaton that area of safety operaton is higher than traditional type electrostatic discharge protective device 500.
Following table 1 summarizes electrostatic discharge protective device 200 and electrostatic discharge protective device 400 is put compared to traditional type electrostatic
The improvement of electric protective device 500.Percentage in table means thus percentage change, and means that electrostatic discharge protective fills " again "
The special properties for setting one of 200 and electrostatic discharge protective device 400 are the property of traditional type electrostatic discharge protective device 500
How many times of matter.For example, as shown in table 1, the trigger current of electrostatic discharge protective device 200 is higher than traditional type electrostatic discharge protective
About 3 times of the trigger current of device 500.The improvement of conducting resistance, trigger current and electricity area of safety operaton is also shown in figure
6A is into Fig. 8.Static discharge, which improves, means to provide the improvement of the efficiency of electrostatic discharge protective, that is, handles higher electrostatic and put
The improvement of piezoelectric voltage or the efficiency of biggish static discharge current.The efficiency of electrostatic discharge protective can be by simulating by human body
(people-body Model (human-body model, HBM)), machine (machine mould (machine model, MM)) or charging dress
One ESD gun of discharge measuring or utilization setting (charging-mounted cast (charged-device model, CDM)) and coming
(ESD gun) measurement.
Table 1 compares traditional type electrostatic discharge protective device and new-type electrostatic discharge protective device
Persons of ordinary skill in the technical field of the present invention consider in light of actual conditions disclosed herein specification and practical application
Afterwards, it clearly understood that the other embodiment of the present invention.Specification and example are only to as demonstration example, practical model of the invention
Farmland and spirit are subject to view as defined in claim.
Claims (20)
1. a kind of semiconductor device characterized by comprising
One substrate；
One first metal-oxide-semiconductor structure, is formed in the substrate, which includes:
One first drain region, a first passage area and one first source area are successively arranged along a first direction；
One drain electrode is formed on first drain region and is electrically coupled to first drain region；And
One body zone is formed under the first passage area and is electrically coupled to the first passage area；
One second metal-oxide-semiconductor structure, is formed in the substrate, the second metal-oxide semiconductor (MOS) body structure packet
One second drain region, a second channel area and one second source area are included, is successively arranged along a second direction, the second direction is not
It is same as the first direction；And
One bipolar junction structure, is formed in the substrate, which includes an emitter region, a base region and a collector
Area,
Wherein:
One first common semiconductor area is shared in first source area and second drain region in the substrate,
One second common semiconductor area is shared in the drain electrode and the base region in the substrate, and
The body zone and the collector region share a third common semiconductor area in the substrate.
2. a kind of semiconductor device characterized by comprising
One substrate；
One high-voltage metal oxide semiconductor (HV MOS) structure, is formed in the substrate, the high-voltage metal oxide semiconductor
Structure includes:
One first semiconductor region, has a first conductive type and one first doping level, which is high pressure gold
Belong to a drain region of oxide-semiconductor structure；
One second semiconductor region is formed on first semiconductor region, second semiconductor region have the first conductive type with
One second doping level, second doping level are higher than first doping level, which is the high-pressure metal oxygen
One drain electrode of compound semiconductor structure and the drain region for being electrically coupled to the high-voltage metal oxide semiconductor structure；
One third semiconductor region has a second conductive type, which includes the high-voltage metal oxide semiconductor
One channel region of structure；And
One the 4th semiconductor region, has the first conductive type, and the 4th semiconductor region is the high-voltage metal oxide semiconductor knot
The source region of structure,
Wherein:
First semiconductor region, the third semiconductor region and the 4th semiconductor region are successively arranged along a first direction；
One low pressure metal oxide semiconductor (LV MOS) structure, is formed in the substrate, the low pressure metal oxide semiconductor
Structure includes:
One the 5th semiconductor region, has the second conductive type, and the 5th semiconductor region is the low pressure metal oxide semiconductor
One channel region；And
One the 6th semiconductor region, has the first conductive type, and the 6th semiconductor region is the low pressure metal oxide semiconductor knot
The source region of structure,
Wherein:
4th semiconductor region is a drain region of the low pressure metal oxide-semiconductor structure, and
4th semiconductor region, the 5th semiconductor region and the 6th semiconductor region are successively arranged along a second direction, this second
Direction is different from the first direction；And
One bipolar junction structure, is formed in the substrate, which includes:
One the 7th semiconductor region is formed on first semiconductor region and is contacted with second semiconductor region, and the 7th half leads
Body area has the second conductive type and is an emitter region of the bipolar junction structure；And
One the 8th semiconductor region is formed under the third semiconductor region and has the second conductive type, the 8th semiconductor region
For a collector region of the bipolar junction structure；
Wherein second semiconductor region is a base region of the bipolar junction structure,
Wherein:
8th semiconductor region is also a body zone of the high-voltage metal oxide semiconductor structure, and
The third semiconductor region and the 8th semiconductor region are the multiple portions in the continuity trap with the second conductive type.
3. semiconductor device according to claim 2, wherein the second direction is perpendicular to the first direction.
4. semiconductor device according to claim 2, wherein the doping level of the 7th semiconductor region is higher than the third half
The doping level of conductor region.
5. semiconductor device according to claim 2, which is characterized in that further include:
One electrode district is formed in the 6th semiconductor region and is electrically coupled to the continuity trap,
Wherein:
The electrode district has the second conductive type, and the doping level of the electrode district is higher than the doping level of the continuity trap, and
The electrode district is an ontology of the high-voltage metal oxide semiconductor structure and the low pressure metal oxide-semiconductor structure
Area and be the bipolar junction structure a collector region.
6. semiconductor device according to claim 2, in which:
The high-voltage metal oxide semiconductor structure further include:
One first grid dielectric film is formed on the third semiconductor region；
One first gate electrode is formed on the first grid dielectric film, and the low pressure metal oxide-semiconductor structure is also
Including；
One second grid dielectric film, is formed on the 5th semiconductor region；And
One second grid electrode is formed on the second grid dielectric film.
7. semiconductor device according to claim 6, in which:
The first grid dielectric film and the second grid dielectric film are the multiple portions of a continuity insulating layer, continuity insulation
Layer is formed on the substrate, and
The first gate electrode and the second grid electrode are the multiple portions of a continuity polysilicon layer, the continuity polysilicon
Layer is formed on the continuity insulating layer.
8. semiconductor device according to claim 2, which is characterized in that further include:
One drain contact is formed on first semiconductor region；And
One source contact is formed on the 6th semiconductor region.
9. semiconductor device according to claim 8, wherein there is no contact holes to be formed on the 4th semiconductor region.
10. semiconductor device according to claim 2, wherein the 7th semiconductor region is contacted with first semiconductor region,
And second semiconductor region being directed around in the 7th semiconductor region with the surface that is parallel to the semiconductor device.
11. semiconductor device according to claim 2, in which:
The first conductive type is a N-type conductivity type, and
The second conductive type is a P-type conduction type.
12. semiconductor device according to claim 11, wherein
The substrate is a p-type substrate,
The semiconductor device further include:
One N shape trap (N-Well), is formed in the p-type substrate, and the doping level of the N shape trap is lower than first doping level,
Wherein the high-voltage metal oxide semiconductor structure, the low pressure metal oxide-semiconductor structure and the bipolar junction structure shape
At in the N shape trap.
13. semiconductor device according to claim 12, wherein the N shape trap includes the high-voltage metal oxide semiconductor knot
One drift region of structure, the drift region are formed between first semiconductor region and the third semiconductor region.
14. semiconductor device according to claim 12, wherein the doping level of the N shape trap is 1 × 1010/ cubic centimetre
To about 1 × 1016/ cubic centimetre.
15. semiconductor device according to claim 11,
Wherein first semiconductor region includes one first N-type trap, the semiconductor device further include:
One second N-type trap is formed in first N-type trap, the doping level of second N-type trap be higher than first doping level and
Lower than second doping level,
Wherein second semiconductor region and the 5th semiconductor region are formed in second N-type trap.
16. semiconductor device according to claim 2,
Wherein:
The high-voltage metal oxide semiconductor structure is one first high-voltage metal oxide semiconductor structure, and
The bipolar junction structure is one first bipolar junction structure,
The high-voltage metal oxide semiconductor structure further include:
One second high-voltage metal oxide semiconductor structure, is formed in the substrate, second high-voltage metal oxide semiconductor
Structure includes:
One the 9th semiconductor region with the second conductive type and is a channel of the second high-voltage metal oxide semiconductor structure
Area, and for the 4th semiconductor region, which arranges symmetrically to each other with the 9th semiconductor region；
The tenth semiconductor region with the first conductive type and is a drain electrode of the second high-voltage metal oxide semiconductor structure
Electrode, and for the 4th semiconductor region, which arranges symmetrically to each other with the tenth semiconductor region；With
And
The a tenth semiconductor area with the first conductive type and is a leakage of the second high-voltage metal oxide semiconductor structure
Polar region, and for the 4th semiconductor region, which arranges symmetrically to each other with the tenth semiconductor area,
Wherein the 4th semiconductor region is the source region of the second high-voltage metal oxide semiconductor structure；And
One second bipolar junction structure, is formed in the substrate, which includes:
The 12nd semiconductor region, is formed on the tenth semiconductor area and is contacted with the tenth semiconductor region, and for this
For 4th semiconductor region, the 12nd semiconductor region is to be symmetrically arranged in the 7th semiconductor region, the 12nd semiconductor
Area has the second conductive type and is an emitter region of the second bipolar junction structure, and
The 13rd semiconductor region is formed under the 9th semiconductor region and has the second conductive type, and the 13rd leads
Body area is a collector region of the second bipolar junction structure,
Wherein the tenth semiconductor region is a base region of the second bipolar junction structure,
Wherein:
13rd semiconductor region is also a body zone of the second high-voltage metal oxide semiconductor structure, and
9th semiconductor region and the 13rd semiconductor region are the multiple portions in the continuity trap.
17. semiconductor device according to claim 16, in which:
The first high-voltage metal oxide semiconductor structure further includes one first drift region, be formed in the substrate and between this
Between semiconductor area and the third semiconductor region, which has the first conductive type, and first drift region
Doping level is lower than first doping level, and
The second high-voltage metal oxide semiconductor structure further includes one second drift region, be formed in the substrate and between this
Between ten semiconductor areas and the 13rd semiconductor region, which has the first conductive type, and second drift
The doping level in area is lower than the doping level in the tenth semiconductor area.
18. semiconductor device according to claim 17, wherein first drift region and second drift region are with this
Multiple portions in one continuity trap of the first conductive type, the continuity trap with the first conductive type are formed in the substrate
In.
19. semiconductor device according to claim 16, in which:
The doping level of tenth semiconductor region is identical to second doping level, and
The doping level in the tenth semiconductor area is identical to first doping level.
20. a kind of semiconductor device characterized by comprising
One substrate；
One first trap, is formed in the substrate, which has a first conductive type and one first doping level；
One first heavily doped region is formed in first trap, which there is the first conductive type to mix with one second
Miscellaneous degree, second doping level are higher than first doping level；
One second trap, is formed in the substrate, which has a second conductive type and a third doping level；
One second heavily doped region is formed in second trap, which there is the first conductive type to mix with one the 4th
Miscellaneous degree, the 4th doping level are higher than first doping level；
One third heavily doped region is formed in first trap, which there is the second conductive type to mix with one the 5th
Miscellaneous degree, the 5th doping level are higher than the third doping level, which is contacted with first heavily doped region；
One the 4th heavily doped region is formed in second trap, and there is the 4th heavily doped region the first conductive type to mix with one the 6th
Miscellaneous degree, the 6th doping level are higher than first doping level,
Wherein；
Second trap includes:
One side is formed between first trap and second heavily doped region；And
One top is formed between second heavily doped region and the 4th heavily doped region,
First trap, the side and second heavily doped region are successively arranged along a first direction, and
Second heavily doped region, the top and the 4th heavily doped region are successively arranged along a second direction, and the second direction is not
It is same as the first direction.
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| KR100867574B1 (en) * | 2002-05-09 | 2008-11-10 | 페어차일드코리아반도체 주식회사 | Power device and method for manufacturing the same |
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