CN106158724A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN106158724A CN106158724A CN201510131248.6A CN201510131248A CN106158724A CN 106158724 A CN106158724 A CN 106158724A CN 201510131248 A CN201510131248 A CN 201510131248A CN 106158724 A CN106158724 A CN 106158724A
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- copper metal
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Abstract
The forming method of a kind of semiconductor structure, comprising: substrate is provided, is formed with metal plug in described substrate；Form copper metal layer on the substrate；Form hard mask layer on copper metal layer surface on described metal plug；With described hard mask layer as mask, halogen-free gas cluster ion beam etching technics is used to remove the copper metal layer of segment thickness；Continue with described hard mask layer as mask, use eutral particle beam etching technics to remove remaining copper metal layer, bottom hard mask layer, form the copper metal line being connected with metal plug.The method of the present invention, improves the contact area of copper metal line and metal plug.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly to the forming method of a kind of semiconductor structure.
Background technology
With the development of semiconductor technology, the chip integration of super large-scale integration has been up to several hundred million
Or even the scale of tens devices, multiple layer metal interconnection technique more than two-layer is extensively used.Pass
The metal interconnection of system is made up of aluminum metal, but device feature size is not in IC chip
Disconnected reducing, the current densities in metal interconnecting wires is continuously increased, it is desirable to response time constantly reduce, pass
The aluminum interconnecting of system can not meet requirement.With the continuous reduction of process, copper interconnection technology is
It has been substituted aluminium interconnection technique.Compared with aluminium, the lower electricity that can reduce interconnection line of resistivity of metallic copper
Resistance electric capacity (RC) postpones, and improves electromigration, improves device stability.
Fig. 1～Fig. 3 is the cross-sectional view of prior art copper interconnecting line forming method.
With reference to Fig. 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 is formed with first Jie
Matter layer 101, is formed with metal plug 102 in described first medium layer 101.
With reference to Fig. 2, described first medium layer 101 forms second dielectric layer 103；Etch described second
Dielectric layer 103, forms the opening 104 exposing metal plug surface in described second dielectric layer 103.
With reference to Fig. 3, form the copper metal line 105 filling full gate mouth, the bottom of described copper metal line 105 with
Metal plug 102 makes electrical contact with.
The copper metal line that prior art is formed still has much room for improvement with the contact performance of the metal plug of bottom.
Content of the invention
The problem that the present invention solves is in interconnection process, how to improve connecing of copper metal line and metal plug
Touch performance.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, comprising: provide
Substrate, is formed with metal plug in described substrate；Form copper metal layer on the substrate；At described gold
Belong to and on the copper metal layer surface on connector, form hard mask layer；With described hard mask layer as mask, use nothing
The gas cluster ion beam etching technics of halogen removes the copper metal layer of segment thickness；Continue firmly to cover with described
Film layer is mask, uses eutral particle beam etching technics to remove remaining copper metal layer, at the bottom of hard mask layer
Portion forms the copper metal line being connected with metal plug.
Optionally, the gas that described halogen-free gas cluster ion beam etching technics uses include oxygen and
Acetic acid gas.
Optionally, the chamber temp of described halogen-free gas cluster ion beam etching technics is less than 60 DEG C,
The pressure of acetic acid gas is 5.0E-4Pa～1.0E-02Pa, and voltage is 1KV～10KV, cluster ions bundle agent
Amount is 1E16～1E17ions/cm2。
Optionally, the thickness of described copper metal layer is 500～1000 angstroms.
Optionally, the thickness of the copper metal layer that described halogen-free gas cluster ion beam is removed when etching is
300～800 angstroms.
Optionally, the gas that eutral particle beam etching technics uses includes oxygen and alcohol gas.
Optionally, temperature during described eutral particle beam etching is less than-30 DEG C.
Optionally, the width of described copper metal line, is gradually increased from top to bottom.
The embodiment of the present invention additionally provides the forming method of a kind of semiconductor structure, comprising:
Substrate is provided, described substrate is formed with metal plug；
Form copper metal layer on the substrate；
Form hard mask layer on copper metal layer surface on described metal plug；
With described hard mask layer as mask, use halogen-free gas cluster ion beam etching technics removal portion
Divide the copper metal layer of thickness；
Continue with described hard mask layer as mask, use hydrogeneous plasma etching industrial to remove remaining copper gold
Belong to layer, bottom hard mask layer, form the copper metal line being connected with metal plug.
Optionally, the gas that described halogen-free gas cluster ion beam etching technics uses include oxygen and
Acetic acid gas.
Optionally, the chamber temp of described halogen-free gas cluster ion beam etching technics is less than 60 DEG C,
The pressure of acetic acid gas is 5.0E-4Pa～1.0E-02Pa, and voltage is 1KV～10KV, cluster ions bundle agent
Amount is 1E16～1E17ions/cm2。
Optionally, described hydrogeneous plasma etching industrial is pulsed plasma etching.
Optionally, the gas that hydrogeneous plasma etching industrial uses includes hydrogen, and the flow of hydrogen is
50～200sccm, dutycycle during pulsed plasma etching is 20%-90%, and pulse frequency is
0.1KHz～10KHz, chamber temp is 0～15 DEG C, and chamber pressure is 10～200mTorr, radio frequency source and partially
Putting source power is 100～500W.
Optionally, the thickness of described copper metal layer is 500～1000 angstroms.
Optionally, the thickness of the copper metal layer that described halogen-free gas cluster ion beam is removed when etching is
300～800 angstroms.
Optionally, described substrate includes Semiconductor substrate and the dielectric layer being positioned in Semiconductor substrate.
Optionally, it is additionally included in the substrate between the sidewall of copper metal line and adjacent copper metal line formation viscous
Attached layer；Adhesion layer forms ultra-low K dielectric layer.
Optionally, the width of described copper metal line, is gradually increased from top to bottom.
Compared with prior art, technical scheme has the advantage that
The forming method of the semiconductor structure of the present invention, after forming copper metal layer, successively uses in substrate
Halogen-free gas cluster ion beam etching technics and eutral particle beam etching technics etching copper metal level are formed
Copper metal line, owing to whole etching process does not has a halogen, thus prevents the etching of halogen to damage
Wound；When etching additionally, due to gas cluster ion beam etching technics, etching process relatively relaxes, thus formed
The sidewall profile of copper metal line is relatively preferable；In addition halogen-free gas cluster ion beam etching work is first used
Skill performs etching, and then uses eutral particle beam etching technics when performing etching, etching body be all neutral or
Uncharged, thus in etching process, etching ion residues will not be produced or etching injury (is i.e. being carved
Etch ion during erosion will not enter in copper metal line and metal plug)；In addition, copper metal line is by carving
Erosion is formed, thus the bottom width of the copper metal line being formed can be wider, improves copper metal line and bottom
The contact area of metal plug.
Further, the width of the described copper metal line of described formation, is gradually increased from top to bottom, because of
And copper metal line and the contact area of bottom metal connector are increased, improve the performance of device.
Further, the thickness of described copper metal layer is 500～1000 angstroms, described halogen-free cluster gas from
The thickness of the copper metal layer removed during son bundle etching is 300～800 angstroms, improves etching efficiency, reduces
The difficulty of subsequent etching processes.
The forming method of the semiconductor structure of the present invention, after forming copper metal layer, successively uses in substrate
Halogen-free gas cluster ion beam etching technics and hydrogeneous plasma etching industrial etching copper metal level are formed
Copper metal line, owing to whole etching process does not has a halogen, thus prevents the etching of halogen to damage
Wound；When etching additionally, due to gas cluster ion beam etching technics, etching process relatively relaxes, thus formed
The sidewall profile of copper metal line is relatively preferable；In addition halogen-free gas cluster ion beam etching work is first used
Skill performs etching, and then uses the remaining copper metal layer of hydrogeneous plasma etching industrial etching, can be well
The pattern of the copper metal line bottom control, and prevent from producing on substrate surface the residual of copper.
Brief description
Fig. 1～Fig. 3 is the cross-sectional view of prior art copper interconnecting line forming method；
Fig. 4～Fig. 7 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
Detailed description of the invention
As background technology is sayed, copper metal line still has much room for improvement with the contact performance of the metal plug of bottom.
Research discovery, prior art forms copper metal line and generally uses electroplating technology, i.e. present second medium
Form opening in Ceng, then use electroplating technology to fill copper in the opening and form copper metal line.But, with
The continuous reduction of characteristic size, when being patterned second dielectric layer, due to the limit of photoetching process
The position of the opening that system is formed easily produces skew, due to the restriction of etching technics, the end of the opening of formation
Portion's width can be less than the width at top, when forming copper metal line in opening, and copper metal line and bottom
The contact area of metal plug can reduce, and have impact on the electric property of the device of formation.
Further study show that, although deposition and etching technics can be used to form copper metal line, but adopt
With halogen (such as Cl2) etching copper when easily produce etching injury (such as plasma be to metallic copper
Damage), and the surface topography forming copper metal line is poor.
To this end, the invention provides the forming method of a kind of semiconductor structure, substrate forms copper metal
After Ceng, halogen-free gas cluster ion beam etching technics and eutral particle beam etching technics is successively used to carve
Erosion copper metal layer forms copper metal line, owing to whole etching process does not has halogen, thus prevents halogen
The etching injury of race's element；When etching additionally, due to gas cluster ion beam etching technics, etching process is more slow
With, thus the sidewall profile of the copper metal line being formed is relatively preferable；In addition halogen-free gas group is first used
Ion beam etching technics performs etching, and when then using eutral particle beam etching technics to perform etching, carves
Erosion body is all neutral or uncharged, thus in etching process, will not produce etching ion residues or quarter
Wound of deteriorating (i.e. etching ion in etching process will not enter in copper metal line and metal plug)；In addition,
Copper metal line is formed by etching, thus the bottom width of the copper metal line being formed can be wider, improves
The contact area of the metal plug of copper metal line and bottom.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.When describing the embodiment of the present invention in detail, for purposes of illustration only,
Schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not at this
Limit the scope of the invention.Additionally, the three of length, width and the degree of depth should be comprised in actual fabrication
Dimension space size.
Fig. 4～Fig. 7 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
With reference to Fig. 4, substrate is provided, described substrate is formed metal plug 202；Shape on the substrate
Become copper metal layer 203；Form hard mask layer on copper metal layer 203 surface on described metal plug 202
204。
Described substrate includes Semiconductor substrate 200 and the dielectric layer 201 being positioned in Semiconductor substrate 200.
Described Semiconductor substrate 200 is formed with semiconductor devices, such as transistor etc., described dielectric layer
Being formed with metal plug 202 in 201, described metal plug 202 electrically connects with corresponding semiconductor devices,
In one embodiment, described metal plug 202 can electrically connect with the grid of transistor, source electrode or drain electrode.
In other embodiments of the invention, described substrate can be for having the other kinds of of metal plug
Structure.
The material of described Semiconductor substrate 200 can for silicon (Si), germanium (Ge) or SiGe (GeSi),
Carborundum (SiC)；Also can be silicon-on-insulator (SOI), germanium on insulator (GOI)；Or also may be used
Think other material, such as GaAs etc. III-V compounds of group.Described Semiconductor substrate 300 is all right
Inject certain Doped ions according to design requirement to change electrical parameter.In described Semiconductor substrate 300
Inside being also formed with fleet plough groove isolation structure (not shown), described fleet plough groove isolation structure is for isolation not
Same transistor, prevents from being electrically connected between different crystal pipe, and the material of described fleet plough groove isolation structure can
Think silica, silicon nitride, silicon oxynitride therein one or more.
The material of described dielectric layer 201 is silica, silicon oxynitride, fluorine silica glass or other suitable materials
Material, described dielectric layer 201 can be single or multiple lift (>=2 layers) stacked structure.
Described copper metal layer 203 is subsequently used for forming the copper metal line electrically connecting with metal plug 202, institute
The formation process stating copper metal layer 203 is sputtering, in one embodiment, the thickness of described copper metal layer 203
Degree is 500～1000 angstroms.
After forming copper metal layer 203, copper metal layer 203 surface forms hard mask layer 204, described
Hard mask layer covers the copper metal layer 203 on metal plug 202 surface.
With reference to Fig. 5, with described hard mask layer 204 as mask, halogen-free gas cluster ion beam is used to carve
Etching technique removes the copper metal layer 203 of segment thickness.
The gas that described halogen-free gas cluster ion beam etching technics uses includes oxygen and acetic acid gas
Body.When using halogen-free gas cluster ion beam etching technics to perform etching, hard mask layer 204 both sides
Copper metal layer 203 in one layer of copper product on surface be oxidized to cupric oxide, simultaneous oxidation by oxygen cluster ions
Copper and acetic acid gas react formation byproduct of reaction, and byproduct of reaction is sent out by carrier of oxygen cluster ions bundle
The heat penetrated decomposes, thus realizes that gas cluster ion beam etching technics etching removes part copper, gas group
When ion beam etching technics performs etching, owing to etching process compares mitigation, the copper metal line of formation
Sidewall profile is preferable, and etching ion will not spread inside copper, thus etching process is to copper product
Damage very little.
In one embodiment, the chamber temp of described halogen-free gas cluster ion beam etching technics is less than
60 DEG C, can be-65 DEG C ,-70 DEG C ,-75 DEG C ,-80 DEG C ,-85 DEG C, the pressure of acetic acid gas is 5.0E-4
Pa～1.0E-02Pa, can be 4.0E-4Pa, 3.0E-4Pa, 1.0E-4Pa, 5.0E-3Pa, 8.0E-3Pa,
Voltage is 1KV～10KV, can be 2KV, 4KV, 6KV, 8KV, 9KV, cluster ions bundle agent
Amount is 1E16～1E17ions/cm2, 2E16ions/cm2、3E16ions/cm2、5E16ions/cm2、8E16
ions/cm2、9E16ions/cm2, under this etch process parameters, etch rate faster can be kept,
And the sidewall of the copper metal line being formed has higher surface topography, the copper metal line of formation is (from top
Be gradually reduced to bottom width) Sidewall angles be maintained between 60～80 degree.
In one embodiment, the copper metal layer that described halogen-free gas cluster ion beam is removed when etching
Thickness is 500～1000 angstroms, improves etching efficiency, reduces the difficulty of subsequent etching processes.
With reference to Fig. 6, with described hard mask layer as mask, eutral particle beam etching technics is used to remove remaining
Copper metal layer, forms the copper metal line 205 being connected with metal plug 202 bottom hard mask layer 204.
The gas that described eutral particle beam etching technics uses includes oxygen and alcohol gas.Eutral particle beam
When performing etching, copper and oxygen form cupric oxide, the first electron volts energy under the effect of the first ev energy
Amount is 12～50ev, can be 15ev, 20ev, 25ev, 30ev, 40ev, 50ev, cupric oxide and second
Alcohol forms ethanol epoxide copper compound under the effect of the second ev energy, and the second ev energy is
1～10ev, can be 1ev, 2ev, 5ev, 7ev, 8ev, 10ev.
Needing relatively low temperature during eutral particle beam etching, in one embodiment, described eutral particle beam is carved
Temperature during erosion is less than-30 DEG C, can be-32 DEG C ,-34 DEG C ,-36 DEG C ,-38 DEG C ,-39 DEG C ,-40 DEG C.
Use eutral particle beam etching technics when performing etching, etching body (oxygen and ethanol) be all neutral or
Uncharged, thus in etching process, etching ion residues will not be produced or etching injury (is i.e. being carved
Etch ion during erosion will not enter in copper metal line and metal plug).
The present invention is carved by successively using halogen-free gas cluster ion beam etching technics and eutral particle beam
The copper metal line 205 that etching technique is formed, the width of copper metal line 205, it is gradually increased from top to bottom,
Owing to the width bottom copper gold thread 205 is relatively wide, though the copper metal line 205 position generating unit being formed
Dividing skew, described copper metal line 205 is still bigger with the contact area of the metal plug 202 of bottom.
In another embodiment of the invention, halogen-free gas cluster ion beam etching technics is being used to carve
After etching off is except the copper metal layer of segment thickness, continue, with described hard mask layer 204 as mask, to use hydrogeneous
Plasma etching industrial removes remaining copper metal layer, is formed and metal plug bottom hard mask layer 204
202 copper metal lines 205 connecting.
Described hydrogeneous plasma etching industrial is pulsed plasma etching, and pulsed plasma etching can be very
The pattern of the good copper metal line bottom control, and prevent from producing on substrate surface the residual of copper, at a tool
In the embodiment of body, the gas that hydrogeneous plasma etching industrial uses includes hydrogen, and the flow of hydrogen is
50～200sccm, can be 60sccm, 80sccm, 100sccm, 150sccm, 180sccm, 190sccm,
Dutycycle during pulsed plasma etching is 20%-90%, can be the 30%th, the 40%th, the 50%th, the 60%th,
70%th, 80%, pulse frequency is 0.1KHz～10KHz, can for 0.5KHz, 1KHz, 3KHz,
5KHz, 8KHz, 9KHz, chamber temp is 0～15 DEG C, can be 3 DEG C, 7 DEG C, 8 DEG C, 10 DEG C,
12 DEG C, 14 DEG C, chamber pressure is 10～200mTorr, can for 30mTorr, 50mTorr, 70mTorr,
100mTorr, 120mTorr, 150mTorr, 190mTorr, radio frequency source and bias source power are 100～500W,
Can be, 120W, 150W, 180W, 200W, 250W, 300W, 350W, 450W so that
While the copper metal line being formed has higher surface topography, the copper metal line of formation is (from top the end of to
Portion's width is gradually reduced) Sidewall angles be maintained between 60～80 degree, can be 65 degree, 70 degree, 75
Degree, 78 degree.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (18)
1. the forming method of a semiconductor structure, it is characterised in that include:
Substrate is provided, described substrate is formed with metal plug；
Form copper metal layer on the substrate；
Form hard mask layer on copper metal layer surface on described metal plug；
With described hard mask layer as mask, use halogen-free gas cluster ion beam etching technics removal part
The copper metal layer of thickness；
Continue with described hard mask layer as mask, use eutral particle beam etching technics to remove remaining copper metal
Layer, forms the copper metal line being connected with metal plug bottom hard mask layer.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described halogen-free
The gas that gas cluster ion beam etching technics uses includes oxygen and acetic acid gas.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that described halogen-free
The chamber temp of gas cluster ion beam etching technics is less than 60 DEG C, and the pressure of acetic acid gas is 5.0E-4
Pa～1.0E-02Pa, voltage is 1KV～10KV, and cluster ions beam dose is 1E16～1E17
ions/cm2。
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described copper metal layer
Thickness be 500～1000 angstroms.
5. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that described halogen-free
The thickness of the copper metal layer removed during gas cluster ion beam etching is 300～800 angstroms.
6. the forming method of the semiconductor structure as described in claim 1 or 3, it is characterised in that neutral particle
The gas that bundle etching technics uses includes oxygen and alcohol gas.
7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that described neutral particle
Temperature during bundle etching is less than-30 DEG C.
8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that described copper metal line
Width, be gradually increased from top to bottom.
9. the forming method of a semiconductor structure, it is characterised in that include:
Substrate is provided, described substrate is formed with metal plug；
Form copper metal layer on the substrate；
Form hard mask layer on copper metal layer surface on described metal plug；
With described hard mask layer as mask, use halogen-free gas cluster ion beam etching technics removal part
The copper metal layer of thickness；
Continue with described hard mask layer as mask, use hydrogeneous plasma etching industrial to remove remaining copper metal
Layer, forms the copper metal line being connected with metal plug bottom hard mask layer.
10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that described halogen-free
The gas that gas cluster ion beam etching technics uses includes oxygen and acetic acid gas.
The forming method of 11. semiconductor structures as claimed in claim 10, it is characterised in that described halogen-free
The chamber temp of gas cluster ion beam etching technics is less than 60 DEG C, and the pressure of acetic acid gas is 5.0E-4
Pa～1.0E-02Pa, voltage is 1KV～10KV, and cluster ions beam dose is 1E16～1E17
ions/cm2。
The forming method of 12. semiconductor structures as claimed in claim 11, described hydrogeneous plasma etching industrial is
Pulsed plasma etching.
The forming method of 13. semiconductor structures as claimed in claim 12, it is characterised in that hydrogeneous plasma is carved
The gas that etching technique uses includes hydrogen, and the flow of hydrogen is 50～200sccm, and pulsed plasma is carved
Dutycycle during erosion is 20%-90%, and pulse frequency is 0.1KHz～10KHz, and chamber temp is 0～15
DEG C, chamber pressure is 10～200mTorr, and radio frequency source and bias source power are 100～500W.
The forming method of 14. semiconductor structures as claimed in claim 9, it is characterised in that described copper metal layer
Thickness be 500～1000 angstroms.
The forming method of 15. semiconductor structures as described in claim 9 or 14, it is characterised in that described Halogen
The thickness of the copper metal layer removed when the gas cluster ion beam of element etches is 300～800 angstroms.
The forming method of 16. semiconductor structures as claimed in claim 9, it is characterised in that described substrate includes
Semiconductor substrate and the dielectric layer being positioned in Semiconductor substrate.
The forming method of 17. semiconductor structures as claimed in claim 9, it is characterised in that be additionally included in copper gold
Belong to and in the substrate between the sidewall of line and adjacent copper metal line, form adhesion layer；Adhesion layer is formed super
Low K dielectric layer.
The forming method of 18. semiconductor structures as claimed in claim 13, it is characterised in that described copper metal line
Width, be gradually increased from top to bottom.
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| CN201510131248.6A CN106158724B (en) | 2015-03-24 | 2015-03-24 | The forming method of semiconductor structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109585290A (en) * | 2017-09-28 | 2019-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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|---|---|---|---|---|
| US5849641A (en) * | 1997-03-19 | 1998-12-15 | Lam Research Corporation | Methods and apparatus for etching a conductive layer to improve yield |
| US6054389A (en) * | 1997-12-29 | 2000-04-25 | Vanguard International Semiconductor Corporation | Method of forming metal conducting pillars |
| CN1359536A (en) * | 1998-07-08 | 2002-07-17 | 应用材料有限公司 | Method of forming metal interconnects |
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2015
- 2015-03-24 CN CN201510131248.6A patent/CN106158724B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5849641A (en) * | 1997-03-19 | 1998-12-15 | Lam Research Corporation | Methods and apparatus for etching a conductive layer to improve yield |
| US6054389A (en) * | 1997-12-29 | 2000-04-25 | Vanguard International Semiconductor Corporation | Method of forming metal conducting pillars |
| CN1359536A (en) * | 1998-07-08 | 2002-07-17 | 应用材料有限公司 | Method of forming metal interconnects |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109585290A (en) * | 2017-09-28 | 2019-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109585290B (en) * | 2017-09-28 | 2022-03-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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