CN106158724B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN106158724B CN106158724B CN201510131248.6A CN201510131248A CN106158724B CN 106158724 B CN106158724 B CN 106158724B CN 201510131248 A CN201510131248 A CN 201510131248A CN 106158724 B CN106158724 B CN 106158724B
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Abstract
A kind of forming method of semiconductor structure, comprising: substrate is provided, is formed with metal plug in the substrate；Copper metal layer is formed on the substrate；Hard mask layer is formed on the copper metal layer surface on the metal plug；Using the hard mask layer as exposure mask, using the copper metal layer of halogen-free gas cluster ion beam etching technics removal segment thickness；Continue using the hard mask layer as exposure mask, remaining copper metal layer is removed using eutral particle beam etching technics, forms the copper metal line connecting with metal plug in hard mask layer bottom.Method of the invention improves the contact area of copper metal line and metal plug.
Description
Technical field
The present invention relates to field of semiconductor fabrication, in particular to a kind of forming method of semiconductor structure.
Background technique
With the development of semiconductor technology, the chip integration of super large-scale integration has been up to several hundred million or even tens
The scale of hundred million devices, two layers or more of multiple layer metal interconnection technique be able to extensively using.Traditional metal interconnection is by aluminium gold
Made of category, but with the continuous reduction of device feature size in IC chip, the current densities in metal interconnecting wires are not
It is disconnected to increase, it is desirable that response time constantly reduce, traditional aluminum interconnecting is no longer satisfied requirement.Not with process
Disconnected to reduce, copper interconnection technology is instead of aluminium interconnection technique.Compared with aluminium, the resistivity of metallic copper is lower can to reduce interconnection
The resistance capacitance (RC) of line postpones, and improves electromigration, improves device stability.
FIG. 1 to FIG. 3 is the schematic diagram of the section structure of prior art copper interconnecting line forming method.
With reference to Fig. 1, semiconductor substrate 100 is provided, first medium layer 101, institute are formed in the semiconductor substrate 100
It states and is formed with metal plug 102 in first medium layer 101.
With reference to Fig. 2, second dielectric layer 103 is formed on the first medium layer 101；The second dielectric layer 103 is etched,
The opening 104 for exposing metal plug surface is formed in the second dielectric layer 103.
With reference to Fig. 3, the copper metal line 105 of filling full gate mouth, the bottom of the copper metal line 105 and metal plug are formed
102 electrical contacts.
The contact performance of the metal plug of copper metal line and bottom that the prior art is formed is still to be improved.
Summary of the invention
Problems solved by the invention is how to improve the contact performance of copper metal line and metal plug in interconnection process.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
Metal plug is formed in substrate；Copper metal layer is formed on the substrate；Copper metal layer surface on the metal plug
Upper formation hard mask layer；Using the hard mask layer as exposure mask, using halogen-free gas cluster ion beam etching technics removal portion
Divide the copper metal layer of thickness；Continue using the hard mask layer as exposure mask, remaining copper is removed using eutral particle beam etching technics
Metal layer forms the copper metal line connecting with metal plug in hard mask layer bottom.
Optionally, the gas that the halogen-free gas cluster ion beam etching technics uses includes oxygen and acetic acid gas
Body.
Optionally, the chamber temp of the halogen-free gas cluster ion beam etching technics is less than 60 DEG C, acetic acid gas
Pressure be 5.0E-4Pa~1.0E-02Pa, voltage be 1KV~10KV, cluster ions beam dose be 1E16~1E17ions/
cm2。
Optionally, the copper metal layer with a thickness of 500~1000 angstroms.
Optionally, the copper metal layer removed when the halogen-free gas cluster ion beam etching with a thickness of 300~800
Angstrom.
Optionally, the gas that eutral particle beam etching technics uses includes oxygen and alcohol gas.
Optionally, the temperature when eutral particle beam etches is less than -30 DEG C.
Optionally, the width of the copper metal line, is gradually increased from top to bottom.
The embodiment of the invention also provides a kind of forming methods of semiconductor structure, comprising:
Substrate is provided, is formed with metal plug in the substrate；
Copper metal layer is formed on the substrate；
Hard mask layer is formed on the copper metal layer surface on the metal plug；
Using the hard mask layer as exposure mask, using halogen-free gas cluster ion beam etching technics removal segment thickness
Copper metal layer；
Continue using the hard mask layer as exposure mask, remaining copper metal layer is removed using hydrogeneous plasma etching industrial,
The copper metal line connecting with metal plug is formed on hard mask layer bottom.
Optionally, the gas that the halogen-free gas cluster ion beam etching technics uses includes oxygen and acetic acid gas
Body.
Optionally, the chamber temp of the halogen-free gas cluster ion beam etching technics is less than 60 DEG C, acetic acid gas
Pressure be 5.0E-4Pa~1.0E-02Pa, voltage be 1KV~10KV, cluster ions beam dose be 1E16~1E17ions/
cm2。
Optionally, the hydrogeneous plasma etching industrial is pulsed plasma etching.
Optionally, the gas that hydrogeneous plasma etching industrial uses includes hydrogen, and the flow of hydrogen is 50~200sccm,
Duty ratio when pulsed plasma etching is 20%-90%, and pulse frequency is 0.1KHz~10KHz, and chamber temp is 0~15
DEG C, chamber pressure is 10~200mTorr, and radio frequency source and biasing source power are 100~500W.
Optionally, the copper metal layer with a thickness of 500~1000 angstroms.
Optionally, the copper metal layer removed when the halogen-free gas cluster ion beam etching with a thickness of 300~800
Angstrom.
Optionally, the substrate includes semiconductor substrate and the dielectric layer in semiconductor substrate.
It optionally, further include forming adhesion layer in substrate between the side wall and adjacent copper metal line of copper metal line；?
Ultra-low K dielectric layer is formed on adhesion layer.
Optionally, the width of the copper metal line, is gradually increased from top to bottom.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of semiconductor structure of the invention, after copper metal layer is formed on the substrate, successively using halogen-free
Gas cluster ion beam etching technics and eutral particle beam etching technics etching copper metal layer form copper metal line, due to entirely carving
Erosion process does not have halogen, thus prevents the etching injury of halogen；Work is etched additionally, due to gas cluster ion beam
Etching process relatively mitigates when skill etches, thus the sidewall profile of the copper metal line formed is relatively preferable；Furthermore first using halogen-free
Gas cluster ion beam etching technics perform etching, then using eutral particle beam etching technics perform etching when, etch body
It is all neutral or uncharged, thus in etching process, etching ion residues or etching injury will not be generated (i.e. etched
Ion is etched in journey to be entered in copper metal line and metal plug)；In addition, copper metal line is formed by etching, thus formed
The bottom width of copper metal line can be wider, improve the contact area of the metal plug of copper metal line and bottom.
Further, the width of the copper metal line of the formation, is gradually increased from top to bottom, so that copper is golden
The contact area for belonging to line and bottom metal plug increases, and improves the performance of device.
Further, the copper metal layer with a thickness of 500~1000 angstroms, the halogen-free gas cluster ion beam etching
When remove copper metal layer with a thickness of 300~800 angstroms, improve etching efficiency, reduce the difficulty of subsequent etching processes.
The forming method of semiconductor structure of the invention, after copper metal layer is formed on the substrate, successively using halogen-free
Gas cluster ion beam etching technics and hydrogeneous plasma etching industrial etching copper metal layer form copper metal line, due to entirely carving
Erosion process does not have halogen, thus prevents the etching injury of halogen；Work is etched additionally, due to gas cluster ion beam
Etching process relatively mitigates when skill etches, thus the sidewall profile of the copper metal line formed is relatively preferable；Furthermore first using halogen-free
Gas cluster ion beam etching technics perform etching, remaining copper metal is then etched using hydrogeneous plasma etching industrial
Layer, can control the pattern of the copper metal line of bottom well, and prevent the residual that copper is generated on substrate surface.
Detailed description of the invention
FIG. 1 to FIG. 3 is the schematic diagram of the section structure of prior art copper interconnecting line forming method；
Fig. 4~Fig. 7 is the schematic diagram of the section structure of the forming process of semiconductor structure of the embodiment of the present invention.
Specific embodiment
As described in the background art, the contact performance of copper metal line and the metal plug of bottom is still to be improved.
The study found that the prior art, which forms copper metal line, generallys use electroplating technology, i.e., formed in present second dielectric layer
Then opening fills copper using electroplating technology in the opening and forms copper metal line.However, with the continuous reduction of characteristic size,
When being patterned to second dielectric layer, since the position of the opening of the limitation formation of photoetching process is easy to produce offset, by
In the limitation of etching technics, the bottom width of the opening of formation can be less than the width at top, when the formation copper metal line in opening
When, the contact area of the metal plug of copper metal line and bottom can reduce, and affect the electric property for the device to be formed.
Further study show that although copper metal line can be formed using deposition and etching technics, using halogen family member
Element (such as Cl2) etching copper when be easy to produce etching injury (such as the damage of plasma to metallic copper), and form copper metal
The surface topography of line is poor.
For this purpose, the present invention provides a kind of forming methods of semiconductor structure, after copper metal layer is formed on the substrate, successively
Copper metal is formed using halogen-free gas cluster ion beam etching technics and eutral particle beam etching technics etching copper metal layer
Line since entire etching process does not have halogen, thus prevents the etching injury of halogen；Additionally, due to cluster gas
Etching process relatively mitigates when ion beam etch process etches, thus the sidewall profile of the copper metal line formed is relatively preferable；Furthermore
It is first performed etching using halogen-free gas cluster ion beam etching technics, is then carved using eutral particle beam etching technics
When erosion, etching body is all neutral or uncharged, thus in etching process, etching ion residues or etching injury will not be generated
(ion is etched i.e. in etching process to be entered in copper metal line and metal plug)；In addition, copper metal line passes through etching shape
At, thus the bottom width of the copper metal line formed can be wider, improves the contact of copper metal line with the metal plug of bottom
Area.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
It should include the three-dimensional space of length, width and depth in production.
Fig. 4~Fig. 7 is the schematic diagram of the section structure of the forming process of semiconductor structure of the embodiment of the present invention.
With reference to Fig. 4, substrate is provided, metal plug 202 is formed in the substrate；Copper metal layer is formed on the substrate
203；Hard mask layer 204 is formed on 203 surface of copper metal layer on the metal plug 202.
The substrate includes semiconductor substrate 200 and the dielectric layer 201 in semiconductor substrate 200.
It is formed with semiconductor devices, such as transistor etc. in the semiconductor substrate 200, is formed in the dielectric layer 201
There is metal plug 202, the metal plug 202 is electrically connected with corresponding semiconductor devices, and in one embodiment, the metal is inserted
Plug 202 can be electrically connected with the grid of transistor, source electrode or drain electrode.
In other embodiments of the invention, the substrate can be the other kinds of structure with metal plug.
The material of the semiconductor substrate 200 can be silicon (Si), germanium (Ge) or SiGe (GeSi), silicon carbide (SiC)；
It is also possible to silicon-on-insulator (SOI), germanium on insulator (GOI)；Or can also be for other materials, such as GaAs etc.
III-V compounds of group.The semiconductor substrate 300 can also inject certain Doped ions according to design requirement to change electricity
Parameter.Fleet plough groove isolation structure (not shown), the shallow trench isolation knot are also formed in the semiconductor substrate 300
Structure prevents from being electrically connected between different crystal pipe, the material of the fleet plough groove isolation structure can for different transistors to be isolated
Think that silica, silicon nitride, silicon oxynitride are one such or several.
The material of the dielectric layer 201 is silica, silicon oxynitride, fluorine silica glass or other suitable materials, is given an account of
Matter layer 201 can be single-layer or multi-layer (>=2 layers) stacked structure.
The copper metal layer 203 is subsequently used for forming the copper metal line being electrically connected with metal plug 202, the copper metal layer
203 formation process be sputtering, in one embodiment, the copper metal layer 203 with a thickness of 500~1000 angstroms.
After forming copper metal layer 203, hard mask layer 204 is formed on 203 surface of copper metal layer, the hard mask layer covers
Copper metal layer 203 on 202 surface of lid metal plug.
It is exposure mask with the hard mask layer 204 with reference to Fig. 5, is gone using halogen-free gas cluster ion beam etching technics
Except the copper metal layer 203 of segment thickness.
The gas that the halogen-free gas cluster ion beam etching technics uses includes oxygen and acetic acid gas.Using nothing
When the gas cluster ion beam etching technics of halogen performs etching, the one of surface in the copper metal layer 203 of 204 two sides of hard mask layer
Layer copper product is oxidized to copper oxide by oxygen cluster ions, and simultaneous oxidation copper and acetic acid gas react to form byproduct of reaction,
The heat that byproduct of reaction is emitted by carrier of oxygen cluster ions beam decomposes, to realize that gas cluster ion beam etching technics etches
Part copper is removed, when gas cluster ion beam etching technics performs etching, since etching process compares mitigation, the copper metal of formation
The sidewall profile of line is preferable, and etching ion will not be spread to inside copper, thus etching process to the damage of copper product very
It is small.
In one embodiment, the chamber temp of the halogen-free gas cluster ion beam etching technics, can less than 60 DEG C
Think -65 DEG C, -70 DEG C, -75 DEG C, -80 DEG C, -85 DEG C, the pressure of acetic acid gas is 5.0E-4Pa~1.0E-02Pa, Ke Yiwei
4.0E-4Pa, 3.0E-4Pa, 1.0E-4Pa, 5.0E-3Pa, 8.0E-3Pa, voltage be 1KV~10KV, can for 2KV, 4KV,
6KV, 8KV, 9KV, cluster ions beam dose is 1E16~1E17ions/cm2, 2E16ions/cm2、3E16ions/cm2、
5E16ions/cm2、8E16ions/cm2、9E16ions/cm2, under the etch process parameters, can keep etching speed faster
Rate, and the side wall surface topography with higher of the copper metal line formed, the copper metal line of formation is (from top to bottom width
Be gradually reduced) Sidewall angles be maintained between 60~80 degree.
In one embodiment, the copper metal layer removed when the halogen-free gas cluster ion beam etching with a thickness of
500~1000 angstroms, etching efficiency is improved, reduces the difficulty of subsequent etching processes.
With reference to Fig. 6, using the hard mask layer as exposure mask, remaining copper metal is removed using eutral particle beam etching technics
Layer forms the copper metal line 205 connecting with metal plug 202 in 204 bottom of hard mask layer.
The gas that the eutral particle beam etching technics uses includes oxygen and alcohol gas.Eutral particle beam performs etching
When, copper and oxygen form copper oxide under the action of the first ev energy, and the first ev energy is 12~50ev, Ke Yiwei
15ev, 20ev, 25ev, 30ev, 40ev, 50ev, copper oxide and ethyl alcohol form ethyl alcohol oxygen under the action of the second ev energy
Base copper compound, the second ev energy are 1~10ev, can be 1ev, 2ev, 5ev, 7ev, 8ev, 10ev.
Eutral particle beam needs lower temperature when etching, in one embodiment, the temperature when eutral particle beam etches
Degree is less than -30 DEG C, can be -32 DEG C, -34 DEG C, -36 DEG C, -38 DEG C, -39 DEG C, -40 DEG C.
When being performed etching using eutral particle beam etching technics, etching body (oxygen and ethyl alcohol) is all neutrality or uncharged,
Thus in etching process, will not generating etching ion residues or etching injury, (etching ion i.e. in etching process will not be into
Enter in copper metal line and metal plug).
The present invention is by successively using halogen-free gas cluster ion beam etching technics and eutral particle beam etching technics
The copper metal line 205 of formation, the width of copper metal line 205 are gradually increased from top to bottom, due to 205 bottom of copper gold thread
Width is relatively wide, even if partial offset, the gold of the copper metal line 205 and bottom occur for 205 position of copper metal line formed
The contact area for belonging to plug 202 is still larger.
In another embodiment of the invention, removal portion is being etched using halogen-free gas cluster ion beam etching technics
After dividing the copper metal layer of thickness, continue with the hard mask layer 204 to be exposure mask, be removed using hydrogeneous plasma etching industrial remaining
Copper metal layer, form the copper metal line 205 that connect with metal plug 202 in 204 bottom of hard mask layer.
The hydrogeneous plasma etching industrial is pulsed plasma etching, and pulsed plasma etching can control well
The pattern of the copper metal line of bottom, and prevent the residual that copper is generated on substrate surface, in a specific embodiment, it is hydrogeneous it is equal from
The gas that sub- etching technics uses includes hydrogen, and the flow of hydrogen is 50~200sccm, can for 60sccm, 80sccm,
100sccm, 150sccm, 180sccm, 190sccm, duty ratio when pulsed plasma etching are 20%-90%, Ke Yiwei
30%, 40%, 50%, 60%, 70%, 80%, pulse frequency be 0.1KHz~10KHz, can for 0.5KHz, 1KHz, 3KHz,
5KHz, 8KHz, 9KHz, chamber temp be 0~15 DEG C, can for 3 DEG C, 7 DEG C, 8 DEG C, 10 DEG C, 12 DEG C, 14 DEG C, chamber pressure is
10~200mTorr, can for 30mTorr, 50mTorr, 70mTorr, 100mTorr, 120mTorr, 150mTorr,
190mTorr, radio frequency source and biasing source power be 100~500W, Ke Yiwei, 120W, 150W, 180W, 200W, 250W, 300W,
350W, 450W so that formed copper metal line surface topography with higher while, formation copper metal line (from top to
Bottom width is gradually reduced) Sidewall angles be maintained between 60~80 degree, can be 65 degree, 70 degree, 75 degree, 78 degree.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (16)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, is formed with metal plug in the substrate；
Copper metal layer is formed on the substrate；
Hard mask layer is formed on the copper metal layer surface on the metal plug；
Using the hard mask layer as exposure mask, using the copper gold of halogen-free gas cluster ion beam etching technics removal segment thickness
Belong to layer, the gas that the halogen-free gas cluster ion beam etching technics uses includes oxygen and acetic acid gas；
Continue using the hard mask layer as exposure mask, remaining copper metal layer is removed using eutral particle beam etching technics, is being covered firmly
The copper metal line connecting with metal plug is formed on film layer bottom, and the gas that eutral particle beam etching technics uses includes oxygen and second
Alcohol gas.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the halogen-free cluster gas from
For the chamber temp of beamlet etching technics less than 60 DEG C, the pressure of acetic acid gas is 5.0E-4Pa~1.0E-02Pa, voltage 1KV
~10KV, cluster ions beam dose are 1E16~1E17ions/cm2。
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the copper metal layer with a thickness of
500~1000 angstroms.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the halogen-free cluster gas from
Beamlet etch when remove copper metal layer with a thickness of 300~800 angstroms.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that when the eutral particle beam etches
Temperature is less than -30 DEG C.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the width of the copper metal line, from
Top is gradually increased to bottom.
7. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, is formed with metal plug in the substrate；
Copper metal layer is formed on the substrate；
Hard mask layer is formed on the copper metal layer surface on the metal plug；
Using the hard mask layer as exposure mask, using the copper gold of halogen-free gas cluster ion beam etching technics removal segment thickness
Belong to layer；
Continue using the hard mask layer as exposure mask, remaining copper metal layer is removed using hydrogeneous plasma etching industrial, is being covered firmly
The copper metal line connecting with metal plug is formed on film layer bottom.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the halogen-free cluster gas from
The gas that beamlet etching technics uses includes oxygen and acetic acid gas.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the halogen-free cluster gas from
For the chamber temp of beamlet etching technics less than 60 DEG C, the pressure of acetic acid gas is 5.0E-4Pa~1.0E-02Pa, voltage 1KV
~10KV, cluster ions beam dose are 1E16~1E17ions/cm2。
10. the forming method of semiconductor structure as claimed in claim 9, the hydrogeneous plasma etching industrial is pulsed etc.
Ion etching.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that hydrogeneous plasma etching industrial is adopted
Gas includes hydrogen, and the flow of hydrogen is 50~200sccm, and duty ratio when pulsed plasma etching is 20%-
90%, pulse frequency is 0.1KHz~10KHz, and chamber temp is 0~15 DEG C, and chamber pressure is 10~200mTorr, radio frequency source
It is 100~500W with biasing source power.
12. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the copper metal layer with a thickness of
500~1000 angstroms.
13. the forming method of the semiconductor structure as described in claim 7 or 12, which is characterized in that the halogen-free gas
Cluster ions beam etch when remove copper metal layer with a thickness of 300~800 angstroms.
14. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the substrate includes semiconductor lining
Bottom and the dielectric layer in semiconductor substrate.
15. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that further include in the side of copper metal line
Adhesion layer is formed in substrate between wall and adjacent copper metal line；Ultra-low K dielectric layer is formed on adhesion layer.
16. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the width of the copper metal line,
It is gradually increased from top to bottom.
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| CN201510131248.6A CN106158724B (en) | 2015-03-24 | 2015-03-24 | The forming method of semiconductor structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5849641A (en) * | 1997-03-19 | 1998-12-15 | Lam Research Corporation | Methods and apparatus for etching a conductive layer to improve yield |
| US6054389A (en) * | 1997-12-29 | 2000-04-25 | Vanguard International Semiconductor Corporation | Method of forming metal conducting pillars |
| CN1359536A (en) * | 1998-07-08 | 2002-07-17 | 应用材料有限公司 | Method of forming metal interconnects |
-
2015
- 2015-03-24 CN CN201510131248.6A patent/CN106158724B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5849641A (en) * | 1997-03-19 | 1998-12-15 | Lam Research Corporation | Methods and apparatus for etching a conductive layer to improve yield |
| US6054389A (en) * | 1997-12-29 | 2000-04-25 | Vanguard International Semiconductor Corporation | Method of forming metal conducting pillars |
| CN1359536A (en) * | 1998-07-08 | 2002-07-17 | 应用材料有限公司 | Method of forming metal interconnects |
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