CN106155161A

CN106155161A - High efficiency low pressure difference linear voltage regulator

Info

Publication number: CN106155161A
Application number: CN201510207855.6A
Authority: CN
Inventors: 陈俊嘉; 陈昭安; 许健丰; 张凯斐
Original assignee: MStar Semiconductor Inc Taiwan
Current assignee: MediaTek Inc
Priority date: 2015-04-28
Filing date: 2015-04-28
Publication date: 2016-11-23
Anticipated expiration: 2035-04-28
Also published as: CN106155161B

Abstract

The present invention relates to a kind of high efficiency low pressure difference linear voltage regulator, in order to receive an input voltage from an input power cord and to export an output voltage in an out-put supply line.This low pressure difference linear voltage regulator includes one first active member and one second active member, an operational amplifier and a protection circuit.This first active member and this second active member, all have a withstanding voltage.This first active member is connected end with this second active member through one, is series between this input power cord and this out-put supply line.This operational amplifier is connected to a control end of this second active member, controls this second active member according to a core power supply voltage of this output voltage and a core power line, so that this output voltage stabilization is in a target voltage values.This protection circuit is connected to a control end of this input power cord, this out-put supply line, this connection end and this first active member, according to this input voltage and this output voltage, controls the voltage of this connection end and this control end of this first active member.

Description

High efficiency low pressure difference linear voltage regulator

Technical field

The present invention is related to a low pressure difference linear voltage regulator (Low Drop-Out Regulator, LDO), and espespecially one Kind of high efficiency, use the transistor LDO as driving stage (driving stage) of low withstanding voltage.

Background technology

IC interior generally requires and is designed with the power line with different voltage, for example, one integrated The inside of circuit, can be designed with core power line DVDD, 1.5V of power line AVDD3P3,1.0V of 3.3V The seasonal pulse tree power line AVDDTREE of import and export power line AVDD1P5,1.0V etc..One integrated circuit May only accept the power supply supply of extraneous one or two fixed voltage, and other have the power supply of different voltage Line, then be the conversion provided through IC interior power supply changeover device, stablizes the power supply of each power line Voltage.LDO is the one of power supply changeover device, because its framework is simple, so widely IC design circle institute is wide General employing.Although supply voltage is identical, core power line DVDD and seasonal pulse tree power line AVDDTREE will not Short cut with each other, and be mutually isolated, it is to avoid produced noise on a power line, have influence on by another power line The operation of the circuit powered.

In integrated circuit, in order at different electrical power electricity pressing operation, also be provided with and can bear different tolerance voltage Transistor.The withstanding voltage of one transistor represents the maximum that the cross-pressure between the every two-end-point of this transistor can bear Value, as long as the cross-pressure between the every two-end-point of this transistor is less than this withstanding voltage, this transistor just has enough Reliability.For example, integrated circuit has a core circuit, and it is mainly used in logical operations, includes core unit Part, such as core nmos pass transistor and core PMOS transistor.In order to reach high arithmetic speed and low power consuming, Core circuit is powered by the core power line DVDD of 1.0V, and the withstanding voltage of core parts only has 1V.Integrated Circuit can also have output/input circuit, includes import and export element, such as import and export nmos pass transistor and import and export PMOS transistor.Import and export element is in order to there be the ability of higher anti-extraneous high-voltage signal, so its withstanding voltage 1.5V may be up to, it is possible to powered by the import and export power line AVDD1P5 of 1.5V.It is said that in general, tolerance The element that voltage is the highest, will reach certain current driving capability, the silicon area (silicon area) shared by its circuit The biggest, cost is the highest.In this description, import and export element is exemplified as respectively with the withstanding voltage of core parts 1.5V and 1V.But the invention is not restricted to this, as long as the withstanding voltage of import and export element is more than the tolerance of core parts Voltage is the most permissible.

Figure 1A is LDO 10 known to, its import and export element NMOS crystal using withstanding voltage to be 3.3V Pipe MN_3P3, as driving stage.LDO 10 using the power line AVDD3P3 of 3.3V as primary input power line, On out-put supply line LDO_OUT, it is desirable to produce the voltage of stable 1.0V.Out-put supply line LDO_OUT Can be as seasonal pulse tree power line AVDDTREE, to meeting double data rate (double data rate, DDR) Seasonal pulse tree (clock tree) power supply needed for the output/input circuit of agreement.LDO 10 has a shortcoming the biggest: power consumption. When normal operating, nmos pass transistor MN_3P3 itself can consume suitable electric energy, because when stable state, its Drain-source cross-pressure (V_DS) up to 2V, the electric energy itself expended will be the output electric current product with 2V of LDO 10, non- Often waste.

Figure 1B is LDO 20 known to another.The import and export power line that primary input power line is 1.5V of LDO 20 AVDD1P5, driving stage uses the nmos pass transistor MN_1P5 belonging to an import and export element.LDO 20 compares LDO 10 power savings, because the V of nmos pass transistor MN_1P5_DSOnly 0.5V.Simply, the lowest V_DS, NMOS Transistor MN_1P5 to reach sufficiently high driving electric current, no matter at silicon area and PSRR (power Supply rejection ratio, PSRR) consider, all it is difficult to.

Summary of the invention

Embodiment discloses has a kind of low pressure difference linear voltage regulator, in order to receive an input voltage from an input power cord And export an output voltage in an out-put supply line.This low pressure difference linear voltage regulator include one first active member with And one second active member, an operational amplifier and a protection circuit.This first active member and this second Active member, all has a withstanding voltage.This first active member is connected end with this second active member through one, It is series between this input power cord and this out-put supply line.This operational amplifier is connected to this second active member A control end, control this second actively according to a core power supply voltage of this output voltage and a core power line Element, so that this output voltage stabilization is in a target voltage values.This protection circuit is connected to this input power cord, is somebody's turn to do One control end of out-put supply line, this connection end and this first active member, according to this input voltage and this is defeated Go out voltage, control the voltage of this connection end and this control end of this first active member.

Embodiment discloses has a kind of voltage conversion method, for a low pressure difference linear voltage regulator from an input power cord Receive an input voltage and export an output voltage in an out-put supply line.This low pressure difference linear voltage regulator comprises one One active member, one second active member and an operational amplifier.This first active member and this second active element Part is series between this input power cord and this out-put supply line through a connection end.This first and second active element Part all has a withstanding voltage.This operational amplifier is connected to a control end of this second active member.This voltage turns The method of changing comprises: control this second active according to a core power supply voltage of this output voltage and a core power line Element, so that this output voltage stabilization is in a target voltage values；And, according to this input voltage and this output voltage Control the voltage of this connection end and this control end of this first active member.

Accompanying drawing explanation

Figure 1A is LDO known to.

Figure 1B is LDO known to another.

Fig. 1 C is an imaginary LDO.

Fig. 2 shows the LDO implemented according to the present invention.

Fig. 3 shows some signal waveforms in Fig. 2.

Fig. 4 denotes especially before time point t1, some element states of element in Fig. 2.

Fig. 5 denotes especially between time point t1 to t2, some element states of element in Fig. 2.

Fig. 6 denotes especially after time point t2, some element states of element in Fig. 2.

Fig. 7 Yu Fig. 8 is another two LDO implemented according to the present invention.

Symbol description

10:LDO

12: operational amplifier

20:LDO

25:LDO

30:LDO

32: protection circuit

34: comparator

36: or lock

38: multiplexer

40: bleeder circuit

50:LDO

52: protection circuit

54: bleeder circuit

60:LDO

62: operational amplifier

AVDD1P5: import and export power line

AVDD3P3: power line

DVDD: core power line

LDO_OUT: out-put supply line

MN_1P5:NMOS transistor

MN_3P3:NMOS transistor

MN_CORE:NMOS transistor

MN1_CORE:NMOS transistor

MN2_CORE:NMOS transistor

MP_CORE:PMOS transistor

MP2_CORE:PMOS transistor

MP1:PMOS transistor

MP2:PMOS transistor

PG: power good signal

PROT_D: connect end

PROT_G: gate terminal

S1P0, S0P5, S2P2: dividing potential drop end

T0, t1, t2: time point

VG: gate terminal

V_REF: preset security value

Detailed description of the invention

Fig. 1 C is an imaginary LDO 25.Driving stage compared to Figure 1B, LDO 25 changes employing and belongs to core unit One nmos pass transistor MN1_CORE of part.Unfortunately, LDO 25 has reliability issues.For example, In one electric sequence (power sequence) design, the import and export power line AVDD1P5 in Fig. 1 C is main defeated as one Entering power line, after main power voltage thereon may arrive 1.5V, operational amplifier 12 just starts to draw high from 0V The grid of nmos pass transistor MN1_CORE, and the output voltage on out-put supply line LDO_OUT is the most at leisure From 0V, the 1.0V toward target voltage values is close.It has been discovered that the drain-gate of nmos pass transistor MN1_CORE Cross-pressure (V_DG) and drain-source cross-pressure (V_DS), maximum is about 1.5V, exceedes nmos pass transistor MN1_CORE's Withstanding voltage (1V).So, the nmos pass transistor MN1_CORE in LDO 25 is because too high cross-pressure, real Border has reliability issues on using.

Fig. 2 shows the LDO 30 implemented according to the present invention.The driving stage of LDO 30 has a PMOS transistor MP_CORE (a first active member) and nmos pass transistor MN_CORE (the second active member), both It is belonging to core parts.PMOS transistor and nmos pass transistor are all some embodiments of active member, and this Invention is not limited to this.For example, in other embodiments, active member can be vacuum tube device, field effect crystalline substance Body pipe (field effect transistor, FET), bipolarity junction transistor (Bipolar Junction Transistor, BJT) etc..Import and export power line AVDD1P5, as a primary input power line, is connected to PMOS transistor The source electrode of MP_CORE.When stable state, the supply voltage of import and export power line AVDD1P5 is 1.5V.Output electricity Source line LDO_OUT is connected to the source electrode of nmos pass transistor MN_CORE.PMOS transistor MP_CORE with The drain electrode of nmos pass transistor MN_CORE, is all connected to connect end PROT_D.As shown in Figure 2, PMOS Transistor MP_CORE and nmos pass transistor MN_CORE is series at import and export power line AVDD1P5 with defeated Go out between power line LDO_OUT.PMOS transistor MP_CORE has gate terminal PROT_G, and NMOS is brilliant Body pipe MN_CORE has gate terminal VG.

Operational amplifier 12 is powered by the power line AVDD3P3 of 3.3V, has two inputs and is connected respectively to core Heart power line DVDD and out-put supply line LDO_OUT.The output of operational amplifier 12 is connected to gate terminal VG.When stable state, the supply voltage of core power line DVDD is 1.0V, so during stable state, out-put supply line Output voltage on LDO_OUT is also 1.0V (target voltage values).

LDO 30 has additionally comprised a protection circuit 32, and it is coupled to out-put supply line LDO_OUT, core power Line DVDD and import and export power line AVDD1P5.The extreme PROT_G of protection circuit 32 control gate be connected end PROT_D.In an electric sequence, protection circuit 32 may insure that PMOS transistor MP_CORE and NMOS The cross-pressure at any two ends, such as V on transistor MN_CORE_DS、V_GD、V_GSDeng, no more than core parts Withstanding voltage (1V).So protection circuit 32 guarantees PMOS transistor MP_CORE and nmos pass transistor MN_CORE is all without there being reliability issues.

Protection circuit 32 has a bleeder circuit 40, is connected to import and export power line AVDD1P5 and an earthing power supply Between line.Bleeder circuit 40 has three resistance, is connected with dividing potential drop end S1P0 with S0P5.In one embodiment, The resistance of three resistance the most all as.When stable state, the main power voltage of import and export power line AVDD1P5 is big Being about 1.5V, the voltage of dividing potential drop end S1P0 Yu S0P5 is 1V and 0.5V the most respectively.

PMOS transistor MP1 (the 3rd active member) is connected to dividing potential drop end S1P0 and is connected between end PROT_D, PMOS transistor MP2 (the 4th active member) is connected to core power line DVDD and is connected between end PROT_D. In one embodiment, PMOS transistor MP1 and MP2 are core parts.In another embodiment, PMOS Transistor MP1 Yu MP2 is import and export element.

Comparator 34 compares preset security value V_REFOutput voltage with out-put supply line LDO_OUT.Real at this Execute in example, preset security value V_REFFor 0.5V, less than the out-put supply line LDO_OUT target voltage when stable state Value (1.0V).

Multiplexer 38 have two inputs be respectively connecting to dividing potential drop end S0P5 and import and export power line AVDD1P5 and One output is connected to gate terminal PROT_G of PMOS transistor MP_CORE.As can be known from Fig. 2, when output electricity When the output voltage of source line LDO_OUT is less than 0.5V, multiplexer 38 connects import and export power line AVDD1P5 to grid Extreme PROT_G；Otherwise, when the output voltage of out-put supply line LDO_OUT is more than 0.5V, multiplexer 38 Connect dividing potential drop end S0P5 to gate terminal PROT_G.

PMOS transistor MP1 with or lock 36 receive have reverse power good signal PG, its logical value regard core Depending on the core power supply voltage of power line DVDD.For example, when core power supply voltage is more than a 0.9V (core Normal value), core power supply voltage can be considered as and reached the 1V of stable state, so power good signal PG becomes In logic " 1 ", voltage potential is a high-voltage value.Otherwise, when core power supply voltage is less than 0.9V, power supply is just Regular signal PG is in logic " 0 ", voltage potential is a low voltage value.For core parts, high-voltage value For 1V, for import and export element, high-voltage value is 1.5V.

Fig. 3 shows some signal waveforms in Fig. 2, from top to bottom, is import and export power line AVDD1P5 respectively Main power voltage, the core power supply voltage of core power line DVDD, the logical value of power good signal PG, company Connect the voltage of end PROT_D, connect the voltage of end PROT_G, the voltage of gate terminal VG and out-put supply line The output voltage of LDO_OUT.In Fig. 3, it is assumed that electric sequence (power sequence) is import and export power line AVDD1P5 powers at first, is followed by core power line DVDD, followed by out-put supply line LDO_OUT.

Referring to Fig. 3 and Fig. 4.Fig. 4 denotes especially before time point t1, some elements of element in Fig. 2 State, includes the unlatching of PMOS transistor MP1, the closedown of PMOS transistor MP2, PMOS transistor MP_CORE closes, nmos pass transistor MN_CORE closes and multiplexer 38 is connected to import and export power line AVDD1P5 and gate terminal PROT_G.

When LDO 30 powers at the beginning, the main power voltage of import and export power line AVDD1P5 starts to climb from 0V, 1.5V when time point t0 reaches stable state.The voltage of dividing potential drop end S1P0 Yu S0P5 is the 2/3 of main power voltage respectively With 1/3, so climbing together as well as main power voltage, respectively reach 1V and 0.5V of stable state at time point t0. Before time point t1, the output voltage of out-put supply line LDO_OUT is about 0V, and comparator 34 exports logic Value " 0 ", control multiplexer 38 so that it is be connected to import and export power line AVDD1P5 and gate terminal PROT_G, So PMOS transistor MP_CORE is closed.Before time point t1, because the core power of core power line DVDD Voltage is the most on the low side, so power good signal PG is in logic " 0 ", PMOS transistor MP1 is opened, and will divide Pressure side S1P0 is with to be connected end PROT_D phase short-circuit.Therefore, before time point t1, connect the company of end PROT_D Connect voltage and will follow the voltage of dividing potential drop end S1P0, climb and rest on 1V, as shown in Figure 3.Additionally, logical value For " 0 " power good signal PG and the logical value of comparator 34 output " 0 " also result in or lock 36 exports logic Value " 1 ", so PMOS transistor MP2 is closed.As shown in Figure 3, before time point t1, gate terminal VG is about It is all 0V, so nmos pass transistor MN_CORE closes.

Referring to Fig. 3 and Fig. 5.Fig. 5 denotes especially between time point t1 to t2, in Fig. 2 element some Element state, includes the closedown of PMOS transistor MP1, the unlatching of PMOS transistor MP2, PMOS transistor MP_CORE closes, nmos pass transistor MN_CORE opens and multiplexer 38 is connected to import and export power line AVDD1P5 and gate terminal PROT_G.

At time point t1, the core power supply voltage of core power line DVDD almost stabilizes, power good signal PG transition is in logic " 1 ".So, PMOS transistor MP1 is closed, PMOS transistor MP2 is opened, dimension Hold and connect the connection voltage of end PROT_D in the 1V of core power line DVDD.After time point t1, computing is put Big device 12 voltage drawing high gate terminal VG slowly, subsequently results in nmos pass transistor MN_CORE and opens, also Draw high the output voltage of out-put supply line LDO_OUT, as shown in Figure 3.Out-put supply line LDO_OUT's Output voltage reaches 0.5V (preset security value V at time point t2_REF)。

Referring to Fig. 3 and Fig. 6.Fig. 6 denotes especially after time point t2, some elements of element in Fig. 2 State, includes the closedown of PMOS transistor MP1, the closedown of PMOS transistor MP2, PMOS transistor MP_CORE open, nmos pass transistor MN_CORE open and multiplexer 38 be connected to dividing potential drop end S0P5 with Gate terminal PROT_G.

After time point t2, the output voltage of out-put supply line LDO_OUT has exceeded 0.5V, so or lock 36 Close PMOS transistor MP2, and multiplexer 38 is connected to dividing potential drop end S0P5 and gate terminal PROT_G.Grid The voltage of end PROT_G can be all 0.5V so that PMOS transistor as the voltage of dividing potential drop end S0P5 MP_CORE opens, by the connection voltage high of connection end PROT_D to 1.5V.After time point t2, fortune Calculate amplifier 12 and continue to draw high the voltage of gate terminal VG, and it is defeated to cause nmos pass transistor MN_CORE to draw high Go out the output voltage of power line LDO_OUT, until stable at target voltage values (1.0V), as shown in Figure 3.From Fig. 3 it can be seen that whenever, PMOS transistor MP_CORE and nmos pass transistor MN_CORE, often The cross-pressure at any two ends in individual element, is both less than or equal to 1V, the problem therefore not having reliability.

Due to when stable state, the driving stage of LDO 30 be with core parts (PMOS transistor MP_CORE with And a nmos pass transistor MN_CORE), supply induced current.Knowable to design with analog result, whether at silicon Area and PSRR PSRR consider, the performance of LDO 30 all than in known technology through import and export Element supplies the LDO 10 of induced current and 20 outstanding.

Fig. 7 shows according to another embodiment of the present invention.In LDO 50, it is that PMOS in Fig. 2 embodiment is brilliant Body pipe MP_CORE is replaced into nmos pass transistor MN2_CORE.Due to nmos pass transistor MN2_CORE Need higher grid voltage to open, in LDO 50, it is provided that another bleeder circuit 54, be coupled to 3.3V's Between electric wire wire AVDD3P3 and ground power line, provide the voltage of 2.2V through dividing potential drop end S2P2.Work as comparator 34 output logical values " 0 " time, multiplexer 38 is by PROT_G ground connection, to guarantee nmos pass transistor MN2_CORE Close；When comparator 34 exports logical value " 1 " time, PROT_G is connected the voltage of 2.2V to open by multiplexer 38 Open nmos pass transistor MN2_CORE.

Fig. 8 shows according to another embodiment of the present invention.In LDO 60, it is that NMOS in Fig. 2 embodiment is brilliant Body pipe MN_CORE is replaced into PMOS transistor MP2_CORE.And the operational amplifier 12 in Fig. 2 is two defeated Enter to hold reversal connection, become operational amplifier 62 in fig. 8.But nmos pass transistor MN_CORE is replaced into PMOS transistor MP2_CORE will cause poor PSRR PRSS.The foregoing is only the present invention's Preferred embodiment, all impartial changes done according to scope of the present invention patent and modification, all should belong to the culvert of the present invention Lid scope.

Claims

1. a low pressure difference linear voltage regulator, in order to receive an input voltage and in an output from an input power cord Power line exports an output voltage, includes:

One first active member and one second active member, all have a withstanding voltage, this first active member with This second active member, through a connection end, is series between this input power cord and this out-put supply line；

One operational amplifier, is connected to a control end of this second active member, according to this output voltage and a core One core power supply voltage of heart power line controls this second active member, so that this output voltage stabilization is in a target electricity Pressure value；And

One protection circuit, is connected to this input power cord, this out-put supply line, this connection end and this first active One control end of element, according to this input voltage and this output voltage, control the voltage of this connection end and this This control end of one active member.

2. this low pressure difference linear voltage regulator as claimed in claim 1, it is characterised in that this protection circuit comprises There is a bleeder circuit, be connected between this input power cord and a ground power line, and there is one first dividing potential drop end, When this core power supply voltage is less than a particular value, this protection circuit controls this first dividing potential drop end and is electrically connected to this company Connect end.

3. this low pressure difference linear voltage regulator as claimed in claim 2, it is characterised in that this protection circuit is more wrapped Containing one the 3rd active member, it is connected to this first dividing potential drop end and is connected between end with this.

4. this low pressure difference linear voltage regulator as claimed in claim 3, it is characterised in that this withstanding voltage is First withstanding voltage, the 3rd active member has one second withstanding voltage, and it is equal to this input voltage.

5. this low pressure difference linear voltage regulator as claimed in claim 3, it is characterised in that this withstanding voltage is First withstanding voltage, the 3rd active member has one second withstanding voltage, and it is equal to this particular value.

6. this low pressure difference linear voltage regulator as claimed in claim 1, it is characterised in that when this core power electricity Pressure is a particular value, and when this output voltage is less than a preset security value, this protection circuit controls this core power line Being electrically connected to this connection end, this preset security value is less than this target voltage values.

7. this low pressure difference linear voltage regulator as claimed in claim 6, it is characterised in that this protection circuit comprises There is one the 4th active member, be connected to this core power line and be connected between end with this.

8. this low pressure difference linear voltage regulator as claimed in claim 7, it is characterised in that this withstanding voltage is First withstanding voltage, the 4th active member is to manufacture to bear one second withstanding voltage, and it is equal to this input voltage.

9. this low pressure difference linear voltage regulator as claimed in claim 7, it is characterised in that this withstanding voltage is First withstanding voltage, the 4th active member has one second withstanding voltage, and it is equal to this particular value.

10. this low pressure difference linear voltage regulator as claimed in claim 1, it is characterised in that this protection circuit comprises Have:

One comparator, compares this output voltage and a preset security value, and this preset security value is less than this target voltage values, When this output voltage is less than this preset security value, this protection circuit closes this first active member, and defeated when this When going out voltage higher than this preset security value, this protection circuit opens this first active member.

11. these low pressure difference linear voltage regulators as claimed in claim 10, it is characterised in that this protection circuit is also wrapped Contain:

One first bleeder circuit, is connected between this input power cord and an earth lead, has one second dividing potential drop end； And

One multiplexer, has two inputs and is respectively connecting to this second dividing potential drop end and this input power cord and an output It is connected to this control end of this first active member；

Wherein, when this output voltage is less than this preset security value, this multiplexer connect this input power cord to this This control end of one active member, to maintain this first active member to close；And

When this output voltage is higher than this preset security value, this multiplexer connects this second dividing potential drop end to this first active This control end of element, to maintain this first active member to open.

12. these low pressure difference linear voltage regulators as claimed in claim 10, it is characterised in that this protection circuit is also wrapped Contain:

One second bleeder circuit, is connected between a power supply line and an earth lead, has one the 3rd dividing potential drop end； And

One multiplexer, has two inputs and is respectively connecting to the 3rd dividing potential drop end and ground connection and an output is connected to this This control end of first active member；

Wherein, when this output voltage is less than this preset security value, this multiplexer is by this control of this first active member End ground connection processed, to maintain this first active member to close；And

When this output voltage is higher than this preset security value, this multiplexer connects the 3rd dividing potential drop end to this first active This control end of element, to maintain this first active member to open.

13. 1 kinds of voltage conversion methods, receive an input for a low pressure difference linear voltage regulator from an input power cord Voltage also exports an output voltage in an out-put supply line, this low pressure difference linear voltage regulator comprise one first active member, One second active member and an operational amplifier, this first active member is connected through one with this second active member End is series between this input power cord and this out-put supply line, and it is resistance to that this first and second active member all has one By voltage, this operational amplifier is connected to a control end of this second active member, and this voltage conversion method comprises:

This second active member is controlled according to a core power supply voltage of this output voltage and a core power line, with Make this output voltage stabilization in a target voltage values；And

According to this voltage being connected end of this input voltage and this output voltage control and this first active member should Control end.

14. voltage conversion methods as claimed in claim 13, it is characterised in that this low pressure difference linear voltage regulator Also comprise a protection circuit, this protection circuit be connected to this input power cord, this out-put supply line, this connection end, One control end and this core power line of this first active member, this protection circuit includes one first bleeder circuit, It is connected between this input power cord and a ground power line, and there is one first dividing potential drop end and one second dividing potential drop end, This voltage conversion method comprises:

When this core power supply voltage is less than a particular value, this protection circuit controls this first dividing potential drop end and is electrically connected to This connection end；

When this core power supply voltage is this particular value, and when this output voltage is less than a preset security value, this protection electricity Road controls this core power line and is electrically connected to this connection end, and this preset security value is less than this target voltage values；And

When this output voltage is higher than this preset security value, this protection circuit controls this second dividing potential drop end and is electrically connected to This control end of this first active member is to open this first active member, so that this input power cord is electrically connected to This connection end.

15. voltage conversion methods as claimed in claim 13, it is characterised in that this low pressure difference linear voltage regulator Also comprise a protection circuit, this protection circuit be connected to this input power cord, this out-put supply line, this connection end, One control end and this core power line of this first active member, this protection circuit includes one first bleeder circuit And one second bleeder circuit, this first bleeder circuit is connected between this input power cord and a ground power line, And there is one first dividing potential drop end, this second bleeder circuit is connected between a power supply line and a ground power line, And there is one the 3rd dividing potential drop end, the voltage of the 3rd dividing potential drop end is higher than this input voltage, and this voltage conversion method comprises:

When this output voltage is higher than this preset security value, this protection circuit controls the 3rd dividing potential drop end and is electrically connected to This control end of this first active member is to open this first active member, so that this input power cord is electrically connected to This connection end.