CN106155161B - Efficient low pressure difference linear voltage regulator - Google Patents
Efficient low pressure difference linear voltage regulator Download PDFInfo
- Publication number
- CN106155161B CN106155161B CN201510207855.6A CN201510207855A CN106155161B CN 106155161 B CN106155161 B CN 106155161B CN 201510207855 A CN201510207855 A CN 201510207855A CN 106155161 B CN106155161 B CN 106155161B
- Authority
- CN
- China
- Prior art keywords
- voltage
- active member
- protection circuit
- partial pressure
- core
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention relates to a kind of efficient low pressure difference linear voltage regulator, to receive an input voltage from an input power cord and export an output voltage in an out-put supply line.The low pressure difference linear voltage regulator includes one first active member and one second active member, an operational amplifier and a protection circuit.First active member and second active member, all with a withstanding voltage.First active member passes through a connection end with second active member, is series between the input power cord and the out-put supply line.The operational amplifier is connected to a control end of second active member, and the core power supply voltage according to the output voltage and a core power line controls second active member, so that the output voltage stabilization is in a target voltage values.The protection circuit is connected to a control end of the input power cord, the out-put supply line, the connection end and first active member, according to the input voltage and the output voltage, controls the voltage of the connection end and the control end of first active member.
Description
Technical field
The present invention is related to a low pressure difference linear voltage regulator (Low Drop-Out Regulator, LDO), espespecially a kind of high
Efficiency, driving stage (driving stage) LDO is used as using the transistor of low withstanding voltage.
Background technology
IC interior generally requires to be designed with the power line with different voltages, for example, an integrated circuit
Inside, 3.3V power line AVDD3P3,1.0V core power line DVDD, 1.5V import and export power line can be designed with
AVDD1P5,1.0V clock pulse tree power line AVDDTREE etc..One integrated circuit may only receive extraneous one or two
The power supply supply of individual fixed voltage, and other have the power line of different voltages, then are to pass through IC interior Power convert
The conversion that device is provided, to stablize the supply voltage of each power line.LDO is one kind of power supply changeover device, because of the letter of its framework
It is single, so widely IC design circle institute is widely used.Although supply voltage is identical, core power line DVDD and clock pulse tree electricity
Source line AVDDTREE will not short cut with each other, and be mutually isolated, it is to avoid the noise produced by a power line, have influence on by another
The operation for the circuit that one power line is powered.
In integrated circuit, in order to which in the electric pressing operation of different electrical power, can also be provided with can bear the crystalline substance of different tolerance voltage
Body pipe.The withstanding voltage of one transistor represents the maximum that the cross-pressure between the every two-end-point of this transistor can be born, as long as should
Cross-pressure between the every two-end-point of transistor is no more than the withstanding voltage, and the transistor just has enough reliabilitys.For example,
Integrated circuit has a core circuit, and it is mainly used in logical operation, includes core parts, for example core nmos pass transistor and core
Heart PMOS transistor.In order to reach high arithmetic speed and low power consuming, core circuit is supplied by 1.0V core power line DVDD
Electricity, the withstanding voltage of core parts only has 1V.Integrated circuit can also have output/input circuit, include import and export element, for example
Import and export nmos pass transistor and import and export PMOS transistor.Import and export element is in order to there is the energy of higher anti-extraneous high-voltage signal
Power, so its withstanding voltage may be up to 1.5V, can also be powered by 1.5V import and export power line AVDD1P5.It is general and
Speech, the higher element of withstanding voltage will reach certain current driving capability, the silicon area (silicon shared by its circuit
Area) bigger, cost is higher.In this description, the withstanding voltage of import and export element and core parts is exemplified as respectively
1.5V and 1V.But the invention is not restricted to this, as long as the withstanding voltage of import and export element can more than the withstanding voltage of core parts
With.
Figure 1A is LDO 10 known to one, and it uses withstanding voltage for a 3.3V import and export element nmos pass transistor MN_
3P3, is used as driving stage.LDO 10 is using 3.3V power line AVDD3P3 as primary input power line, in out-put supply line LDO_
On OUT, it is desirable to produce stable 1.0V voltage.Out-put supply line LDO_OUT can as clock pulse tree power line AVDDTREE,
Come the clock pulse tree (clock needed for the output/input circuit to meeting double data rate (double data rate, DDR) agreement
Tree) power.LDO 10 has the shortcomings that one very big：Power consumption.In normal operating, nmos pass transistor MN_3P3 can be consumed in itself
Suitable electric energy, because in stable state, its drain-source cross-pressure (VDS) be up to 2V, itself expend electric energy by be LDO 10 output
The product of electric current and 2V, is wasted very much.
Figure 1B is another known LDO 20.LDO 20 primary input power line is 1.5V import and export power line
AVDD1P5, driving stage is using the nmos pass transistor MN_1P5 for belonging to an import and export element.LDO 20 than LDO10 power saving because
Nmos pass transistor MN_1P5 VDSOnly 0.5V.Simply, such low VDS, nmos pass transistor MN_1P5 will reach sufficiently high
Driving current, no matter being considered in silicon area and PSRR (power supply rejection ratio, PSRR),
All it is difficult to.
The content of the invention
Embodiment disclose have a kind of low pressure difference linear voltage regulator, to from an input power cord receive an input voltage and in
One out-put supply line exports an output voltage.The low pressure difference linear voltage regulator includes one first active member and one second master
Dynamic element, an operational amplifier and a protection circuit.First active member and second active member, all with one
Withstanding voltage.First active member passes through a connection end with second active member, is series at the input power cord and is somebody's turn to do
Between out-put supply line.The operational amplifier is connected to a control end of second active member, according to the output voltage and
One core power supply voltage of one core power line controls second active member, so that the output voltage stabilization is in a target voltage
Value.The protection circuit is connected to a control of the input power cord, the out-put supply line, the connection end and first active member
End processed, according to the input voltage and the output voltage, controls the control of the voltage and first active member of the connection end
End processed.
Embodiment, which is disclosed, a kind of voltage conversion method, is received for a low pressure difference linear voltage regulator from an input power cord
One input voltage simultaneously exports an output voltage in an out-put supply line.The low pressure difference linear voltage regulator includes one first active element
Part, one second active member and an operational amplifier.First active member passes through a connection end with second active member
It is series between the input power cord and the out-put supply line.First and second active member all has a withstanding voltage.
The operational amplifier is connected to a control end of second active member.The voltage conversion method is included：According to the output voltage
And one a core power supply voltage of core power line control second active member so that the output voltage stabilization is in a target
Magnitude of voltage；And, voltage and first active member according to the input voltage and the output voltage control connection end
The control end.
Brief description of the drawings
Figure 1A is LDO known to one.
Figure 1B is another known LDO.
Fig. 1 C are an imaginary LDO.
The LDO that Fig. 2 displays are implemented according to the present invention.
Fig. 3 shows some signal waveforms in Fig. 2.
Fig. 4 is especially denoted before time point t1, some element states of element in Fig. 2.
Fig. 5 is especially denoted between time point t1 to t2, some element states of element in Fig. 2.
Fig. 6 is especially denoted after time point t2, some element states of element in Fig. 2.
Fig. 7 and Fig. 8 is according to another two LDO of the invention implemented.
Symbol description
10：LDO
12：Operational amplifier
20：LDO
25：LDO
30：LDO
32：Protection circuit
34：Comparator
36：Or lock
38：Multiplexer
40：Bleeder circuit
50：LDO
52：Protection circuit
54：Bleeder circuit
60：LDO
62：Operational amplifier
AVDD1P5：Import and export power line
AVDD3P3：Power line
DVDD：Core power line
LDO_OUT：Out-put supply line
MN_1P5：Nmos pass transistor
MN_3P3：Nmos pass transistor
MN_CORE：Nmos pass transistor
MN1_CORE：Nmos pass transistor
MN2_CORE：Nmos pass transistor
MP_CORE：PMOS transistor
MP2_CORE：PMOS transistor
MP1：PMOS transistor
MP2：PMOS transistor
PG：Power good signal
PROT_D：Connection end
PROT_G：Gate terminal
S1P0、S0P5、S2P2：Partial pressure end
t0、t1、t2：Time point
VG：Gate terminal
VREF：Preset security value
Embodiment
Fig. 1 C are an imaginary LDO 25.Compared to Figure 1B, LDO 25 driving stage, which changes to use, belongs to the one of core parts
Nmos pass transistor MN1_CORE.Unfortunately, LDO 25 has reliability issues.For example, an electric sequence (power
Sequence) in design, the import and export power line AVDD1P5 in Fig. 1 C is used as a primary input power line, main power source electricity thereon
Pressure may be reached after 1.5V, and the ability of operational amplifier 12 draws high nmos pass transistor MN1_CORE grid since 0V, and exports electricity
Output voltage on the line LDO_OUT of source is just close toward the 1.0V of target voltage values from 0V at leisure.It has been discovered that NMOS is brilliant
Body pipe MN1_CORE drain-gate cross-pressure (VDG) and drain-source cross-pressure (VDS), maximum is about 1.5V, more than nmos pass transistor MN1_
CORE withstanding voltage (1V).So, nmos pass transistor MN1_CORE in LDO 25 is because too high cross-pressure, in practice
Have reliability issues.
The LDO 30 that Fig. 2 displays are implemented according to the present invention.LDO 30 driving stage has a PMOS transistor MP_CORE
(a first active member) and nmos pass transistor MN_CORE (the second active member), is both to belong to core parts.PMOS
Transistor AND gate nmos pass transistor is all some embodiments of active member, and the invention is not restricted to this.For example, in other realities
Apply in example, active member can be vacuum tube device, field-effect transistor (field effect transistor, FET), bipolar
Property junction transistor (Bipolar Junction Transistor, BJT) etc..Import and export power line AVDD1P5 is defeated as a master
Enter power line, be connected to PMOS transistor MP_CORE source electrode.In stable state, import and export power line AVDD1P5 supply voltage
For 1.5V.Out-put supply line LDO_OUT is connected to nmos pass transistor MN_CORE source electrode.PMOS transistor MP_CORE and NMOS
Transistor MN_CORE drain electrode, is all connected to connection end PROT_D.As shown in Figure 2, PMOS transistor MP_CORE and NMOS
Transistor MN_CORE is series between import and export power line AVDD1P5 and out-put supply line LDO_OUT.PMOS transistor MP_
There is CORE gate terminal PROT_G, nmos pass transistor MN_CORE to have gate terminal VG.
Operational amplifier 12 is powered by 3.3V power line AVDD3P3, and core electricity is connected respectively to two inputs
Source line DVDD and out-put supply line LDO_OUT.The output of operational amplifier 12 is connected to gate terminal VG.In stable state, core
Power line DVDD supply voltage is 1.0V, so during stable state, the output voltage on out-put supply line LDO_OUT is also 1.0V
(target voltage values).
LDO 30 has additionally comprised a protection circuit 32, its be coupled to out-put supply line LDO_OUT, core power line DVDD,
With import and export power line AVDD1P5.The extreme PROT_G of the control gate of protection circuit 32 and connection end PROT_D.In an electric sequence
In, protection circuit 32 may insure the cross-pressure at any two ends on PMOS transistor MP_CORE and nmos pass transistor MN_CORE, example
Such as VDS、VGD、VGSDeng the no more than withstanding voltage (1V) of core parts.So protection circuit 32 ensures PMOS transistor MP_
CORE and nmos pass transistor MN_CORE are all without there is reliability issues.
Protection circuit 32 has a bleeder circuit 40, be connected to import and export power line AVDD1P5 and a ground power line it
Between.Bleeder circuit 40 has three resistance, is connected with partial pressure end S1P0 with S0P5.In one embodiment, the resistance of three resistance
Value is about all.In stable state, import and export power line AVDD1P5 main power voltage is about 1.5V, partial pressure end S1P0 with
S0P5 voltage is about 1V and 0.5V respectively.
PMOS transistor MP1 (the 3rd active member) is connected between partial pressure end S1P0 and connection end PROT_D, and PMOS is brilliant
Body pipe MP2 (the 4th active member) is connected between core power line DVDD and connection end PROT_D.In one embodiment, PMOS
Transistor MP1 and MP2 are core parts.In another embodiment, PMOS transistor MP1 and MP2 are import and export elements.
Comparator 34 compares a preset security value VREFWith out-put supply line LDO_OUT output voltage.In this embodiment
In, preset security value VREFFor 0.5V, less than target voltage values (1.0V) of the out-put supply line LDO_OUT in stable state.
Multiplexer 38 is respectively connecting to partial pressure end S0P5 with two inputs and import and export power line AVDD1P5 and one are defeated
Go out to be connected to PMOS transistor MP_CORE gate terminal PROT_G.As can be known from Fig. 2, when out-put supply line LDO_OUT output
When voltage is less than 0.5V, the connection of multiplexer 38 import and export power line AVDD1P5 to gate terminal PROT_G；Conversely, working as out-put supply
When line LDO_OUT output voltage is more than 0.5V, the connection of multiplexer 38 partial pressure end S0P5 to gate terminal PROT_G.
PMOS transistor MP1 with or lock 36 receive and have a reverse power good signal PG, its logical value regards core power line
Depending on DVDD core power supply voltage.For example, when core power supply voltage is more than 0.9V (a core normal value), it can be considered as
Core power supply voltage has reached the 1V of stable state, so power good signal PG becomes in logic " 1 ", voltage potential is one
High-voltage value.Conversely, when core power supply voltage is less than 0.9V, power good signal PG is in logic " 0 ", voltage potential is one
Low voltage value.For core parts, high-voltage value is 1V, for import and export element, and high-voltage value is 1.5V.
Fig. 3 shows some signal waveforms in Fig. 2, from top to bottom, is import and export power line AVDD1P5 main power source respectively
Voltage, core power line DVDD core power supply voltage, power good signal PG logical value, connection end PROT_D voltage,
The output voltage of connection end PROT_G voltage, gate terminal VG voltage and out-put supply line LDO_OUT.In Fig. 3, it is assumed that
Electric sequence (power sequence) be import and export power line AVDD1P5 at first upper electricity, followed by core power line DVDD, so
After be only out-put supply line LDO_OUT.
Referring to Fig. 3 and Fig. 4.Fig. 4 is especially denoted before time point t1, some element shapes of element in Fig. 2
State, includes PMOS transistor MP1 unlatchings, PMOS transistor MP2 closings, PMOS transistor MP_CORE closings, nmos pass transistor
MN_CORE is closed and multiplexer 38 is connected to import and export power line AVDD1P5 and gate terminal PROT_G.
When LDO 30 is upper at the beginning electric, import and export power line AVDD1P5 main power voltage climbs since 0V, in the time
Point t0 reaches 1.5V during stable state.Partial pressure end S1P0 and S0P5 voltage is the 2/3 and 1/3 of main power voltage respectively, so
It can together be climbed with main power voltage, the 1V and 0.5V of stable state are respectively reached in time point t0.Before time point t1, output
Power line LDO_OUT output voltage is about 0V, the output of comparator 34 logical value " 0 ", multiplexer 38 is controlled, it is connected
Import and export power line AVDD1P5 and gate terminal PROT_G, so PMOS transistor MP_CORE is closed.Before time point t1, because
Core power line DVDD core power supply voltage is also relatively low, so power good signal PG is in logic " 0 ", PMOS transistor
MP1 is opened, by partial pressure end S1P0 and the short circuit of connection end PROT_D phases.Therefore, before time point t1, connection end PROT_D company
The voltage that voltage will follow partial pressure end S1P0 is connect, climbs and rests on 1V, as shown in Figure 3.In addition, logical value is " 0 " electricity
The logical value that source normal signal PG and comparator 34 are exported " 0 " is also resulted in or the output of lock 36 logical value " 1 ", so PMOS is brilliant
Body pipe MP2 is closed.As shown in Figure 3, before time point t1, gate terminal VG is about 0V, so nmos pass transistor MN_CORE
Close.
Referring to Fig. 3 and Fig. 5.Fig. 5 is especially denoted between time point t1 to t2, some members of element in Fig. 2
Part state, includes PMOS transistor MP1 closings, PMOS transistor MP2 unlatchings, PMOS transistor MP_CORE closings, NMOS crystalline substances
Body pipe MN_CORE is opened and multiplexer 38 is connected to import and export power line AVDD1P5 and gate terminal PROT_G.
In time point t1, core power line DVDD core power supply voltage is almost stabilized, and power good signal PG turns
State is in logic " 1 ".So, PMOS transistor MP1 is closed, PMOS transistor MP2 is opened, and maintains connection end PROT_D company
Voltage is connect in core power line DVDD 1V.After time point t1, the electricity for drawing high gate terminal VG of operational amplifier 12 slowly
Pressure, subsequently results in nmos pass transistor MN_CORE unlatchings, out-put supply line LDO_OUT output voltage has also been drawn high, such as Fig. 3
It is shown.Out-put supply line LDO_OUT output voltage reaches 0.5V (preset security value V in time point t2REF)。
Referring to Fig. 3 and Fig. 6.Fig. 6 is especially denoted after time point t2, some element shapes of element in Fig. 2
State, includes PMOS transistor MP1 closings, PMOS transistor MP2 closings, PMOS transistor MP_CORE unlatchings, nmos pass transistor
MN_CORE is opened and multiplexer 38 is connected to partial pressure end S0P5 and gate terminal PROT_G.
After time point t2, out-put supply line LDO_OUT output voltage has exceeded 0.5V, so or lock 36 close
PMOS transistor MP2, and multiplexer 38 is connected to partial pressure end S0P5 and gate terminal PROT_G.Gate terminal PROT_G voltage can be with
Partial pressure end S0P5 voltage is the same, is all 0.5V so that PMOS transistor MP_CORE is opened, by connection end PROT_D connection
Voltage high is to 1.5V.After time point t2, operational amplifier 12 continues to draw high gate terminal VG voltage, and causes NMOS brilliant
Body pipe MN_CORE has drawn high out-put supply line LDO_OUT output voltage, until stablizing at target voltage values (1.0V), as
Shown in Fig. 3.From figure 3, it can be seen that whenever, PMOS transistor MP_CORE and nmos pass transistor MN_CORE, each element
In any two ends cross-pressure, both less than or equal to 1V, therefore the problem of there is no reliability.
Because in stable state, LDO 30 driving stage is with core parts (a PMOS transistor MP_CORE and a NMOS
Transistor MN_CORE), to supply electric current.It was found from design and analog result, whether in silicon area and PSRR
PSRR's considers, and LDO 30 performance supplies the LDO 10 and 20 of electric current all than the transmission import and export element in known technology
That comes is outstanding.
Fig. 7 displays are according to another embodiment of the present invention.It is by PMOS transistor MP_ in Fig. 2 embodiments in LDO 50
CORE is replaced into nmos pass transistor MN2_CORE.Because nmos pass transistor MN2_CORE needs higher grid voltage to open,
There is provided another bleeder circuit 54 in LDO 50, it is coupled between 3.3V electric wire wire AVDD3P3 and ground power line, passes through
Partial pressure end S2P2 provides 2.2V voltage.When comparator 34 export logical value " 0 " when, PROT_G is grounded by multiplexer 38, with true
Nmos pass transistor MN2_CORE is protected to close；When comparator 34 export logical value " 1 " when, multiplexer 38 is by PROT_G connections 2.2V's
Voltage is to open nmos pass transistor MN2_CORE.
Fig. 8 displays are according to another embodiment of the present invention.It is by nmos pass transistor MN_ in Fig. 2 embodiments in LDO 60
CORE is replaced into PMOS transistor MP2_CORE.And two input reversal connections of the operational amplifier 12 in Fig. 2, turn into fig. 8
Operational amplifier 62.But nmos pass transistor MN_CORE is replaced into PMOS transistor MP2_CORE to cause poor power supply
Rejection ratio PRSS.It the foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to scope of the present invention patent
Change and modify, should all belong to the covering scope of the present invention.
Claims (15)
1. a kind of low pressure difference linear voltage regulator, to receive an input voltage and defeated in an out-put supply line from an input power cord
Go out an output voltage, include：
One first active member and one second active member, all with a withstanding voltage, first active member with this second
Active member passes through a connection end, is series between the input power cord and the out-put supply line；
One operational amplifier, is connected to a control end of second active member, according to the output voltage and a core power
One core power supply voltage of line controls second active member, so that the output voltage stabilization is in a target voltage values；And
One protection circuit, is connected to the input power cord, the out-put supply line, the connection end, a control of first active member
End processed and the core power line, according to the input voltage and the output voltage, control the connection end voltage and this
The control end of one active member.
2. low pressure difference linear voltage regulator as claimed in claim 1, it is characterised in that the protection circuit includes partial pressure electricity
Road, is connected between the input power cord and a ground power line, and with one first partial pressure end, when the core power supply voltage is low
When a particular value, the protection circuit controls the first partial pressure end to be electrically connected to the connection end.
3. low pressure difference linear voltage regulator as claimed in claim 2, it is characterised in that the protection circuit has further included one the 3rd
Active member, is connected between the first partial pressure end and the connection end.
4. low pressure difference linear voltage regulator as claimed in claim 3, it is characterised in that the withstanding voltage is one first tolerance electricity
Pressure, the 3rd active member has one second withstanding voltage, and it is equal to the input voltage.
5. low pressure difference linear voltage regulator as claimed in claim 3, it is characterised in that the withstanding voltage is one first tolerance electricity
Pressure, the 3rd active member has one second withstanding voltage, and it is equal to the particular value.
6. low pressure difference linear voltage regulator as claimed in claim 1, it is characterised in that when the core power supply voltage is one specific
Value, and the output voltage be less than a preset security value when, the protection circuit controls the core power line to be electrically connected to the connection
End, the preset security value is less than the target voltage values.
7. low pressure difference linear voltage regulator as claimed in claim 6, it is characterised in that the protection circuit includes one the 4th master
Dynamic element, is connected between the core power line and the connection end.
8. low pressure difference linear voltage regulator as claimed in claim 7, it is characterised in that the withstanding voltage is one first tolerance electricity
Pressure, the 4th active member is to manufacture to bear one second withstanding voltage, and it is equal to the input voltage.
9. low pressure difference linear voltage regulator as claimed in claim 7, it is characterised in that the withstanding voltage is one first tolerance electricity
Pressure, the 4th active member has one second withstanding voltage, and it is equal to the particular value.
10. low pressure difference linear voltage regulator as claimed in claim 1, it is characterised in that the protection circuit includes：
One comparator, compares the output voltage and a preset security value, and the preset security value is less than the target voltage values, when this is defeated
When going out voltage less than the preset security value, the protection circuit closes first active member, and is somebody's turn to do when the output voltage is higher than
During preset security value, the protection circuit opens first active member.
11. low pressure difference linear voltage regulator as claimed in claim 10, it is characterised in that the protection circuit also includes：
One first bleeder circuit, is connected between the input power cord and a ground wire, with one second partial pressure end；And
One multiplexer, is respectively connecting to the second partial pressure end with two inputs and is connected to the input power cord and an output
The control end of first active member；
Wherein, when the output voltage is less than the preset security value, the multiplexer connects the input power cord to first active
Control end of element, to maintain first active member to close；And
When the output voltage is higher than the preset security value, the multiplexer connects the second partial pressure end to first active member
The control end, to maintain first active member to open.
12. low pressure difference linear voltage regulator as claimed in claim 10, it is characterised in that the protection circuit also includes：
One second bleeder circuit, is connected between a power supply line and a ground wire, with one the 3rd partial pressure end；And
One multiplexer, is respectively connecting to the 3rd partial pressure end and ground connection with two inputs and an output is connected to first master
The control end of dynamic element；
Wherein, when the output voltage is less than the preset security value, the multiplexer terminates the control of first active member
Ground, to maintain first active member to close；And
When the output voltage is higher than the preset security value, the multiplexer connects the 3rd partial pressure end to first active member
The control end, to maintain first active member to open.
13. a kind of voltage conversion method, an input voltage is received simultaneously for a low pressure difference linear voltage regulator from an input power cord
An output voltage is exported in an out-put supply line, the low pressure difference linear voltage regulator includes one first active member, one second active
Element and an operational amplifier, first active member are series at input electricity with second active member through a connection end
Between source line and the out-put supply line, first and second active member all has a withstanding voltage, and the operational amplifier connects
A control end of second active member is connected to, the voltage conversion method is included：
A core power supply voltage according to the output voltage and a core power line controls second active member, so that this is defeated
Go out voltage stabilization in a target voltage values；And
According to the input voltage and the voltage and the control end of first active member of the output voltage control connection end.
14. voltage conversion method as claimed in claim 13, it is characterised in that the low pressure difference linear voltage regulator is also protected comprising one
Protection circuit, the protection circuit is connected to the input power cord, the out-put supply line, the connection end, the one of first active member
Control end and the core power line, the protection circuit include one first bleeder circuit, are connected to the input power cord and one
Between ground power line, and with one first partial pressure end and one second partial pressure end, the voltage conversion method is included：
When the core power supply voltage is less than a particular value, the protection circuit controls the first partial pressure end to be electrically connected to the connection
End；
When the core power supply voltage be the particular value, and the output voltage be less than a preset security value when, the protection circuit control
The core power line is electrically connected to the connection end, and the preset security value is less than the target voltage values；And
When the output voltage be higher than the preset security value when, the protection circuit control the second partial pressure end be electrically connected to this first
The control end of active member is to open first active member, so that the input power cord is electrically connected to the connection end.
15. voltage conversion method as claimed in claim 13, it is characterised in that the low pressure difference linear voltage regulator is also protected comprising one
Protection circuit, the protection circuit is connected to the input power cord, the out-put supply line, the connection end, the one of first active member
Control end and the core power line, the protection circuit include one first bleeder circuit and one second bleeder circuit, and this
One bleeder circuit is connected between the input power cord and a ground power line, and with one first partial pressure end, second partial pressure
Circuit is connected between a power supply line and a ground power line, and with one the 3rd partial pressure end, the electricity at the 3rd partial pressure end
Pressure is higher than the input voltage, and the voltage conversion method is included：
When the core power supply voltage is less than a particular value, the protection circuit controls the first partial pressure end to be electrically connected to the connection
End；
When the core power supply voltage be the particular value, and the output voltage be less than a preset security value when, the protection circuit control
The core power line is electrically connected to the connection end, and the preset security value is less than the target voltage values；And
When the output voltage be higher than the preset security value when, the protection circuit control the 3rd partial pressure end be electrically connected to this first
The control end of active member is to open first active member, so that the input power cord is electrically connected to the connection end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510207855.6A CN106155161B (en) | 2015-04-28 | 2015-04-28 | Efficient low pressure difference linear voltage regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510207855.6A CN106155161B (en) | 2015-04-28 | 2015-04-28 | Efficient low pressure difference linear voltage regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106155161A CN106155161A (en) | 2016-11-23 |
| CN106155161B true CN106155161B (en) | 2017-08-18 |
Family
ID=57347763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510207855.6A Active CN106155161B (en) | 2015-04-28 | 2015-04-28 | Efficient low pressure difference linear voltage regulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106155161B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290806A (en) * | 2011-08-24 | 2011-12-21 | 北京经纬恒润科技有限公司 | LDO (Low Dropout Output) overvoltage protective circuit and LDO (Low Dropout Output) using the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1669831A1 (en) * | 2004-12-03 | 2006-06-14 | Dialog Semiconductor GmbH | Voltage regulator output stage with low voltage MOS devices |
| US20080204958A1 (en) * | 2007-02-27 | 2008-08-28 | Intersil Americas Inc. | Back-current protection circuit |
-
2015
- 2015-04-28 CN CN201510207855.6A patent/CN106155161B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290806A (en) * | 2011-08-24 | 2011-12-21 | 北京经纬恒润科技有限公司 | LDO (Low Dropout Output) overvoltage protective circuit and LDO (Low Dropout Output) using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106155161A (en) | 2016-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105871180B (en) | A kind of high current CMOS push-pull driver circuits and its control method | |
| US9454164B2 (en) | Method and apparatus for limiting startup inrush current for low dropout regulator | |
| US9817426B2 (en) | Low quiescent current voltage regulator with high load-current capability | |
| US9958889B2 (en) | High and low power voltage regulation circuit | |
| CN104808735B (en) | Low-voltage differential signal drive circuit | |
| CN105700598B (en) | A kind of foldback current limit circuit for Voltagre regulator | |
| CN103973273A (en) | High-speed high-precision low-detuning fully differential dynamic comparator | |
| CN104793678A (en) | Voltage regulator | |
| CN103117740B (en) | Low-power-consumptiolevel level shift circuit | |
| CN107390758A (en) | Low-voltage bandgap reference source circuit | |
| CN204361895U (en) | Drive pressurizer | |
| CN105099436B (en) | Track to track input buffer | |
| CN106155161B (en) | Efficient low pressure difference linear voltage regulator | |
| CN105577165B (en) | A kind of I/O interface level shifting circuit and I/O interface level conversion method | |
| CN102044964A (en) | Voltage regulator circuit | |
| CN101853037A (en) | Energy-saving voltage stabilizer | |
| CN104270138A (en) | Input/output buffer of multiple voltage domains | |
| CN107992144B (en) | The start-up circuit of band gap reference | |
| CN209297190U (en) | A kind of low pressure drop image current source circuit | |
| CN207706058U (en) | A kind of constant-current control circuit, chip and Switching Power Supply | |
| CN203786597U (en) | Low-dropout linear regulator | |
| CN207264237U (en) | A kind of adjustable reduction voltage circuit of GaN chips TGA2216 SM | |
| CN104299647B (en) | Negative pressure conversion circuit | |
| CN205490105U (en) | Reduction voltage circuit among middle and high voltage integrated circuit | |
| TWI569123B (en) | Ldo with high power conversion efficiency |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191217 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Patentee after: MediaTek.Inc Address before: Taiwan Hsinchu County Tai Yuan Street China jhubei City, No. 26 4 floor 1 Patentee before: MStar Semiconductor Co., Ltd. |
|
| TR01 | Transfer of patent right |