CN106154669A - Array base palte and preparation method thereof, liquid crystal indicator - Google Patents
Array base palte and preparation method thereof, liquid crystal indicator Download PDFInfo
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- CN106154669A CN106154669A CN201610823315.5A CN201610823315A CN106154669A CN 106154669 A CN106154669 A CN 106154669A CN 201610823315 A CN201610823315 A CN 201610823315A CN 106154669 A CN106154669 A CN 106154669A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 16
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 208
- 239000010409 thin film Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 13
- 230000000903 blocking effect Effects 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 53
- 239000011159 matrix material Substances 0.000 abstract description 14
- 239000002184 metal Substances 0.000 description 20
- 239000010408 film Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention relates to a kind of array base palte and preparation method thereof, liquid crystal indicator.Array base palte includes: underlay substrate；It is positioned at the thin film transistor (TFT) on described underlay substrate, described thin film transistor (TFT) includes active layer, source electrode, drain electrode and via, and described drain electrode or described source electrode have the part being positioned in described via, also include: the first light-shielding structure, described first light-shielding structure is less than the described via distance to described underlay substrate to the distance of described underlay substrate, described first light-shielding structure upright projection on described underlay substrate has overlapping region with described via upright projection on described underlay substrate, described first light-shielding structure is for reducing incident from described underlay substrate side and being irradiated to described drain electrode or the light of described source electrode.Array base palte of the present invention and preparation method thereof, liquid crystal indicator, by arranging light-shielding structure, the problem solving light leak in the case of need not widening black matrix, there is higher aperture opening ratio.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a liquid crystal display device.
Background
Fig. 1A, 1B and 1C show pixel structures of a conventional lcd, specifically, fig. 1A is a schematic top view of the pixel structure of the conventional lcd, fig. 1B is a schematic cross-sectional view of fig. 1A along a dashed line 100, and fig. 1C is a schematic cross-sectional view of fig. 1A along a dashed line 110. Referring to fig. 1A, 1B and 1C, a TFT substrate 1 and a color filter substrate 2 are bonded to form a display, and a support pillar 11 is usually disposed at an intersection of a horizontal black matrix 12 and a vertical black matrix 13 and located between two adjacent transistors on the TFT substrate 1. The TFT substrate further includes data lines 14 and scan lines 15, and a region where the data lines 14 and the scan lines 15 vertically cross is a pixel region 16. The cross-sectional views of the display along the dotted lines 100 and 110 are shown in fig. 1B and 1C, and the liquid crystal display includes a thin film transistor 17 and a supporting pillar 11, and a pixel region 16 is viewed along 110 in a horizontal plane.
Fig. 2 is a schematic view of a source/drain metal electrode. As shown in fig. 2, the side wall of the via hole 22 of the interlayer insulating layer has a certain angle, and the source/drain metal electrode 23 is attached to the side wall of the via hole 22, wherein the interlayer insulating layer is composed of two layers of dielectrics, namely a silicon oxide layer 211 and a silicon nitride layer 212. When light rays irradiate, the source/drain electrode metal electrode 23 on the side wall can reflect the light rays, and in the case of the first condition, part of the light rays are directly reflected and emitted upwards; in the case of the second embodiment, after being reflected downward, part of the light is reflected again at the interface between the silicon oxide layer 211 and the silicon nitride layer 212 and emitted upward, and the light reflected upward interferes with the light emitted along a straight line, so that the polarization state of the light is changed. It can be seen that in both cases, the light does not travel along a straight line, so that the horizontal black matrix 12 on the color filter substrate cannot block the emergent light.
If the width of the black matrix is not wide enough, it is not enough to block a light leakage region, and a light leakage phenomenon occurs in a dark state, resulting in a decrease in contrast. In order to solve the problem of light leakage, the width of the black matrix needs to be increased, and meanwhile, the error of the bonding pair group of the TFT substrate and the color film substrate needs to be considered, the black matrix may not be capable of shielding the light leakage due to dislocation, so that the black matrix needs to be further increased, and the aperture opening ratio is reduced.
Therefore, a new array substrate is required to address the above problems.
The above information disclosed in this background section is only for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention provides an array substrate, a preparation method thereof and a liquid crystal display device, which can solve the problem of light leakage.
Additional features and advantages of the invention will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
According to a first aspect of the present invention, an array substrate includes:
a substrate base plate;
a thin film transistor on the substrate, the thin film transistor including an active layer, a source electrode, a drain electrode, and a via hole, and the drain electrode or the source electrode having a portion in the via hole, the thin film transistor further including:
the distance between the first shading structure and the substrate base plate is smaller than that between the via hole and the substrate base plate, and the distance between the vertical projection of the first shading structure on the substrate base plate and the vertical projection of the drain electrode or the source electrode on the substrate base plate is smaller than or equal to 3 micrometers.
According to an embodiment of the present invention, a vertical projection of the first light shielding structure on the substrate base plate and a vertical projection of the via hole on the substrate base plate have an overlapping region.
According to an embodiment of the present invention, the via hole includes a first via hole and a second via hole, the source has a portion located in the first via hole, the drain has a portion located in the second via hole, and the first light shielding structure is respectively disposed between the first via hole and the substrate and between the second via hole and the substrate.
According to an embodiment of the present invention, the first light shielding structure is polygonal or semicircular.
According to an embodiment of the present invention, a vertical projection of the via hole on the substrate base plate is located in a vertical projection area of the first light shielding structure on the substrate base plate.
According to an embodiment of the present invention, the active layer is polysilicon.
According to an embodiment of the present invention, the display device further includes a second light shielding structure, the second light shielding structure is disposed on a side of the active layer close to the substrate base, a vertical projection of the second light shielding structure on the substrate base and a vertical projection of the active layer on the substrate base have an overlapping region, and a vertical projection of the second light shielding structure on the substrate base and a vertical projection of the first light shielding structure on the substrate base do not overlap.
According to an embodiment of the present invention, the first light shielding structure and the second light shielding structure are located on the same layer.
According to an embodiment of the present invention, the active layer includes a channel region, and the channel region is U-shaped.
According to an embodiment of the present invention, the first light shielding structure is a metal material or a black resin material.
According to an embodiment of the present invention, the light-shielding structure further includes a buffer layer, and the first light-shielding structure is disposed on a side of the buffer layer close to the substrate.
According to an embodiment of the present invention, the array substrate further includes a data line and a scan line crossing each other and disposed in an insulating manner, and the data line is multiplexed as the drain electrode.
According to an embodiment of the present invention, the first light shielding structure and the scan line are located on the same layer.
According to a second aspect of the present invention, a method for preparing an array substrate as described above includes:
providing a substrate base plate;
forming a first light shielding structure on the substrate base plate;
forming a thin film transistor on the substrate base plate; wherein,
the thin film transistor includes an active layer, a source electrode, a drain electrode, and a via hole, and the drain electrode or the source electrode has a portion located in the via hole;
the distance from the first shading structure to the substrate base plate is smaller than the distance from the via hole to the substrate base plate, and the distance between the vertical projection of the first shading structure on the substrate base plate and the vertical projection of the drain electrode or the source electrode on the substrate base plate is smaller than or equal to 3 micrometers.
According to a third aspect of the present invention, a liquid crystal display device includes the array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.
According to the array substrate, the preparation method thereof and the liquid crystal display device, the shading structure is arranged between the via hole and the substrate, the distance between the vertical projection of the first shading structure on the substrate and the vertical projection of the drain electrode or the source electrode on the substrate is less than or equal to 3 micrometers, part or all light rays which are centered on the drain electrode or the source electrode and within a range of 3 micrometers from the drain electrode or the source electrode can be shaded, the light leakage phenomenon caused by light ray reflection of the source/drain metal electrode in the via hole is reduced, the problem of light leakage is solved under the condition that a black matrix is not required to be widened, and the aperture ratio is high.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1A is a schematic top view of a pixel structure of a conventional lcd.
FIG. 1B is a schematic cross-sectional view of FIG. 1A along dashed line 100.
FIG. 1C is a schematic cross-sectional view of FIG. 1A along dashed line 110.
Fig. 2 is a schematic view of a source/drain metal electrode.
Fig. 3A schematically shows a cross-sectional view of a substrate base plate in an array base plate according to an exemplary embodiment of the present invention.
Fig. 3B schematically illustrates a top view of fig. 3A.
Fig. 3C schematically shows a cross-sectional view of a substrate base plate in an array base plate according to an exemplary embodiment of the present invention.
Fig. 3D schematically illustrates a top view of fig. 3C.
Fig. 4A schematically shows a cross-sectional view of a substrate in another array substrate according to an exemplary embodiment of the present invention.
Fig. 4B schematically illustrates a top view of fig. 4A.
Fig. 5 schematically illustrates a top view of a substrate base plate in an array base plate according to an exemplary embodiment of the present invention.
Fig. 6 schematically illustrates a top view of a substrate base plate in an array base plate according to an exemplary embodiment of the present invention.
Fig. 7 schematically illustrates a top view of a substrate base plate in an array base plate according to an exemplary embodiment of the present invention.
Fig. 8 is a flowchart schematically illustrating a method of manufacturing an array substrate according to an exemplary embodiment of the present invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Fig. 3A schematically shows a cross-sectional view of a substrate base plate of an array base plate according to an exemplary embodiment of the present invention, and fig. 3B schematically shows a top view of fig. 3A.
As shown in fig. 3A, an array substrate includes: the substrate 30 includes a thin film transistor on the substrate 30. The thin film transistor includes a buffer layer 31, an active layer 32, a gate insulating layer 33, a gate electrode 34, an interlayer insulating layer 35, and a source/drain metal electrode 36 in this order. A via 37 is also included in the thin film transistor and the source/drain metal electrode 36 has a portion located in the via 37, i.e., the source/drain metal electrode 36 may be disposed in the via 37. Dotted lines are shown as vias 37, and the source/drain metal electrodes 36 are connected to the source and drain regions in the active layer 32 through the vias 37.
The thin film transistor may further include a first light shielding structure 38, and a distance from the first light shielding structure 38 to the substrate base plate 30 is smaller than a distance from the via hole 37 to the substrate base plate 30, that is, the first light shielding structure 38 is located between the substrate base plate 30 and the via hole 37. The vertical projection of the first light shielding structure 38 on the substrate base plate 30 and the vertical projection of the via hole 37 on the substrate base plate 30 have an overlapping region 381, that is, when viewed from the direction of the substrate base plate 30, the first light shielding structure 38 can shield a part of the sidewall of the via hole 37, and further shield a part of the sidewall of the source/drain metal electrode 36 located in the via hole 37. The first light-shielding structure 38 is disposed to reduce the light ray S1 incident from the substrate 30 side and irradiated to the source/drain metal electrode 36.
Fig. 3B is a schematic top view of fig. 3A, wherein the active layer 32 is a U-shaped channel. The source/drain metal electrode 36 is located in the via hole 37, and the first light shielding structure 38 is disposed between the substrate 30 and the via hole 37, and can shield a portion of the sidewall of the source/drain metal electrode 36 located in the via hole 37, so as to reduce the light ray S1 incident from the substrate 30 side and irradiated to the source/drain metal electrode 36.
The array substrate of the present embodiment has the first light shielding structure 38 disposed between the via hole 37 and the substrate 30, so as to shield the light emitted from the substrate 30 to the sidewall of the via hole 37, i.e., to shield the light S1 emitted to the source/drain metal electrode 36 in the via hole 37, thereby reducing the refraction and reflection phenomenon caused by the light reflected by the source/drain metal electrode 36 in the via hole 37, solving the problem of light leakage without widening the black matrix, and having a high aperture ratio.
According to an exemplary embodiment, as shown in fig. 3C and 3D, the perpendicular projection of the via hole 37 on the substrate base plate 30 is located in the perpendicular projection area 382 of the first light shielding structure 38 on the substrate base plate 30, that is, the first light shielding structure 38 blocks all the via hole 37, so that the light ray S1 emitted from the substrate base plate 30 to the via hole 37 can be completely shielded. The arrangement can shield all the light rays S1 emitted to the via holes 37, avoid the refraction and reflection phenomenon caused by the light rays reflected by the source/drain metal electrodes 36 in the via holes 37, solve the problem of light leakage without widening a black matrix, and have higher aperture opening ratio.
Fig. 4A schematically shows a cross-sectional view of a substrate base plate in another array base plate according to an exemplary embodiment of the present invention, and fig. 4B schematically shows a top view of fig. 4A.
As shown in fig. 4A, an array substrate includes: the substrate 40 includes a thin film transistor on the substrate 40. The thin film transistor includes a buffer layer 41, an active layer 42, a gate insulating layer 43, a gate electrode 44, an interlayer insulating layer 45, a source electrode 461, and a drain electrode 462 in this order. The thin film transistor further includes a first via hole 471 and a second via hole 472, the source electrode 461 has a portion located in the first via hole 471, and the drain electrode 462 has a portion located in the second via hole 472. The dotted lines are vias 471 and 472, and the source electrode 461 and the drain electrode 462 are connected to the source region and the drain region in the active layer 42 through the vias 471 and 472, respectively.
The thin film transistor may further include first light shielding structures 481 and 482, the first light shielding structure 481 is disposed between the first via hole 471 and the substrate base plate 40, and the first light shielding structure 482 is disposed between the second via hole 472 and the substrate base plate 40. The first light shielding structures 481 and 482 are spaced from the substrate base 40 by a distance less than the distance from the vias 471 and 482 to the substrate base 40, i.e., the first light shielding structures 481 and 482 are respectively located between the substrate base 40 and the vias 471 and 482. The vertical projections of the first light shielding structures 481 and 482 on the substrate base plate 40 and the vertical projections of the first via hole 471 and the second via hole 472 on the substrate base plate 40 have an overlapping region 48, that is, when viewed from the direction of the substrate base plate 40, the first light shielding structure 481 can shield part of the sidewall of the first via hole 471, and the first light shielding structure 482 can shield the second via hole 472, so as to shield the source electrode 461 and the drain electrode 462 in the first via hole 471 and the second via hole 472. The first light-shielding structures 481 and 482 are arranged to reduce the light ray S1 incident from the substrate 40 and irradiated to the source electrode 461 and the drain electrode 462.
Fig. 4B is a schematic top view of fig. 4A, wherein the active layer 42 may be a U-shaped channel. The source electrode 461 is located in the via hole 471, and the first light shielding structure 481 is disposed between the substrate 40 and the via hole 471, and can shield a portion of the sidewall of the source electrode 461 located in the via hole 471, so as to reduce the light ray S1 incident from one side of the substrate 40 and irradiating the source electrode 461. Similarly, the drain electrode 462 is located in the via hole 472, and the first light shielding structure 482 is disposed between the substrate 40 and the via hole 472, and can shield the drain electrode 462 located in the via hole 472, so as to shield the light ray S1 incident from the substrate 40 side and irradiated to the drain electrode 462.
According to an example embodiment, the active layer 42 may be polysilicon. The active layer 42 is of a polysilicon structure, and the polysilicon structure has high mobility and strong device driving capability.
According to an example embodiment, the first light shielding structures 481 and 482 may employ a metal material or a black resin material. When the first shading structures 481 and 482 are made of metal materials, the shading effect is good and high temperature resistance is achieved. When the first light-shielding structures 481 and 482 are made of black resin, the first light-shielding structures can be formed by directly using an exposure process, and the process is simple.
According to an example embodiment, as shown in fig. 4A, the substrate 40 further includes a second light shielding structure 49, the second light shielding structure 49 may be disposed on a side of the active layer 42 close to the substrate 40, a vertical projection of the second light shielding structure 49 on the substrate 40 and a vertical projection of the active layer 42 on the substrate 40 have an overlapping region 491, and a vertical projection of the second light shielding structure 49 on the substrate 40 and a vertical projection of the first light shielding structures 481 and 482 on the substrate 40 do not overlap.
That is, a second light shielding structure 49 may be further disposed between the base substrate 40 and the active layer 42, and the second light shielding structure 49 may be disposed below the active layer 42 for shielding the light S2 emitted from the base substrate 40 toward the active layer 42. The regions where the first light shielding structures 481 and 482 do not overlap with the second light shielding structure 49 are separated from each other.
The second light shielding structure 49 is provided under the active layer 42, which can prevent the active layer 42 from being deteriorated due to long-time irradiation of light. In addition, the first light shielding structures 481 and 482 and the second light shielding structure 49 are separately arranged, and the light shielding structures are only arranged at the positions needing light shielding, so that the area of the light shielding metal structures can be further reduced, the aperture opening ratio is increased, and the generated capacitive coupling interference is small.
According to an example embodiment, as shown in fig. 4A, the first light shielding structures 481 and 482 and the second light shielding structure 49 may be located at the same layer.
According to an example embodiment, the first light blocking structures 481 and 482 may be disposed at a side of the buffer layer 41 close to the substrate base plate 40.
If the first light-shielding structures 481 and 482 and the second light-shielding structure 49 are disposed on the same layer, the first light-shielding structures 481 and 482 and the second light-shielding structure 49 are uniformly manufactured without additional processes, thereby preventing light leakage and increasing the aperture ratio without increasing any process.
Fig. 5 schematically illustrates a top view of a substrate base plate in an array base plate according to an exemplary embodiment of the present invention.
As shown in fig. 5, the active layer 52 is a U-shaped channel. The source 561 is located in the via 571, and the first light shielding structure 58 is disposed between the substrate 50 and the via 571, and can shield a portion of the sidewall of the source 561 located in the via 571, so as to reduce light incident from one side of the substrate 50 and irradiating the source 561. Meanwhile, the first light shielding structure 58 is disposed between the first via hole 571 and the second via hole 572, and can shield a portion of the sidewall of the drain electrode 562 located in the via hole 572, so as to shield light incident from the substrate 50 side and irradiating the drain electrode 562.
The first light shielding structure 58 is disposed between the first via 571 and the second via 572, and can simultaneously shield a portion of sidewalls of the source 561 in the first via 571 and a portion of sidewalls of the drain 562 in the second via 572. For the high-resolution array substrate and the display panel, the area of the light-shielding metal block of the first light-shielding structure 58 is small, so that the generated capacitive coupling interference is small, and the aperture ratio is further increased.
Fig. 6 schematically illustrates a top view of a substrate base plate in an array base plate according to an exemplary embodiment of the present invention.
As shown in fig. 6, the active layer 62 is a U-shaped channel. The source 661 is positioned in the via 671, and the first light shielding structure 681 is disposed between the substrate base 60 and the via 671, and has a semicircular shape. It should be noted that there is no overlapping area between the first light shielding structure 681 and the source electrode 661, specifically, the distance between the vertical projection of the first light shielding structure 681 on the substrate 60 and the vertical projection of the source electrode 661 on the substrate 60 is less than or equal to 3 micrometers, which can shield part or all of the light within a range of 3 micrometers from the source electrode, and can be used to reduce the interference between the light incident from the substrate 60 side and the light reflected from the source electrode 661.
It has been found that the light leakage caused by the source 661 in the via 671 is mainly concentrated within a range of 3 micrometers from the edge of the source 661 with the source 661 as the center, and thus, when the distance between the vertical projection of the first light shielding structure 681 on the substrate base 60 and the vertical projection of the source 661 on the substrate base 60 is less than or equal to 3 micrometers, the light leakage phenomenon can be reduced. In addition, the via hole 671 is generally designed to be circular or elliptical, so that the edge of the light leakage region caused by the source 661 in the via hole 671 is also approximately arc-shaped, and the first light shielding structure 681 is configured to be semicircular and can be matched with the edge of the via hole, thereby reducing light leakage and further improving the aperture ratio.
In some embodiments of the present invention, a first light shielding structure 682 may be further disposed between the substrate 60 and the via hole 672, and similarly, the first light shielding structure 682 may be semicircular like the first light shielding structure 681, and a distance between a vertical projection of the first light shielding structure 682 on the substrate 60 and a vertical projection of the drain electrode 662 on the substrate 60 is less than or equal to 3 μm, which can be used to shield light incident from a side of the substrate 60 and interfering with light reflected by the drain electrode 662, thereby reducing light leakage.
In order to better illustrate the position relationship between the first light shielding structure and the drain electrode or/and the source electrode, in the structure shown in fig. 6, there is no overlapping region between the first light shielding structure and the drain electrode or/and the source electrode, that is, there is no overlapping region between the vertical projection of the first light shielding structure on the substrate and the vertical projection of the drain electrode or/and the source electrode on the substrate, but the distance between the vertical projection of the first light shielding structure on the substrate and the vertical projection of the drain electrode or/and the source electrode on the substrate is less than or equal to 3 micrometers. However, in other embodiments of the present invention, when the first light shielding structure has a semicircular shape, a vertical projection of the first light shielding structure on the substrate and a vertical projection of the drain electrode or/and the source electrode on the substrate may have an overlapping region.
The first light shielding structures 681 and 682 of the present embodiment have a semicircular structure, and may have a polygonal shape, such as a rectangle, trapezoid, or pentagon, as long as the first light shielding structures can shield light and increase the aperture ratio, and the present disclosure is not limited thereto.
In this embodiment, the first light-shielding structure 681 or 682 having a semicircular shape is provided toward the opening area of the pixel unit, and the area of the first light-shielding structure 681 or 682 is further reduced to increase the light-transmitting area as much as possible. Moreover, the light shielding structure is manufactured on the thin film transistor, and the alignment precision of the light shielding structure is far higher than that of the color film substrate and the TFT substrate, so that the light shielding precision is high, the width of a black matrix can be further reduced, and the aperture opening ratio is increased.
Fig. 7 schematically illustrates a top view of a substrate base plate in an array base plate according to an exemplary embodiment of the present invention.
As shown in fig. 7, the active layer 72 is a U-shaped channel. The source 761 is positioned in the via 771 and the first light shielding structure 781 is disposed between the substrate 70 and the via 771. The drain 762 is located in the via 772, and the first light shielding structure 782 is disposed between the substrate base plate 70 and the via 772. The array substrate further includes a data line 79 and a scan line 74 crossing each other and insulated from each other, and the data line 79 may be reused as the drain electrode 762. The fabrication process can be further simplified by multiplexing the data line 79 as the drain 762.
According to an example embodiment, the first light shielding structures 781, 782 may be located at the same layer as the scan line 74.
In addition, the invention also provides a preparation method of the array substrate. Fig. 8 is a flowchart schematically illustrating a method of manufacturing an array substrate according to an exemplary embodiment of the present invention.
As shown in fig. 8, a method for manufacturing an array substrate includes:
step S802: a base substrate is provided.
Step S804: a first light shielding structure is formed on a substrate. Specifically, the first light shielding structure may be a metal or a light shielding resin.
Step S806: forming a thin film transistor on a substrate; wherein the thin film transistor includes an active layer, a source electrode, a drain electrode, and a via hole, and the drain electrode or the source electrode has a portion located in the via hole. Specifically, for the thin film transistor with the active layer being the low temperature polysilicon, the insulating layer is formed on the structure formed in step S804, and then the active layer, the insulating layer, the via hole, and the source and drain are sequentially formed.
Step S808: the distance between the first light shielding structure and the substrate base plate is less than that between the via hole and the substrate base plate, and the distance between the vertical projection of the first light shielding structure on the substrate base plate and the vertical projection of the drain electrode or the source electrode on the substrate base plate is less than or equal to 3 micrometers.
In the preparation method, the first light shielding structure and the position relation between the source electrode and the drain electrode are prepared according to the requirement that the distance between the vertical projection of the first light shielding structure on the substrate and the vertical projection of the drain electrode or the source electrode on the substrate is less than or equal to 3 micrometers, so that the formed first light shielding structure can reduce light leakage caused by the source electrode or/and the drain electrode in the via hole in the display process.
According to an example embodiment, a liquid crystal display device includes any one of the array substrates in the foregoing embodiments, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.
In the array substrate, the array substrate preparation method and the liquid crystal display device, the first shading structure is arranged at the position of the via hole or in the peripheral area of the via hole and on one side close to the light source, so that light leakage caused by reflection, refraction and the like of the source electrode or the drain electrode in the via hole to light rays can be effectively reduced. In the prior art, the black matrix on the color filter substrate or the counter substrate is widened to block light leakage caused by the source or the drain in the via hole, but this method may cause a decrease in the aperture ratio. Because the propagation direction of the light causing light leakage and the normal direction of the array substrate form an included angle, and the light leakage area is enlarged in the process of transmitting the light from the light source side to the color film substrate or the opposite substrate, in the embodiment of the invention, the first light shielding structure has a smaller area than a black matrix which is arranged on the color film substrate or the opposite substrate to shield the light leakage while achieving the same light shielding effect, so compared with the prior art, the array substrate preparation method and the liquid crystal display device provided by the embodiment of the invention have higher aperture opening ratio while preventing the light leakage and have better display effect.
Exemplary embodiments of the present disclosure are specifically illustrated and described above. It is to be understood that the invention is not limited to the precise construction, arrangements, or instrumentalities described herein; on the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (15)
1. An array substrate, comprising:
a substrate base plate;
a thin film transistor on the substrate, the thin film transistor including an active layer, a source electrode, a drain electrode, and a via hole, and the drain electrode or the source electrode having a portion in the via hole, the thin film transistor further including:
the distance between the first shading structure and the substrate base plate is smaller than that between the via hole and the substrate base plate, and the distance between the vertical projection of the first shading structure on the substrate base plate and the vertical projection of the drain electrode or the source electrode on the substrate base plate is smaller than or equal to 3 micrometers.
2. The array substrate of claim 1, wherein a perpendicular projection of the first light blocking structure on the substrate has an overlapping area with a perpendicular projection of the via on the substrate.
3. The array substrate of claim 2, wherein the vias include a first via and a second via, the source has a portion located in the first via, the drain has a portion located in the second via, and the first light blocking structure is disposed between the first via and the second via, respectively, and the substrate.
4. The array substrate of any one of claims 1-3, wherein the first light blocking structure is polygonal or semicircular.
5. The array substrate of any one of claims 1-3, wherein a perpendicular projection of the via on the substrate is located within a perpendicular projection area of the first light shielding structure on the substrate.
6. The array substrate of any one of claims 1-3, wherein the active layer is polysilicon.
7. The array substrate of claim 6, further comprising a second light shielding structure disposed on a side of the active layer adjacent to the substrate, wherein a vertical projection of the second light shielding structure on the substrate has an overlapping region with a vertical projection of the active layer on the substrate, and wherein a vertical projection of the second light shielding structure on the substrate does not overlap with a vertical projection of the first light shielding structure on the substrate.
8. The array substrate of claim 7, wherein the first light blocking structure and the second light blocking structure are located on the same layer.
9. The array substrate of claim 6, wherein the active layer comprises a channel region, and wherein the channel region is U-shaped.
10. The array substrate of any one of claims 1-3, wherein the first light blocking structure is a metal material or a black resin material.
11. The array substrate of any one of claims 1-3, further comprising a buffer layer, wherein the first light blocking structure is disposed on a side of the buffer layer adjacent to the substrate.
12. The array substrate according to any one of claims 1 to 3, wherein the array substrate further comprises data lines and scan lines crossing each other and arranged in an insulating manner, and the data lines are multiplexed as the drain electrodes.
13. The array substrate of claim 12, wherein the first light blocking structure is located on the same layer as the scan line.
14. A method for preparing the array substrate of claim 1, comprising:
providing a substrate base plate;
forming a first light shielding structure on the substrate base plate;
forming a thin film transistor on the substrate base plate; wherein,
the thin film transistor includes an active layer, a source electrode, a drain electrode, and a via hole, and the drain electrode or the source electrode has a portion located in the via hole;
the distance from the first shading structure to the substrate base plate is smaller than the distance from the via hole to the substrate base plate, and the distance between the vertical projection of the first shading structure on the substrate base plate and the vertical projection of the drain electrode or the source electrode on the substrate base plate is smaller than or equal to 3 micrometers.
15. A liquid crystal display device comprising the array substrate according to any one of claims 1 to 13, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
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