CN106130560A - It is applied to the integrator with the sigma delta analog-to-digital conversion circuit of DAC function - Google Patents
It is applied to the integrator with the sigma delta analog-to-digital conversion circuit of DAC function Download PDFInfo
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- CN106130560A CN106130560A CN201610454408.5A CN201610454408A CN106130560A CN 106130560 A CN106130560 A CN 106130560A CN 201610454408 A CN201610454408 A CN 201610454408A CN 106130560 A CN106130560 A CN 106130560A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
- H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
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Abstract
The invention discloses the integrator of a kind of sigma delta analog-to-digital conversion circuit being applied to have DAC function, this integrator circuit includes sampling capacitance, 2 integrating capacitors, 1 operational amplifier, switches set；Described sampling capacitance has two groups, one group of concatenation operation amplifier positive input terminal, one group of concatenation operation amplifier negative input end；2 integrating capacitors, are connected to positive input terminal and the negative input end of operational amplifier respectively；Described switches set is arranged between operational amplifier and sample circuit, between sampling capacitance and input signal, and between sampling capacitance and integrator common-mode voltage.This integrator can accurately measure the size of the variable quantity of measured signal, it is also possible to measures the size of the absolute value of measured signal.
Description
Technical field
The invention belongs to the technical field of electronics, the integrator that special switched-capacitor circuit realizes.
Background technology
Integrator circuit is the ingredient being applied to sigma delta analog-digital converter (sigma-delta ADC).
Sigma delta analog-digital converter is proportion measurement, and the input signal that will simulate is multiplied by gain A, with the reference voltage of simulation
Ratio be converted to the analog-digital conversion process of digital signal of n-bit.In the past, find many times during analogue signal is measured
The change amount signal of the very big the most often measured signal of the signal of measured signal itself is the least, and ADC is in order to realize measured signal
Accurately measuring of small change amount need to spend bigger cost.
Such as patent application 201110047941.7 discloses the integrator of a kind of Differential Input, includes differential signal source
Vin, operational amplifier A 1, A2 and instrument amplifier A3, the two ends of differential signal source Vin are by difference after wire series resistor R
Accessing operational amplifier A 1, the reverse input end of A2, operational amplifier A 1, the outfan of A2 divide after passing through wire series resistor R1
Not Jie Ru the reverse input end of instrument amplifier A3 and positive input, defeated as resultant signal of the outfan of instrument amplifier A3
Go out end；Between positive input and the outfan of operational amplifier A 1 and the positive input of operational amplifier A 2 and outfan
Between respectively and be connected to electric capacity C.
Although this application can suppress the integrator drift caused by common-mode voltage, it is to be come in fact by multiple operational amplifiers
Existing, integral measurement has certain accuracy, but sometimes and unreliable, and hardware cost is higher.
Summary of the invention
For solving the problems referred to above, it is an object of the invention to provide a kind of Sigma's Dare being applied to there is DAC function
The integrator of tower analog-to-digital conversion circuit, this integrator can accurately measure the size of the variable quantity of measured signal, it is also possible to surveys
Measure the size of the absolute value of measured signal.
For achieving the above object, technical scheme is as follows.
A kind of integrator being applied to there is the sigma delta analog-to-digital conversion circuit of DAC function, it is characterised in that should
Integrator circuit includes sampling capacitance, 2 integrating capacitors, 1 operational amplifier, switches set；Described sampling capacitance has two groups,
One group of concatenation operation amplifier positive input terminal, one group of concatenation operation amplifier negative input end；2 integrating capacitors, are connected to fortune respectively
Calculate positive input terminal and the negative input end of amplifier；Described switches set is arranged between operational amplifier and sample circuit, sampling electricity
Hold between input signal, and between sampling capacitance and integrator common-mode voltage.
Described sampling capacitance, includes 2*n sampling capacitance, and the most often group sampling capacitance includes n, n sampling capacitance
It is together in series, is connected on operational amplifier.
Described switches set, includes a plurality of sampling switch and a plurality of control switch.
Described sampling switch, wherein three sampling switch are series at a sampling capacitance, and these three sampling switch connects respectively
It is connected to VIP input signal anode or the negative terminal of VIN input signal, the anode REFP of reference voltage and and the negative terminal of reference voltage
REFN；Described control switchs, and is arranged between each sampling capacitance and operational amplifier, and integrator common-mode voltage is electric with sampling
Between appearance.
Further, described sampling capacitance is divided into the n such as n anode signal sampling electric capacity and Cs21～Cs2n such as Cs11～Cs1n
Individual negative terminal signal sampling electric capacity, wherein (x=1, the top crown of 2 ..., n) anode signal sampling electric capacity connect 21,23 and open Cs1x
Close, Cs1x (x=1,2 ..., n) anode signal sampling electric capacity bottom crown correspondence connect 1x1 (x=1,2 ..., n), 1x2 (x=
1,2 ..., n), 1x3 (x=1,2 ..., n) three switch；Cs2x (x=1, the top crown of 2 ..., n) negative terminal signal sampling electric capacity
Connect 22,24 switch, Cs2x (x=1,2 ..., n) negative terminal signal sampling electric capacity bottom crown correspondence connect 2x1 (x=1,2 ...,
N), 2x2 (x=1,2 ..., n), 2x3 (x=1,2 ..., n) three switch.1x1 (x=1,2 ..., other end connection n) switched
The anode Vip, 2x1 of input signal (x=1,2 ..., the other end that n) switchs connect input signal negative terminal Vin, 1x2 (x=1,
2 ..., n), 2x2 (x=1,2 ..., the other end that n) switchs connect reference voltage anode REFP, 1x3 (x=1,2 ..., n),
(x=1,2 ..., the other end that n) switchs connect the negative terminal REFN of reference voltage to 2x3, and the other ends of 21,22 switches connect integration
Device common-mode voltage VCM.
Described sampling switch and control switch, controlled by non-overlapping clock, including Ф 1 and Ф 2, Ф 1s and Ф 2s.
Described sampling switch and control switch also can be switched by single PMOS or NMOS tube, CMOS tube etc. and realize.
Described integrating capacitor is divided into anode integrating capacitor and each one of negative terminal integrating capacitor, and wherein anode integrating capacitor is upper
Pole plate connects the other end, the positive input terminal of amplifier controlling to switch, and the bottom crown of anode integrating capacitor connects integrator positive output
End Vop, the negative output terminal of amplifier；The top crown of negative terminal integrating capacitor connects the other end, the negative input end of amplifier controlling to switch,
The bottom crown of negative terminal integrating capacitor connects integrator negative output terminal Von, the positive output end of amplifier.
Operation principle is:
Sampling phase: Ф 1 and Ф 1S opens switch.(x=1, the voltage of 2 ..., n) sampling capacitance two ends are Vip to Cs1x respectively
And VCM, Cs2x (x=1, the voltage of 2 ..., n) sampling capacitance two ends are Vin and VCM respectively.
Integration phase: Ф 2 and Ф 2S opens switch and (opens for two of Cs1x2 and Cs1x3 that each sampling capacitance Cs1x is corresponding
Close, or two switches of Cs2x2 and Cs2x3 corresponding to sampling capacitance Cs2x, only understand and open one of them according to the value of DAC).
Cs1x (x=1, the voltage of 2 ..., n) sampling capacitance two ends be respectively REFP (or REFN) and VCM, Cs2x (x=1,
2 ..., n) voltage at sampling capacitance two ends be REFN (or REFP) and VCM respectively.
So integration is after integration, and integrator output voltage difference is: (assume have m electric capacity to connect in n electric capacity of anode
REFP, has n-m electric capacity to meet REFN, has m electric capacity to meet REFN, have n-m electric capacity to meet REFP, m=in corresponding n electric capacity of negative terminal
0、1、2、…、n)
(n*(Vip-VCM)-(m*(REFP-VCM)+(n-m)*(REFN-VCM))-
n*(Vin-VCM)+(m*(REFN-VCM)+(n-m)*(REFP-VCM)))/Ch
=(n* (Vip-Vin)+(n-2m) * (REFP-REFN))/Ch
=((Vip-Vin)+((n-2m)/n) * (REFP-REFN)) * n/Ch.
When m=0,1,2 ..., n, then:
M=0:=((Vip-Vin)+(REFP-REFN)) * n/Ch；
M=1:=((Vip-Vin)+((n-2)/n) * (REFP-REFN)) * n/Ch；
M=2:=((Vip-Vin)+((n-4)/n) * (REFP-REFN)) * n/Ch；
…
M=n/2:=(Vip-Vin) * n/Ch；
…
M=n:=((Vip-Vin)-(REFP-REFN)) * n/Ch.
So integrator be achieved that differential signal deduct/plus the value of DAC of a reference voltage (REFP-REFN).
ADC value through sigma-deltaADC conversion output is:
((Vip-Vin)+(1-2m/n)*(REFP-REFN))/(REFP-REFN)
The value that so ADC is converted to is to carry out ADC conversion again after measured signal is preceded by a DAC signal.
This DAC signal is: (1-2m/n) * (REFP-REFN)/(REFP-REFN).
The resolution of DAC is: Log (n)/log2.
The present invention by the way, can accurately measure the size of the variable quantity of measured signal, it is also possible to measures
Go out the size of the absolute value of measured signal.
Accompanying drawing explanation
Fig. 1 is the integrator in the sigma-Delta analog-to-digital converter circuit of the band DAC function that the present invention is implemented
The circuit diagram of (fully differential signal input and output).
Fig. 2 is the integrator control in the sigma-Delta analog-to-digital converter circuit of the band DAC function that the present invention is implemented
The phase diagram of system switch clock used.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, right
The present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, and
It is not used in the restriction present invention.
Fig. 1 represents according to the integrator in the sigma-Delta analog-to-digital converter circuit realizing band DAC function stated.
In Fig. 1, the integrator circuit in the sigma-Delta analog-to-digital converter circuit realizing band DAC function is used to include: sampling electricity
Hold Cs11, Cs12 ..., Cs1n, Cs21, Cs22 ..., Cs2n, operational amplifier 30, integrating capacitor 33,34, switch 1x1 (x=
1,2 ..., n), 1x2 (x=1,2 ..., n), 1x3 (x=1,2 ..., n), 2x1 (x=1,2 ..., n), 2x2 (x=1,2 ...,
N), 2x3 (x=1,2 ..., n), 21,22,23,24.
Fig. 2 represents each phase clock explanation of integrator circuit breaker in middle, as follows:
Clock ф 1 phaseswitch 21,22 is opened.
Clock ф 2 phaseswitch 23,24 is opened.
Clock ф 1s phaseswitch 1x1 (x=1,2 ..., n), 2x1 (x=1,2 ..., n) opens.
Clock ф 2s phaseswitch 1x2 (x=1,2 ..., n) or 1x3 (x=1,2 ..., n), 2x2 (x=1,2 ..., n) or
2x3 (x=1,2 ..., n) opens.
The connection of switched-capacitor circuit is as follows:
Cs1x (x=1, the top crown of 2 ..., n) anode signal sampling electric capacity connect 21,23 and switch, Cs1x (x=1,
2 ..., n) anode signal sampling electric capacity bottom crown correspondence connect 1x1 (x=1,2 ..., n), 1x2 (x=1,2 ..., n), 1x3
(x=1,2 ..., n) three switch；Cs2x (x=1, the top crown of 2 ..., n) negative terminal signal sampling electric capacity connect 22,24 switches,
Cs2x (x=1,2 ..., n) negative terminal signal sampling electric capacity bottom crown correspondence connect 2x1 (x=1,2 ..., n), 2x2 (x=1,
2 ..., n), 2x3 (x=1,2 ..., n) three switch.(x=1,2 ..., the other end that n) switchs just are connecting input signal to 1x1
End Vip, 2x1 (x=1,2 ..., the other end that n) switchs connect input signal negative terminal Vin, 1x2 (x=1,2 ..., n), 2x2
(x=1,2 ..., the other end that n) switchs connect reference voltage anode REFP, 1x3 (x=1,2 ..., n), 2x3 (x=1,
2 ..., the other end that n) switchs connect the negative terminal REFN of reference voltage, the other ends of 21,22 switches connect integrator common-mode voltage
VCM。
Integrating capacitor is divided into 33 anode integrating capacitors and each one of 34 negative terminal integrating capacitors.Wherein 33 anode integrating capacitors
Top crown connects the other end of 23 switches, the positive input terminal of 30 amplifiers, and the bottom crown of 33 anode integrating capacitors is just connecting integrator
Output end vo p, the negative output terminal of 30 amplifiers；The top crown of 34 negative terminal integrating capacitors connects the other ends of 24 switches, 30 amplifiers
Negative input end, the bottom crown of 34 negative terminal integrating capacitors connects integrator negative output terminal Von, the positive output end of 30 amplifiers.
It addition, switch is controlled by 2 groups of non-overlapping clocks, including Ф 1 and Ф 2, Ф 1s and Ф 2s, as shown in Figure 2.
Integrator to realize process as follows:
Within an integrator cycle:
Sampling phase: Ф 1 and Ф 1S opens switch.(x=1, the voltage of 2 ..., n) sampling capacitance two ends are Vip to Cs1x respectively
And VCM, Cs2x (x=1, the voltage of 2 ..., n) sampling capacitance two ends are Vin and VCM respectively.
Integration phase: Ф 2 and Ф 2S opens switch and (opens for two of Cs1x2 and Cs1x3 that each sampling capacitance Cs1x is corresponding
Close, or two switches of Cs2x2 and Cs2x3 corresponding to sampling capacitance Cs2x, only understand and open one of them according to the value of DAC).
Cs1x (x=1, the voltage of 2 ..., n) sampling capacitance two ends be respectively REFP (or REFN) and VCM, Cs2x (x=1,
2 ..., n) voltage at sampling capacitance two ends be REFN (or REFP) and VCM respectively.
So integration is after integration, and integrator output voltage difference is: (assume have m electric capacity to connect in n electric capacity of anode
REFP, has n-m electric capacity to meet REFN, has m electric capacity to meet REFN, have n-m electric capacity to meet REFP, m=in corresponding n electric capacity of negative terminal
0、1、2、…、n)
(n*(Vip-VCM)-(m*(REFP-VCM)+(n-m)*(REFN-VCM))-
n*(Vin-VCM)+(m*(REFN-VCM)+(n-m)*(REFP-VCM)))/Ch
So integrator be achieved that differential signal deduct/plus the value of DAC of a reference voltage (REFP-REFN).
ADC value through sigma-deltaADC conversion output is:
((Vip-Vin)+(1-2m/n)*(REFP-REFN))/(REFP-REFN)
The value that so ADC is converted to is to carry out ADC conversion again after measured signal is preceded by a DAC signal.
This DAC signal is: (1-2m/n) * (REFP-REFN)/(REFP-REFN).
The resolution of DAC is: Log (n)/log2.
The present invention can apply in sigma delta modulator, it is possible to achieve is very big in measured signal, but quilt
Survey the accurate measurement that change amount signal is less, i.e. can accurately measure the size of the variable quantity of measured signal, it is also possible to measure
Go out the size of the absolute value of measured signal.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Any amendment, equivalent and the improvement etc. made within god and principle, should be included within the scope of the present invention.
Claims (7)
1. the integrator being applied to there is the sigma delta analog-to-digital conversion circuit of DAC function, it is characterised in that this amasss
Device circuit is divided to include sampling capacitance, 2 integrating capacitors, 1 operational amplifier, switches set；Described sampling capacitance has two groups, and one
Group concatenation operation amplifier positive input terminal, one group of concatenation operation amplifier negative input end；2 integrating capacitors, are connected to computing respectively
The positive input terminal of amplifier and negative input end；Described switches set is arranged between operational amplifier and sample circuit, sampling capacitance
And between input signal, and between sampling capacitance and integrator common-mode voltage.
It is applied to the integrator with the sigma delta analog-to-digital conversion circuit of DAC function the most as claimed in claim 1, its
Being characterised by described sampling capacitance, include 2*n sampling capacitance, the most often group sampling capacitance includes n, n sampling capacitance
It is together in series, is connected on operational amplifier.
It is applied to the integrator with the sigma delta analog-to-digital conversion circuit of DAC function the most as claimed in claim 1, its
It is characterised by described switches set, includes a plurality of sampling switch and a plurality of control switch.
It is applied to the integrator with the sigma delta analog-to-digital conversion circuit of DAC function the most as claimed in claim 3, its
Being characterised by described sampling switch, wherein three sampling switch are series at a sampling capacitance, and these three sampling switch connects respectively
It is connected to VIP input signal anode or the negative terminal of VIN input signal, the anode REFP of reference voltage and and the negative terminal of reference voltage
REFN；Described control switchs, and is arranged between each sampling capacitance and operational amplifier, and integrator common-mode voltage is electric with sampling
Between appearance.
It is applied to the integrator with the sigma delta analog-to-digital conversion circuit of DAC function the most as claimed in claim 4, its
It is characterised by that described sampling capacitance is divided into n negative terminal of n anode signal sampling electric capacity and Cs21～Cs2n etc. such as Cs11～Cs1n
Signal sampling electric capacity, wherein (x=1, the top crown of 2 ..., n) anode signal sampling electric capacity connect 21,23 switches, Cs1x to Cs1x
(x=1,2 ..., n) anode signal sampling electric capacity bottom crown correspondence connect 1x1 (x=1,2 ..., n), 1x2 (x=1,2 ...,
N), 1x3 (x=1,2 ..., n) three switch；Cs2x (x=1,2 ..., n) negative terminal signal sampling electric capacity top crown connect 22,
24 switch, Cs2x (x=1,2 ..., n) negative terminal signal sampling electric capacity bottom crown correspondence connect 2x1 (x=1,2 ..., n), 2x2
(x=1,2 ..., n), 2x3 (x=1,2 ..., n) three switch.1x1 (x=1,2 ..., other end connection input letter n) switched
Number anode Vip, 2x1 (x=1,2 ..., the other end that n) switchs connect input signal negative terminal Vin, 1x2 (x=1,2 ...,
N), 2x2 (x=1,2 ..., the other end that n) switchs connect reference voltage anode REFP, 1x3 (x=1,2 ..., n), 2x3 (x
=1,2 ..., the other end that n) switchs connect the negative terminal REFN of reference voltage, and the other ends of 21,22 switches connect integrator common mode
Voltage VCM.
It is applied to the integrator with the sigma delta analog-to-digital conversion circuit of DAC function the most as claimed in claim 3, its
It is characterised by described sampling switch and controls switch, being controlled by non-overlapping clock, including Ф 1 and Ф 2, Ф 1s and Ф 2s.
It is applied to the integrator with the sigma delta analog-to-digital conversion circuit of DAC function the most as claimed in claim 1, its
Being characterised by that described integrating capacitor is divided into anode integrating capacitor and each one of negative terminal integrating capacitor, wherein anode integrating capacitor is upper
Pole plate connects the other end, the positive input terminal of amplifier controlling to switch, and the bottom crown of anode integrating capacitor connects integrator positive output
End Vop, the negative output terminal of amplifier；The top crown of negative terminal integrating capacitor connects the other end, the negative input end of amplifier controlling to switch,
The bottom crown of negative terminal integrating capacitor connects integrator negative output terminal Von, the positive output end of amplifier.
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| CN201610454408.5A CN106130560B (en) | 2016-06-21 | 2016-06-21 | Integrator applied to sigma delta analog-to-digital conversion circuit with DAC function |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983863A (en) * | 2012-12-18 | 2013-03-20 | 天津大学 | First-stage circuit structure of pipelined analog-to-digital converter |
| CN103067015A (en) * | 2012-12-20 | 2013-04-24 | 天津大学 | Circulation analog-digital converter and conversion method for complementary metal oxide semiconductor (CMOS) image sensor |
| US9019137B1 (en) * | 2014-01-17 | 2015-04-28 | IQ-Analog Corporation | Multiplying digital-to-analog converter |
| CN104901700A (en) * | 2015-05-12 | 2015-09-09 | 清华大学 | Fully digital Sigma-Delta modulator based on phase inverter |
-
2016
- 2016-06-21 CN CN201610454408.5A patent/CN106130560B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983863A (en) * | 2012-12-18 | 2013-03-20 | 天津大学 | First-stage circuit structure of pipelined analog-to-digital converter |
| CN103067015A (en) * | 2012-12-20 | 2013-04-24 | 天津大学 | Circulation analog-digital converter and conversion method for complementary metal oxide semiconductor (CMOS) image sensor |
| US9019137B1 (en) * | 2014-01-17 | 2015-04-28 | IQ-Analog Corporation | Multiplying digital-to-analog converter |
| CN104901700A (en) * | 2015-05-12 | 2015-09-09 | 清华大学 | Fully digital Sigma-Delta modulator based on phase inverter |
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