CN106129062A - The manufacture method of insulating barrier, the manufacture method of array base palte and array base palte - Google Patents
The manufacture method of insulating barrier, the manufacture method of array base palte and array base palte Download PDFInfo
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- CN106129062A CN106129062A CN201610513994.6A CN201610513994A CN106129062A CN 106129062 A CN106129062 A CN 106129062A CN 201610513994 A CN201610513994 A CN 201610513994A CN 106129062 A CN106129062 A CN 106129062A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Abstract
The present invention discloses the manufacture method of a kind of insulating barrier, the manufacture method of array base palte and array base palte, and wherein the manufacture method of insulating barrier includes step: deposit an insulating barrier on substrate；Insulating barrier being exposed development treatment, forms the first opening and the second opening at insulating barrier, wherein the first opening is positioned at the first area of insulating barrier, and the second opening is positioned at second area；By light shield, the first area of insulating barrier is carried out photocuring process；Insulating barrier is carried out the high temperature anneal.On the insulating barrier that the manufacture method of the employing present invention obtains, the first opening part insulating barrier is difficult to flow deformation problem occur.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to the manufacture of the manufacture method of a kind of insulating barrier, array base palte
Method and array base palte.
Background technology
Liquid crystal panel has been widely used in people's daily life and work as main flow display floater, and liquid crystal panel is usual
Circuit control is carried out, to realize display by array base palte.Would generally use organic insulator in array base palte, it can reduce
Parasitic capacitance between metal electrode, to reduce the power consumption of panel, it may also be used for makes each film layer more planarize, thus improves
The dark-state of Display panel, improves the contrast of display.
In prior art, the serious deformation that the opening that insulating barrier is formed would generally occur, it is easily caused opening quilt
Block, the problem that insulating barrier resolution declines.And array base palte is generally divided into the join domain of viewing area and circuit, in display
Region part, the shedding deformation problem of insulating barrier can cause display effect the best.
Summary of the invention
It is an object of the invention to provide the manufacture method of a kind of insulating barrier, the manufacture method of array base palte and array base
Plate, the problem causing display effect the best to solve insulating layer openings in prior art to be easily deformed.
For solving the problems referred to above, the present invention proposes the manufacture method of a kind of insulating barrier, and described manufacture method includes following step
Rapid: on substrate, to deposit an insulating barrier；Described insulating barrier is exposed development treatment, forms the first opening at described insulating barrier
With the second opening, wherein said first opening is positioned at the first area of described insulating barrier, and described second opening is positioned at described insulation
The second area of layer；By light shield, the first area of described insulating barrier is carried out photocuring process；Described insulating barrier is carried out height
Temperature annealing.
Wherein, the described step first area of described insulating barrier being carried out photocuring process by light shield includes: pass through
Light shield carries out ultraviolet curing process to described first area.
Wherein, include after the described step depositing an insulating barrier on substrate: will there is the substrate of insulating barrier in vacuum
Middle placement a period of time.
Wherein, include after the described step depositing an insulating barrier on substrate: described insulating barrier is carried out baking process.
Wherein, the inclination angle of described first opening is more than the inclination angle of described second opening, and described first area is display
Region, described second area is join domain.
For solving the problems referred to above, the present invention provides the manufacture method of a kind of array base palte, described manufacture method to include step:
Substrate is formed insulating barrier；Described insulating barrier is formed pixel electrode layer；The described step forming insulating barrier on substrate
Including: on substrate, deposit an insulating barrier；Described insulating barrier is exposed development treatment, forms first at described insulating barrier and open
Mouthful and the second opening, wherein said first opening is positioned at the first area of described insulating barrier, described second opening be positioned at described absolutely
The second area of edge layer；By light shield, the first area of described insulating barrier is carried out photocuring process；Described insulating barrier is carried out
The high temperature anneal；The described step forming pixel electrode layer on described insulating barrier includes: in the firstth district of described insulating barrier
Territory forms described pixel electrode layer.
Wherein, the described step first area of described insulating barrier being carried out photocuring process by light shield includes: pass through
Light shield carries out ultraviolet curing process to described first area.
Wherein, the described step forming pixel electrode layer on described insulating barrier includes: deposit one on described insulating barrier
Pixel electrode layer；Described pixel electrode layer is exposed development treatment, removes the picture of deposition on described insulating barrier second area
Element electrode layer.
Wherein, the step after described deposition one insulating barrier includes: described insulating barrier is carried out baking process.
For solving the problems referred to above, the present invention also provides for a kind of array base palte, and this array base palte is prepared by above-mentioned manufacture method.
The manufacture method of insulating barrier of the present invention includes step: deposits an insulating barrier on substrate, is exposed insulating barrier
Development treatment, forms the first opening and the second opening at insulating barrier, and the first opening is positioned at the first area of insulating barrier, the second opening
It is positioned at the second area of insulating barrier, by light shield, the first area of insulating barrier is carried out photocuring process, insulating barrier is carried out height
Temperature annealing.For the first opening of first area, before high annealing, carry out photocuring process so that first area
The problem that first opening part insulating barrier is difficult to flow deformation occur.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of manufacture method one embodiment of insulating barrier of the present invention；
Fig. 2 be insulating barrier shown in Fig. 1 manufacture method one embodiment in insulating barrier ratio before and after the high temperature anneal
Relatively schematic diagram；
Fig. 3 is the schematic flow sheet of manufacture method one embodiment of array base palte of the present invention；
Fig. 4 is the structural representation of array base palte that manufacture method one embodiment of array base palte shown in Fig. 3 prepares；
Fig. 5 be array base palte shown in Fig. 3 manufacture method one embodiment in array base corresponding to insulating barrier second area
The top view of plate；
Fig. 6 be array base palte shown in Fig. 3 manufacture method one embodiment in different inclination angle the second opening on pixel
Electrode layer removes the comparison schematic diagram of situation；
Fig. 7 is the structural representation of array base palte one embodiment of the present invention.
Detailed description of the invention
For making those skilled in the art be more fully understood that technical scheme, below in conjunction with the accompanying drawings and be embodied as
The manufacture method of a kind of insulating barrier, the manufacture method of array base palte and the array base palte that invention is provided is done the most in detail by mode
Thin description.
Refer to the schematic flow sheet that Fig. 1 and Fig. 2, Fig. 1 are manufacture method one embodiments of insulating barrier of the present invention, Fig. 2
It it is insulating barrier comparison schematic diagram before and after the high temperature anneal in manufacture method one embodiment of insulating barrier shown in Fig. 1.
The manufacture method of present embodiment insulating barrier comprises the following steps.
S101: deposit an insulating barrier on substrate.
The manufacture of present embodiment insulating barrier 21 is a technique during array base palte manufactures, and in this step, substrate 20 is not
Refer to a certain layer single in array base palte, and refer to the generalized concept of glass substrate, metal level etc..Insulating barrier in this step
21 are formed on the base plate 20 by chemical vapour deposition technique.
Chemical gaseous phase deposition typically has the volatilisation step of solvent, present embodiment will deposited the substrate of insulating barrier 21
20 place a period of time in vacuum, to accelerate the volatilization of solvent, also further insulating barrier 21 can be carried out baking process, or
Directly carry out baking process in a vacuum.
S102: insulating barrier is exposed development treatment.
In this step S102, utilize light shield that insulating barrier 21 is exposed development treatment, obtain corresponding with mask pattern
The insulating barrier 21 of patterning, i.e. forms the first opening 211 and the second opening 212 on insulating barrier 21.First opening 211 is positioned at absolutely
The first area 213 of edge layer 21, the second opening 212 is positioned at the second area 214 of insulating barrier 21.
In present embodiment, insulating barrier 21 is minus, i.e. uses the light shield covering the first opening 211 and the second opening 212 real
Showing exposure imaging, the first opening 211 and the second opening 212 that are not shone by light are etched, and other parts shone by light are then
There is slight cross-linking reaction.
S103: the first area of insulating barrier is carried out photocuring process by light shield.
This step S103 carries out ultraviolet curing process by light shield to described first area 213 so that have first
Insulating barrier 21 first area 213 of opening 211 further crosslinks reaction, and first area 213 can further be consolidated
Change, be not susceptible to Deformation Flow.
S104: insulating barrier is carried out the high temperature anneal.
The high temperature anneal in this step S104 makes insulating barrier 20 full cross-linked, and due to the most right in step S103
Certain solidification has been done in first area 213, and therefore the high temperature in this step S104 is less on the impact of first area 213, makes
Insulating layer material deformation backflow at one opening 211 becomes slight, thus reduces the problems such as the first opening 211 blocking.
And for second area 214, for open at the light shield correspondence first area 213 in present embodiment step S103,
Permission light irradiates, and corresponding to being to cover at second area 214, does not allow light to irradiate；Therefore by light in step S103
The first area 213 being irradiated to solidifies through slight solidification and the further of step S103 of step S102, and is not irradiated by light
Second area 214 there is slight solidification the most in step s 102.
Therefore, after the high temperature anneal of step S104, it is difficult to that through the first area 213 of twice solidification backflow occurs
Deformation, and the second area 214 merely through one-step solidification is susceptible to backflow deformation.In Fig. 2, (A) is high annealing front insulation layer
Shape, the shape of insulating barrier after (B) is high annealing in Fig. 2, as can be seen from Figure, after the high temperature anneal, first
Opening occurs that backflow deformation occur in deformation, the second opening 212 hardly；The inclination angle A of the first opening 211 is more than the second opening
The inclination angle B of 212.
In present embodiment, first area 213 is positioned at viewing area；Second area 214 is positioned at join domain, the i.e. second district
Territory 214 is positioned at the join domain connecting external drive IC, even if therefore the second opening 212 occurs that backflow deformation does not interferes with yet
Display.
It is to be appreciated that the light shield in above-mentioned steps S103 and S102 is respectively different light shields.For Fig. 2, in Fig. 2 only
Representing first area 213 and the insulating barrier situation of second area 214, in the case of between two regions, the description in Fig. 2 is not
It is construed as limiting, can be according to practical situation design the 3rd opening etc..
The manufacture method of insulating barrier of the present invention includes step: deposits an insulating barrier on substrate, is exposed insulating barrier
Development treatment, forms the first opening and the second opening at insulating barrier, and the first opening is positioned at the first area of insulating barrier, the second opening
It is positioned at the second area of insulating barrier, by light shield, the first area of insulating barrier is carried out photocuring process, insulating barrier is carried out height
Temperature annealing.For the first opening of first area, before high annealing, carry out photocuring process so that first area
The problem that first opening part insulating barrier is difficult to flow deformation occur.
Further, during insulating barrier is carried out photocuring process, light shield is utilized to make second area that light not occur
Solidification, first area is different from second area state of cure, and therefore during the high temperature anneal, the first opening and second is opened
Can there is deformation backflow in various degree in mouth so that the different openings on same insulating barrier can have different inclinations angle.
Refer to the schematic flow sheet that Fig. 3 and Fig. 4, Fig. 3 are manufacture method one embodiments of array base palte of the present invention, figure
4 is the structural representation of array base palte that manufacture method one embodiment of array base palte shown in Fig. 3 prepares.
The manufacture method of present embodiment array base palte mainly includes forming insulating barrier and forming pixel on the insulating layer
Electrode layer, comprises the following steps specifically.
S301: deposit an insulating barrier on substrate.
Present embodiment uses on the substrate 40 chemical gaseous phase deposit an insulating barrier 41, and insulating barrier 41 will be deposited
Substrate 40 is positioned in vacuum the volatilization accelerating solvent, insulating barrier 41 also can carry out baking process, or directly enter in a vacuum
Row baking process.
S302: insulating barrier is exposed development treatment.
Forming the first opening 411 and the second opening 412 on insulating barrier 41, wherein the first opening 411 is positioned at insulating barrier 41
First area 413, the second opening 412 is positioned at the second area 414 of insulating barrier 41.
S303: the first area of insulating barrier is carried out photocuring process by light shield.
By light shield, first area 413 is carried out ultraviolet curing process.
S304: insulating barrier is carried out the high temperature anneal.
Above-mentioned steps S301-S304 is similar with step S101-S104 in above-mentioned embodiment method for fabricating insulating layer, tool
Body repeats no more.
S305: form pixel electrode layer on the insulating layer.
This step S305 achieves and forms pixel electrode layer 42 in the first area 413 of insulating barrier 41.
For being positioned at the second area 414 of join domain, then need not form pixel electrode layer 42.Specifically refer to Fig. 5,
Fig. 5 be array base palte shown in Fig. 3 manufacture method one embodiment in the vertical view of array base palte corresponding to insulating barrier second area
Figure.
Wherein join domain is provided with bonding jumper 43, is used for connecting external drive IC.For preventing bonding jumper 43 oxidized, meeting
Bonding jumper 43 also covers pixel electrode layer 42.Pixel electrode layer 42 typically use non-oxidizability preferable MoTi alloy or
ITO。
Therefore the detailed process forming pixel electrode layer in this step S305 is: first deposit a picture on insulating barrier 41
Element electrode layer 42；Then pixel electrode layer 42 is exposed development treatment, with on the first area 413 being positioned at viewing area
Formation pixel electrode layer 42 is to realize display, and forms pixel electrode layer 42 on the bonding jumper 43 be positioned at join domain to realize
Non-oxidizability is protected.
For preventing bonding jumper 43 because pixel electrode layer 42 links together, the therefore second area 414 in join domain
Pixel electrode layer 42 can not be remained, i.e. when pixel electrode layer 42 is exposed development treatment, need to remove insulating barrier second
The pixel electrode layer 42 of deposition on region 414.
For the second opening 412, if its inclination angle is excessive, then remaining easily occurs in pixel electrode layer 42, as shown in Figure 6,
Fig. 6 be array base palte shown in Fig. 3 manufacture method one embodiment in different inclination angle the second opening on pixel electrode layer go
Comparison schematic diagram except situation.
In Fig. 6, the inclination angle of (A) second opening 412 is relatively big, the therefore thickness of the second opening 412 corner pixel electrode layer 42
C is excessive for degree, and when removing the pixel electrode layer 42 of deposition on insulating barrier second area 414, the corner of the second opening 412 is easy
The residual of pixel electrode layer 42 occurs.And when the inclination angle of the second opening 412 is less, i.e. (B) in Fig. 6, the second opening 412
The thickness D of corner's pixel electrode layer 42 and the thickness approximation of other positions, therefore sink on removal insulating barrier second area 414
During the pixel electrode layer 42 amassed, the corner of the second opening 412 is difficult to residual pixel electrode layer 42 occur.
Therefore, in present embodiment step S303, by light shield, insulating barrier 41 is carried out photocuring process, make first area
413 are further solidified, and second area 414 does not accepts illumination, and slight solidification occurs the most in step s 302.
Then, in the high temperature anneal of step S304, it is difficult to that through the first area 413 of twice solidification backflow occurs
Deformation, and the second area 414 merely through one-step solidification is susceptible to backflow deformation.The inclination angle making the first opening 413 is protected
Hold bigger state, thus ensure the resolution of viewing area the first opening 413, easily form pixel electrode layer 42, be beneficial to aobvious
Show effect；The inclination angle simultaneously making the second opening 414 diminishes, and is removing the pixel electrode at join domain the second opening 414
Time, it is difficult to that residual occurs.
In array base palte obtained by the manufacture method of array base palte of the present invention, insulating barrier is after exposure imaging obtains opening,
Before carrying out high annealing, it is implemented selective photocuring to process so that it is occurred not by high temperature action when high annealing
Deformation with degree.Form the opening of different inclination angle on one array base palte according to different regions, be correspondingly improved battle array
The quality of row substrate.
Refer to the structural representation that Fig. 7, Fig. 7 are array base palte one embodiments of the present invention.Present embodiment array base
Plate 700 includes substrate 71, the insulating barrier 72 being formed on substrate 71, and insulating barrier 72 first area 723 has the first opening 721,
Insulating barrier 72 second area 724 has the second opening 722, is formed with pixel electrode layer 73 on first area 723.
The array base palte class that present embodiment array base palte 700 is prepared with the manufacture method of above-mentioned embodiment array base palte
Seemingly, specifically repeat no more.
The foregoing is only embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization is originally
Equivalent structure or equivalence flow process that description of the invention and accompanying drawing content are made convert, or are directly or indirectly used in what other were correlated with
Technical field, is the most in like manner included in the scope of patent protection of the present invention.
Claims (10)
1. the manufacture method of an insulating barrier, it is characterised in that described manufacture method comprises the following steps:
Substrate deposits an insulating barrier；
Described insulating barrier is exposed development treatment, forms the first opening and the second opening at described insulating barrier, wherein said
First opening is positioned at the first area of described insulating barrier, and described second opening is positioned at the second area of described insulating barrier；
By light shield, the first area of described insulating barrier is carried out photocuring process；
Described insulating barrier is carried out the high temperature anneal.
Manufacture method the most according to claim 1, it is characterised in that described the firstth district by light shield to described insulating barrier
Territory carries out the step of photocuring process and includes:
By light shield, the first area of described insulating barrier is carried out ultraviolet curing process.
Manufacture method the most according to claim 1, it is characterised in that the described step depositing an insulating barrier on substrate it
After include:
The substrate with insulating barrier is placed a period of time in a vacuum.
Manufacture method the most according to claim 1, it is characterised in that the described step depositing an insulating barrier on substrate it
After include:
Described insulating barrier is carried out baking process.
Manufacture method the most according to claim 1, it is characterised in that the inclination angle of described first opening is more than described second
The inclination angle of opening, described first area is positioned at viewing area, and described second area is positioned at join domain.
6. the manufacture method of an array base palte, it is characterised in that described manufacture method includes step: form insulation on substrate
Layer；Described insulating barrier is formed pixel electrode layer；
The described step forming insulating barrier on substrate includes:
Substrate deposits an insulating barrier；
Described insulating barrier is exposed development treatment, forms the first opening and the second opening at described insulating barrier, wherein said
First opening is positioned at the first area of described insulating barrier, and described second opening is positioned at the second area of described insulating barrier；
By light shield, the first area of described insulating barrier is carried out photocuring process；
Described insulating barrier is carried out the high temperature anneal；
The described step forming pixel electrode layer on described insulating barrier includes:
Described pixel electrode layer is formed in the first area of described insulating barrier.
Manufacture method the most according to claim 6, it is characterised in that described the firstth district by light shield to described insulating barrier
Territory carries out the step of photocuring process and includes:
By light shield, the first area of described insulating barrier is carried out ultraviolet curing process.
Manufacture method the most according to claim 6, it is characterised in that described formation pixel electrode layer on described insulating barrier
Step include:
Described insulating barrier deposits a pixel electrode；
Described pixel electrode is exposed development treatment, removes the pixel electrode of deposition on described insulating barrier second area.
Manufacture method the most according to claim 6, it is characterised in that the step after described deposition one insulating barrier includes:
Described insulating barrier is carried out baking process.
10. an array base palte, it is characterised in that described array base palte is prepared by manufacture method any one of claim 6-9.
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| WO2018000484A1 (en) * | 2016-07-01 | 2018-01-04 | 深圳市华星光电技术有限公司 | Insulating layer fabrication method, array fabrication method and array substrate |
| CN109192858A (en) * | 2018-09-19 | 2019-01-11 | 京东方科技集团股份有限公司 | Flexible base board, array substrate, display panel and preparation method and display device |
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| WO2018000484A1 (en) * | 2016-07-01 | 2018-01-04 | 深圳市华星光电技术有限公司 | Insulating layer fabrication method, array fabrication method and array substrate |
| US10147598B2 (en) | 2016-07-01 | 2018-12-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Manufacturing method for insulation layer, manufacturing method for array substrate and array substrate |
| CN109192858A (en) * | 2018-09-19 | 2019-01-11 | 京东方科技集团股份有限公司 | Flexible base board, array substrate, display panel and preparation method and display device |
| CN109192858B (en) * | 2018-09-19 | 2020-04-28 | 京东方科技集团股份有限公司 | Flexible substrate, array substrate, display panel, preparation method and display device |
| US11228007B2 (en) | 2018-09-19 | 2022-01-18 | Boe Technology Group Co., Ltd. | Flexible substrate, display panel, and method of fabricating flexible substrate comprising strengthening layer and flexible material |
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