CN106128972A - A kind of discrete bare chip probe test positional matrix device - Google Patents
A kind of discrete bare chip probe test positional matrix device Download PDFInfo
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- CN106128972A CN106128972A CN201610643554.2A CN201610643554A CN106128972A CN 106128972 A CN106128972 A CN 106128972A CN 201610643554 A CN201610643554 A CN 201610643554A CN 106128972 A CN106128972 A CN 106128972A
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- Prior art keywords
- locating slot
- bare chip
- array
- discrete
- discrete bare
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The present invention discloses a kind of discrete bare chip probe test positional matrix device, including the carrier silicon chip in soi structure, the top layer of carrier silicon chip is provided with locating slot array, locating slot array comprises plural array area, each array area is by one group of locating slot forming array, and the locating slot of each array area is formed with the discrete bare chip of each size respectively and coordinates；All of locating slot all uses dry etch process to prepare；Owing to the oxygen buried layer of carrier silicon chip has dry etch process without response, so the end face of oxygen buried layer is i.e. the bottom surface of locating slot after Shi Ke, it is possible to ensure the flatness of locating slot bottom surface；It addition, dry etch process is faint to locating slot inwall undercutting, also ensure that the perpendicularity of locating slot inwall；Locating slot array is divided into different array regions, the discrete bare chip of the corresponding a kind of size respectively of the locating slot in each array region, it is achieved the batch location of bare chip discrete to sizes the most simultaneously.
Description
Technical field
The present invention relates to microelectronic testing technical field, a kind of discrete bare chip probe test positional matrix fills
Put.
Background technology
Traditional microelectronic product chip testing is carried out on full wafer wafer, and wafer does not carries out scribing process, chip
During test, first pass through vacuum gas and full wafer wafer adsorption is fixed on the slide holder of probe station, then according to predetermined step
Away from carrying out chip positioning test, under this pattern, chip position on probe station is fixed, and positions relatively easy.Along with micro-electro-mechanical systems
The appearance of the Novel multi-core chip architectures such as system, multi-chip module, system in package and three dimensional integrated circuits and fast development, carried out point
The demand that vertical bare chip test is evaluated gets more and more.Especially in micro electro mechanical system field, introduce for eliminating front road processes
Stress influence, the pattern carrying out single-chip test is more and more used, and chip now is no longer to concentrate on crystalline substance
On circle, but scribing process forms the discrete bare chip of single form.
Mostly the vacuum gas guide rail being used for adsorbing wafer on the slide holder of probe station is to present circular distribution, full wafer wafer
Guide rail can be completely covered greatly due to area, complete fixing absorption action, and single discrete bare chip is little due to area, it is impossible to be logical
Cross existing vacuum gas suction type to carry out position and fix, in practical operation, can produce when the slide holder on probe station moves
Slight vibration, owing to the discrete bare chip position being placed on slide holder cannot be fixed, therefore along with the appearance of vibration, chip
There is translation or the rotation of any direction in position, causes the biggest difficulty to probe test.
Owing to discrete bare chip test demand gets more and more, the most also occur in that the frock for discrete bare chip test is ground
Study carefully, but the separate chip being both for single size in current document carries out assignment test, for the discrete core of many sizes
Sheet needs to make different frock clamps.Such as " bare chip test frock clamp " (patent No. ZL201320254404.4), " use
Fixture in radio-frequency testing of semiconductor chip " patent document of (patent No. ZL201020143802.5) i.e. discloses this kind of frock
Multiple various sizes of bare chips all can not be positioned on same device by fixture simultaneously.
Summary of the invention
It is an object of the invention to provide a kind of discrete bare chip probe test positional matrix device, it is possible to realize same
The location of bare chip discrete to sizes simultaneously on carrier, simple in construction, easy to use, the suitability is strong.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of discrete bare chip probe test positional matrix device, including the carrier silicon chip in soi structure, the top layer of soi structure
For semiconductor silicon, intermediate layer be oxygen buried layer, bottom be rear substrate, the top layer of carrier silicon chip is provided with locating slot array, locating slot
Array comprises plural array area, and each array area is by one group of locating slot forming array, the locating slot of each array area
Formed with the discrete bare chip of each size respectively and coordinate；All of locating slot all uses dry etch process to prepare.
Further, a length of L+l/n of described locating slot, the width of locating slot be W+w/n, L be relative with locating slot
The length of the discrete bare chip that should coordinate, l is this discrete bare chip bonding point size at length direction, and W is and locating slot phase
The width of the discrete bare chip of corresponding matching, w is this discrete bare chip bonding point size at width, 2≤n≤10.
Further, in each array area, the spacing of adjacent positioned groove is the integer of corresponding cooperation discrete bare chip size
Times.
The invention has the beneficial effects as follows:
One, use dry etch process to make locating slot array on the carrier silicon chip of soi structure, bury oxygen due to carrier silicon chip
Layer has dry etch process without the feature responded, so the end face of oxygen buried layer is i.e. the bottom surface of locating slot after Shi Ke, it is possible to
Ensure the flatness of locating slot bottom surface；It addition, dry etch process is faint, in also ensure that locating slot to locating slot inwall undercutting
The perpendicularity of wall；
Two, locating slot array is divided into different array regions, the most corresponding a kind of size of the locating slot in each array region
Discrete bare chip, it is achieved the most simultaneously bare chip discrete to sizes batch location；
Three, the size of locating slot is with a size of key dimension parameter of discrete bare chip corresponding thereto, then it is discrete naked to be aided with this
The equidirectional bonding point of chip a size of redundancy size parameter, key dimension parameter and redundancy size parameter have collectively established location
The size of groove, makes same model chip manufacture remain able to be positioned groove in the case of there is scale error the most spacing；
Four, use dry etch process to make locating slot, it is ensured that the integrity of carrier silicon chip bottom, make the carrier silicon chip can be square
Just it is loaded on probe station and completes vac sorb, make discrete bare chip be fixed on probe station.
Accompanying drawing explanation
The present invention is further described with embodiment below in conjunction with the accompanying drawings:
Fig. 1 is the structural representation of the present invention；
Fig. 2 is the A-A amplification view of Fig. 1；
Fig. 3 is the enlarged diagram of the second locating slot in Fig. 1.
Detailed description of the invention
Shown in Fig. 1 Yu Fig. 2, the present invention provides a kind of discrete bare chip probe test positional matrix device, including in
The carrier silicon chip 1 of soi structure, the top layer of carrier silicon chip 1 is semiconductor silicon 1a, and intermediate layer is oxygen buried layer 1b, bottom is back lining
End 1c, the top layer of carrier silicon chip 1 is provided with locating slot array 2, and locating slot array 2 comprises plural array area, the present invention with
As a example by three array area, the i.e. first array area 23, the 21, second array area the 22, the 3rd, array area, the first array area 21 is by one group
One locating slot 21a forming array, the second array area 22 is by one group of second locating slot 22a forming array, and the 3rd array area 23 is by one
Organize the 3rd locating slot 23a forming array；First locating slot 21a, the second locating slot 22a and the 3rd locating slot 23a size each the most not
Identical, formed with various sizes of discrete bare chip respectively and coordinate；All of locating slot all uses dry etch process to prepare.
In each array area, the length of locating slot is L+l/n, and the width of locating slot is W+w/n, L and is and locating slot phase
The length of the discrete bare chip of corresponding matching, l is this discrete bare chip bonding point size at length direction, and W is and locating slot
The width of the discrete bare chip of corresponding cooperation, w is this discrete bare chip bonding point size at width, 2≤n≤10, n
Concrete numerical value specifically can set according to different types of discrete bare chip；Shown in Fig. 3, as a example by the second locating slot 22a,
The a length of L+l/n of the second locating slot 22a, the width of the second locating slot 22a be W+w/n, L be relative with the second locating slot 22a
Length L of the discrete bare chip that should coordinate, l is this discrete bare chip bonding point size l at length direction, and W is fixed with second
The width of the discrete bare chip of the position corresponding cooperation of groove 22a, w is this discrete bare chip bonding point size at width；Its
In its array area, the size of locating slot follows principle of identity.
In each array area, the spacing of adjacent positioned groove is the integral multiple of corresponding cooperation discrete bare chip size, namely often
Locating slot distribution in individual array area is all respectively adopted the principle being equally spaced, equally as a example by the distribution of the second locating slot 22a,
Between two adjacent the second locating slots, spacing in the horizontal is and the corresponding cooperation of the second locating slot 22a discrete naked core length of a film
The integral multiple of degree, between two adjacent the second locating slots, spacing in the vertical is and the second corresponding cooperation of locating slot 22a
The integral multiple of discrete bare chip width.
During use, various sizes of discrete bare chip is put in each array area in the locating slot of corresponding cooperation, so
After carrier silicon chip 1 be loaded on probe station complete vac sorb, make discrete bare chip be fixed on probe, use extremely
Convenient.
The above, be only presently preferred embodiments of the present invention, and the present invention not makees any pro forma restriction；Appoint
What those of ordinary skill in the art, without departing under technical solution of the present invention ambit, may utilize the side of the disclosure above
Technical solution of the present invention is made many possible variations and modification by method and technology contents, or the equivalence being revised as equivalent variations is real
Execute example.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit of the present invention, above example is done
Any simple modification, equivalent, equivalence change and modify, all still fall within technical solution of the present invention protection in the range of.
Claims (3)
1. a discrete bare chip probe test positional matrix device, it is characterised in that include the carrier silicon chip in soi structure,
The top layer of carrier silicon chip is provided with locating slot array, and locating slot array comprises plural array area, and each array area is by one
Group locating slot forming array, the locating slot of each array area is formed with the discrete bare chip of each size respectively and coordinates；All of
Locating slot all uses dry etch process to prepare.
One the most according to claim 1 discrete bare chip probe test positional matrix device, it is characterised in that described fixed
Position groove a length of L+l/n, the width of locating slot be W+w/n, L be the length of the discrete bare chip of cooperation corresponding with locating slot
Degree, l is this discrete bare chip bonding point size at length direction, and W is the discrete bare chip of cooperation corresponding with locating slot
Width, w is this discrete bare chip bonding point size at width, 2≤n≤10.
One the most according to claim 1 and 2 discrete bare chip probe test positional matrix device, it is characterised in that every
In individual array area, the spacing of adjacent positioned groove is the integral multiple of corresponding cooperation discrete bare chip size.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610643554.2A CN106128972A (en) | 2016-08-08 | 2016-08-08 | A kind of discrete bare chip probe test positional matrix device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610643554.2A CN106128972A (en) | 2016-08-08 | 2016-08-08 | A kind of discrete bare chip probe test positional matrix device |
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| CN106128972A true CN106128972A (en) | 2016-11-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108535621A (en) * | 2018-04-11 | 2018-09-14 | 上海华虹宏力半导体制造有限公司 | The crystal round test approach of discrete device chip |
| CN114035022A (en) * | 2021-10-21 | 2022-02-11 | 武汉光谷信息光电子创新中心有限公司 | Test tool and test system of chip |
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| US6392289B1 (en) * | 1999-04-15 | 2002-05-21 | Micron Technology, Inc. | Integrated circuit substrate having through hole markings to indicate defective/non-defective status of same |
| CN102163606A (en) * | 2011-01-26 | 2011-08-24 | 北京大学 | Charge-detecting chip and manufacturing method thereof |
| CN101752253B (en) * | 2008-12-08 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of metal oxide semiconductor (MOS) transistor |
| CN204289396U (en) * | 2014-10-01 | 2015-04-22 | 河北华整实业有限公司 | Full compression joint type igbt chip positioner body |
-
2016
- 2016-08-08 CN CN201610643554.2A patent/CN106128972A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6392289B1 (en) * | 1999-04-15 | 2002-05-21 | Micron Technology, Inc. | Integrated circuit substrate having through hole markings to indicate defective/non-defective status of same |
| CN101752253B (en) * | 2008-12-08 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of metal oxide semiconductor (MOS) transistor |
| CN102163606A (en) * | 2011-01-26 | 2011-08-24 | 北京大学 | Charge-detecting chip and manufacturing method thereof |
| CN204289396U (en) * | 2014-10-01 | 2015-04-22 | 河北华整实业有限公司 | Full compression joint type igbt chip positioner body |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108535621A (en) * | 2018-04-11 | 2018-09-14 | 上海华虹宏力半导体制造有限公司 | The crystal round test approach of discrete device chip |
| CN114035022A (en) * | 2021-10-21 | 2022-02-11 | 武汉光谷信息光电子创新中心有限公司 | Test tool and test system of chip |
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Application publication date: 20161116 |