CN106124970A - The fault filling method of SRAM type FPGA and device - Google Patents
The fault filling method of SRAM type FPGA and device Download PDFInfo
- Publication number
- CN106124970A CN106124970A CN201610446085.5A CN201610446085A CN106124970A CN 106124970 A CN106124970 A CN 106124970A CN 201610446085 A CN201610446085 A CN 201610446085A CN 106124970 A CN106124970 A CN 106124970A
- Authority
- CN
- China
- Prior art keywords
- configuration file
- fpga
- fault location
- direct fault
- fault injection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
本发明涉及一种SRAM型FPGA的故障注入方法和装置,该方法包括获取待测FPGA的初始配置文件;获取初始配置文件中的使用中逻辑资源,并确定使用中逻辑资源对应可配置存储单元的配置文件位置;确定故障注入位置,故障注入位置与可配置存储单元的配置文件位置对应;翻转故障注入位置的配置比特位得到故障注入配置文件;将故障注入配置文件下载到待测FPGA中。该SRAM型FPGA的故障注入方法,无需对FPGA的全部位置进行故障注入,通过仅对使用中的逻辑资源进行故障注入,能够提高SRAM型FPGA的故障注入效率,并且,测试人员根据故障注入的反馈能够快速地评价故障对FPGA功能是否有影响。
The present invention relates to a fault injection method and device for SRAM type FPGA. The method includes obtaining an initial configuration file of FPGA to be tested; obtaining in-use logic resources in the initial configuration file, and determining the location of a configurable storage unit corresponding to the in-use logic resources Configuration file position; determine the fault injection position, the fault injection position corresponds to the configuration file position of the configurable storage unit; flip the configuration bit of the fault injection position to obtain the fault injection configuration file; download the fault injection configuration file into the FPGA to be tested. The fault injection method of the SRAM FPGA does not need to perform fault injection on all positions of the FPGA, and by only performing fault injection on the logic resources in use, the fault injection efficiency of the SRAM FPGA can be improved. Can quickly evaluate whether the fault has an impact on the FPGA function.
Description
技术领域technical field
本发明涉及FPGA空间可靠性技术领域,特别是涉及一种SRAM型FPGA的故障注入方法和装置。The invention relates to the technical field of FPGA space reliability, in particular to a fault injection method and device for an SRAM type FPGA.
背景技术Background technique
SRAM(Static Random Access Memory,即静态随机存取存储器)型FPGA(Field-Programmable Gate Array,即现场可编程门阵列)由于其可重复配置、灵活性高、资源丰富等优点,被广泛应用于航天领域。SRAM型FPGA的内部资源由SRAM型的存储单元实现,而SRAM型的存储单元对空间辐射十分敏感,空间重离子和质子在其中产生的单粒子翻转严重威胁其正常运行,成为行业研究和工程应用的重点和焦点。SRAM (Static Random Access Memory, Static Random Access Memory) FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) is widely used in aerospace due to its repeatable configuration, high flexibility, and abundant resources. field. The internal resources of SRAM-type FPGAs are realized by SRAM-type storage units, and SRAM-type storage units are very sensitive to space radiation, and the single-event inversion generated by space heavy ions and protons seriously threatens its normal operation, and has become an industry research and engineering application. focus and focus.
单粒子翻转(Single Event Upset,SEU):指由于单粒子辐射引起电路的逻辑状态发生变化,即逻辑“1”变成逻辑“0”,或逻辑“0”变成逻辑“1”,造成电路逻辑功能混乱。Single event upset (Single Event Upset, SEU): Refers to the change of the logic state of the circuit due to single event radiation, that is, logic "1" becomes logic "0", or logic "0" becomes logic "1", resulting in circuit The logic function is messed up.
单粒子翻转是单粒子效应(Single Event Effects,SEE)中的一种,故障注入方法是评估FPGA单粒子效应敏感性的常用方法,其原理是使用硬件、软件、仿真等技术向器件或系统中注入故障,评估故障对器件性能或系统运行的影响。目前行业内常用的SRAM型FPGA故障注入方法使用故障随机注入或逐位注入来实现器件抗辐射性能的评价。但单粒子翻转在SRAM型FPGA的产生位置是随机的,若采用随机注入或逐位注入方式对FPGA的全部位置进行故障注入,将花费大量的时间才能确定故障位置,因此,现有的SRAM型FPGA故障注入方法效率低,无法快速地评价故障对FPGA功能是否产生影响。Single event upset is a kind of single event effect (Single Event Effects, SEE). The fault injection method is a common method to evaluate the sensitivity of FPGA single event effect. Its principle is to use hardware, software, simulation and other technologies to inject Inject faults and evaluate their impact on device performance or system operation. At present, the commonly used SRAM FPGA fault injection method in the industry uses fault random injection or bit-by-bit injection to realize the evaluation of device radiation resistance performance. However, the generation position of single event flipping in SRAM type FPGA is random. If random injection or bit-by-bit injection is used to inject faults into all positions of FPGA, it will take a lot of time to determine the fault location. Therefore, the existing SRAM type The FPGA fault injection method is inefficient and cannot quickly evaluate whether the fault has an impact on the FPGA function.
发明内容Contents of the invention
基于此,有必要提供一种能够提高故障注入效率的SRAM型FPGA的故障注入方法和装置。Based on this, it is necessary to provide a fault injection method and device for an SRAM FPGA capable of improving fault injection efficiency.
一种SRAM型FPGA的故障注入方法,包括以下步骤:A kind of fault injection method of SRAM type FPGA, comprises the following steps:
获取待测FPGA的初始配置文件;Obtain the initial configuration file of the FPGA to be tested;
获取所述初始配置文件中的使用中逻辑资源,并确定所述使用中逻辑资源对应可配置存储单元的配置文件位置;Obtaining the in-use logical resource in the initial configuration file, and determining the configuration file location of the configurable storage unit corresponding to the in-use logical resource;
确定故障注入位置,所述故障注入位置与所述可配置存储单元的配置文件位置对应;determining a fault injection location, where the fault injection location corresponds to a configuration file location of the configurable storage unit;
翻转所述故障注入位置的配置比特位得到故障注入配置文件;Flipping the configuration bits of the fault injection position to obtain a fault injection configuration file;
将所述故障注入配置文件下载到所述待测FPGA中。Downloading the fault injection configuration file into the FPGA to be tested.
在一个实施例中,所述翻转所述故障注入位置的配置比特位得到故障注入配置文件的步骤包括:In one embodiment, the step of flipping the configuration bits of the fault injection position to obtain the fault injection configuration file includes:
翻转所述故障注入位置中一种类型的可配置存储单元的配置比特位得到故障注入配置文件。A fault injection configuration file is obtained by flipping configuration bits of a type of configurable storage unit in the fault injection location.
在一个实施例中,所述翻转所述故障注入位置的配置比特位得到故障注入配置文件的步骤包括:In one embodiment, the step of flipping the configuration bits of the fault injection position to obtain the fault injection configuration file includes:
分别翻转所述故障注入位置中多种类型的可配置存储单元的配置比特位得到故障注入配置文件。Fault injection configuration files are obtained by respectively flipping configuration bits of multiple types of configurable storage units in the fault injection location.
在一个实施例中,在将所述故障注入配置文件下载到所述待测FPGA中的步骤之后,还包括:In one embodiment, after the step of downloading the fault injection configuration file into the FPGA to be tested, it also includes:
运行所述FPGA以验证所述FPGA是否失效并得到验证结果;Operate described FPGA to verify whether described FPGA fails and obtain verification result;
当所述故障注入位置对应的配置比特位未全部被翻转时,返回翻转所述故障注入位置的配置比特位得到故障注入配置文件的步骤;When the configuration bits corresponding to the fault injection position are not all flipped, return to the step of flipping the configuration bits of the fault injection position to obtain the fault injection configuration file;
当所述故障注入位置对应的配置比特位全部被翻转时,根据所述验证结果、所述故障注入位置和所述故障注入位置对应的可配置存储单元的类型确定失效模式。When all configuration bits corresponding to the fault injection position are flipped, a failure mode is determined according to the verification result, the fault injection position, and the type of the configurable storage unit corresponding to the fault injection position.
在一个实施例中,所述获取所述初始配置文件中的使用中逻辑资源,并确定所述使用中逻辑资源对应可配置存储单元的配置文件位置的步骤包括:In one embodiment, the step of obtaining the in-use logical resources in the initial configuration file, and determining the configuration file location of the in-use logical resources corresponding to the configurable storage unit includes:
确定所述初始配置文件中的用户逻辑资源;determining user logic resources in the initial configuration file;
区分所述用户逻辑资源中的未使用逻辑资源和使用中逻辑资源;Distinguishing between unused logical resources and in-use logical resources among the user logical resources;
确定所述使用中逻辑资源对应可配置存储单元的配置文件位置。Determine the configuration file location of the configurable storage unit corresponding to the logic resource in use.
一种SRAM型FPGA的故障注入装置,包括:A fault injection device for SRAM type FPGA, comprising:
初始配置获取模块,用于获取待测FPGA的初始配置文件;The initial configuration acquisition module is used to obtain the initial configuration file of the FPGA to be tested;
分析模块,用于获取所述初始配置文件中的使用中逻辑资源,并确定所述使用中逻辑资源对应可配置存储单元的配置文件位置;An analysis module, configured to obtain the in-use logical resources in the initial configuration file, and determine the configuration file location of the configurable storage unit corresponding to the in-use logical resources;
故障位置确定模块,用于确定故障注入位置,所述故障注入位置与所述可配置存储单元的配置文件位置对应;A fault location determining module, configured to determine a fault injection location, where the fault injection location corresponds to the configuration file location of the configurable storage unit;
翻转模块,用于翻转所述故障注入位置的配置比特位得到故障注入配置文件;A flipping module, configured to flip configuration bits of the fault injection position to obtain a fault injection configuration file;
故障注入模块,用于将所述故障注入配置文件下载到所述待测FPGA中。A fault injection module, configured to download the fault injection configuration file into the FPGA to be tested.
在一个实施例中,所述翻转模块,用于翻转所述故障注入位置中一种类型的可配置存储单元的配置比特位得到故障注入配置文件。In one embodiment, the flipping module is configured to flip configuration bits of a type of configurable storage unit in the fault injection location to obtain a fault injection configuration file.
在一个实施例中,所述翻转模块,用于分别翻转所述故障注入位置中多种类型的可配置存储单元的配置比特位得到故障注入配置文件。In one embodiment, the flipping module is configured to respectively flip configuration bits of multiple types of configurable storage units in the fault injection location to obtain a fault injection configuration file.
在一个实施例中,验证模块,用于运行所述FPGA以验证所述FPGA是否失效并得到验证结果;In one embodiment, the verification module is used to run the FPGA to verify whether the FPGA fails and obtain verification results;
失效分析模块,用于当所述故障注入位置对应的配置比特位全部被翻转时,根据所述验证结果、所述故障注入位置和所述故障注入位置对应的可配置存储单元的类型确定失效模式;A failure analysis module, configured to determine a failure mode according to the verification result, the fault injection location, and the type of the configurable storage unit corresponding to the fault injection location when the configuration bits corresponding to the fault injection location are all flipped ;
所述翻转模块,还用于当所述故障注入位置对应的配置比特位未全部被翻转时,翻转下一所述故障注入位置的配置比特位得到故障注入配置文件。The flipping module is further configured to flip the configuration bits of the next fault injection location to obtain a fault injection configuration file when not all configuration bits corresponding to the fault injection location are flipped.
在一个实施例中,所述分析模块,包括:In one embodiment, the analysis module includes:
用户获取资源获取模块,用于确定所述初始配置文件中的用户逻辑资源;A user acquisition resource acquisition module, configured to determine the user logic resources in the initial configuration file;
区分模块,用于区分所述用户逻辑资源中的未使用逻辑资源和使用中逻辑资源;A distinguishing module, configured to distinguish between unused logical resources and in-use logical resources among the user logical resources;
存储单元获取模块,用于确定所述使用中逻辑资源对应可配置存储单元的配置文件位置。The storage unit acquisition module is configured to determine the configuration file location of the configurable storage unit corresponding to the logic resource in use.
该SRAM型FPGA的故障注入方法,通过对FPGA的初始配置文件中进行分析得到使用中逻辑资源,且仅对使用中的逻辑资源进行故障注入。单粒子翻转只有发生在使用中的逻辑资源上时,才可能对FPGA正常运行产生影响。该SRAM型FPGA的故障注入方法,无需对FPGA的全部位置进行故障注入,通过仅对使用中的逻辑资源进行故障注入,能够提高SRAM型FPGA的故障注入效率,并且,测试人员根据故障注入的反馈能够快速地评价故障对FPGA功能是否有影响。In the fault injection method of the SRAM FPGA, logic resources in use are obtained by analyzing an initial configuration file of the FPGA, and fault injection is only performed on the logic resources in use. A single event upset can only affect the normal operation of the FPGA if it occurs on a logic resource in use. The fault injection method of the SRAM type FPGA does not need to perform fault injection on all positions of the FPGA. By only performing fault injection on the logic resources in use, the fault injection efficiency of the SRAM type FPGA can be improved, and the tester can improve the fault injection efficiency according to the fault injection. Can quickly evaluate whether the fault has an impact on the FPGA function.
附图说明Description of drawings
图1为一个实施例的SRAM型FPGA的故障注入方法的流程图;Fig. 1 is the flowchart of the fault injection method of the SRAM type FPGA of an embodiment;
图2为一种实施方式的一故障注入位置对应的可配置存储单元的配置比特位;FIG. 2 is a configuration bit of a configurable storage unit corresponding to a fault injection position in an embodiment;
图3为将如图2所示的配置比特位翻转得到的故障注入配置文件;Fig. 3 is the fault injection configuration file obtained by inverting the configuration bits shown in Fig. 2;
图4为另一种实施例的SRAM型FPGA的故障注入方法的流程图;Fig. 4 is the flowchart of the fault injection method of the SRAM type FPGA of another kind of embodiment;
图5为一个实施例的SRAM型FPGA的故障注入装置的功能模块示意图;Fig. 5 is the functional module schematic diagram of the fault injection device of the SRAM type FPGA of an embodiment;
图6为另一个实施例的SRAM型FPGA的故障注入装置的功能模块示意图。FIG. 6 is a schematic diagram of functional modules of a fault injection device for an SRAM FPGA according to another embodiment.
具体实施方式detailed description
为了使本发明的目的、技术方案以及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不限定本发明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
在一个实施例中,如图1所示,提供了一种SRAM型FPGA的故障注入方法,本实施例以该方法应用于计算机为例进行说明,该计算机上运行有一种应用程序,通过该程序来该实现SRAM型FPGA的故障注入方法。该方法包括以下步骤:In one embodiment, as shown in Figure 1, a kind of fault injection method of SRAM type FPGA is provided, and the present embodiment is explained with this method being applied to computer as example, and there is a kind of application program running on this computer, by this program To realize the fault injection method of SRAM type FPGA. The method includes the following steps:
S102:获取待测FPGA的初始配置文件。S102: Obtain an initial configuration file of the FPGA to be tested.
FPGA,即现场可编程门阵列,用户可根据现场的实际情况,在与FPGA连接的输入装置上输入用户设计电路的需求,FPGA自动根据用户需求设计电路,并生成改设计电路对应的初始配置文件。FPGA, that is, Field Programmable Gate Array, the user can input the user's design circuit requirements on the input device connected to the FPGA according to the actual situation on site, FPGA automatically designs the circuit according to the user's requirements, and generates the initial configuration file corresponding to the modified circuit .
S104:获取初始配置文件中的使用中逻辑资源,并确定使用中逻辑资源对应可配置存储单元的配置文件位置。S104: Obtain the in-use logical resource in the initial configuration file, and determine the configuration file location of the configurable storage unit corresponding to the in-use logical resource.
FPGA中所含的资源非常丰富,包括基本的逻辑单元,DSP资源和块RAM等。使用中逻辑资源是指根据用户需求设计的电路中所使用到的FPGA中的逻辑资源。可配置存储单元包括BRAM(Block Random Access Memory块随机存取存储器)、LUT(Look-Up-Table,查找表)和触发器等中的至少一种。在具体的实施方式中,用户通过参考用户手册,对初配置文件内容格式进行分析,分析出初始配置文件中的使用中逻辑资源,以及使用中逻辑资源对应可配置存储单元的配置文件位置并输入到运行有应用程序的计算机中,从而计算机获取到初始配置文件中的使用中逻辑资源,并确定使用中逻辑资源对应可配置存储单元的配置文件位置。The resources contained in the FPGA are very rich, including basic logic units, DSP resources and block RAM. The logic resources in use refer to the logic resources in the FPGA used in the circuit designed according to user requirements. The configurable storage unit includes at least one of BRAM (Block Random Access Memory), LUT (Look-Up-Table, lookup table) and flip-flops. In a specific implementation, the user analyzes the content format of the initial configuration file by referring to the user manual, analyzes the logical resource in use in the initial configuration file, and the configuration file location of the logical resource in use corresponding to the configurable storage unit and enters the to the computer running the application program, so that the computer obtains the in-use logical resource in the initial configuration file, and determines the configuration file location of the configurable storage unit corresponding to the in-use logical resource.
S106:确定故障注入位置,故障注入位置与可配置存储单元的配置文件位置对应。S106: Determine the fault injection location, where the fault injection location corresponds to the configuration file location of the configurable storage unit.
本实施方式中,将可配置存储单元的配置文件位置作为故障注入位置。在具体的实施方式中,可将一种类型的可配置存储单元作为故障注入对象,用于模拟单位翻转故障。或者将多种类型的可配置存储单元作为故障注入对象,用于模拟多位翻转故障。In this embodiment, the configuration file location of the configurable storage unit is used as the fault injection location. In a specific embodiment, one type of configurable storage unit may be used as a fault injection object for simulating a unit flip fault. Or multiple types of configurable memory cells can be used as fault injection objects to simulate multi-bit flip faults.
S108:翻转故障注入位置的配置比特位得到故障注入配置文件。S108: Flipping the configuration bit of the fault injection position to obtain the fault injection configuration file.
具体的,根据与故障注入位置对应的可配置存储单元,查找获取可配置存储单元的配置比特位,得到故障注入位置对应的配置比特位。一种实施方式中,某一故障注入位置对应的可配置存储单元的配置比特位如图2所示。将如图2所示的配置比特位翻转得到的故障配置文件如图3所示。Specifically, according to the configurable storage unit corresponding to the fault injection position, the configuration bit of the configurable storage unit is searched for and obtained, and the configuration bit corresponding to the fault injection position is obtained. In an implementation manner, configuration bits of a configurable storage unit corresponding to a fault injection location are shown in FIG. 2 . The fault configuration file obtained by inverting the configuration bits shown in FIG. 2 is shown in FIG. 3 .
S110:将故障注入配置文件下载到待测FPGA中。S110: Download the fault injection configuration file into the FPGA to be tested.
具体的,将故障配置文件通过JTAG(Joint Test Action Group;联合测试工作组)下载到SARM型FPGA中。Specifically, the fault configuration file is downloaded to the SARM FPGA through JTAG (Joint Test Action Group; joint test working group).
该实施方式的SRAM型FPGA的故障注入方法,通过对FPGA的初始配置文件中进行分析得到使用中逻辑资源,且仅对使用中的逻辑资源进行故障注入。单粒子翻转只有发生在使用中的逻辑资源上时,才可能对FPGA正常运行产生影响。该SRAM型FPGA的故障注入方法,无需对FPGA的全部位置进行故障注入,通过仅对使用中的逻辑资源进行故障注入,能够提高SRAM型FPGA的故障注入效率,并且,测试人员根据故障注入的反馈能够快速地评价故障对FPGA功能是否有影响。In the fault injection method of the SRAM FPGA in this embodiment, logic resources in use are obtained by analyzing the initial configuration file of the FPGA, and fault injection is only performed on the logic resources in use. A single event upset can only affect the normal operation of the FPGA if it occurs on a logic resource in use. The fault injection method of the SRAM type FPGA does not need to perform fault injection on all positions of the FPGA. By only performing fault injection on the logic resources in use, the fault injection efficiency of the SRAM type FPGA can be improved, and the tester can improve the fault injection efficiency according to the fault injection. Can quickly evaluate whether the fault has an impact on the FPGA function.
在其中一个实施例中,步骤S108包括:翻转故障注入位置中一种类型的可配置存储单元的配置比特位得到故障注入配置文件。In one embodiment, step S108 includes: flipping configuration bits of one type of configurable storage unit in the fault injection location to obtain a fault injection configuration file.
可配置存储单元包括多种类型,例如,BRAM(Block Random Access Memory块随机存取存储器)、LUT(Look-Up-Table,查找表)和触发器等。通过翻转一种类型的可配置存储单元的配置比特位,能够模拟SARM型FPGA的单位翻转故障。The configurable storage unit includes various types, for example, BRAM (Block Random Access Memory), LUT (Look-Up-Table, lookup table), and flip-flops. By flipping the configuration bits of one type of configurable memory cell, it is possible to simulate the cell flip failure of a SARM-type FPGA.
在其中一个实施例中,步骤S108包括:分别翻转故障注入位置中多种类型的可配置存储单元的配置比特位得到故障注入配置文件。In one embodiment, step S108 includes: respectively flipping configuration bits of multiple types of configurable storage units in the fault injection location to obtain a fault injection configuration file.
通过翻转多种类型的可配置存储单元的配置比特位,能够模拟SARM型FPGA的多位翻转故障。By flipping the configuration bits of various types of configurable memory cells, it is possible to simulate the multi-bit flip fault of the SARM-type FPGA.
在其中一个实施例中,如图4所示,在步骤S110之后,还包括:In one of the embodiments, as shown in FIG. 4, after step S110, further includes:
S112:运行FPGA以验证FPGA是否失效并得到验证结果。S112: Run the FPGA to verify whether the FPGA is invalid and obtain a verification result.
通过运行注入了故障注入配置文件的FPGA以验证配置的注入的故障是否引起FPGA失效。具体的,验证结果包括失效和未失效以及具体的失效模式。不同的故障注入位置以及不同故障注入位置对应的可配置存储单元的类型得到的失效模式可能相同。Verify that the configured injected faults cause the FPGA to fail by running the FPGA injected with the fault injection configuration file. Specifically, the verification results include failure and non-failure and specific failure modes. The failure modes obtained by different fault injection locations and the types of configurable storage units corresponding to different fault injection locations may be the same.
S114:判断故障注入位置对应的配置比特位是否全部被翻转。若是,则执行步骤S116;若否,则返回步骤S108。S114: Determine whether all the configuration bits corresponding to the fault injection position are flipped. If yes, execute step S116; if no, return to step S108.
在本实施方式中,确定的故障注入位置有多个。每次翻转一个或一组故障注入位置对应的可配置存储单元的配置比特位。在每次运行注入了故障配置文件的待测FPGA后,判断与故障注入位置对应的配置比特位是否全部被翻转。当判断为否时,返回步骤S108以逐一翻转故障注入位置的配置比特位并得到对应的故障注入配置文件。In this embodiment, there are multiple determined fault injection locations. The configuration bits of the configurable storage units corresponding to one or a group of fault injection positions are flipped each time. After running the FPGA under test injected with the fault configuration file each time, it is judged whether all the configuration bits corresponding to the fault injection position are flipped. When the judgment is no, return to step S108 to flip the configuration bits of the fault injection positions one by one and obtain the corresponding fault injection configuration file.
S116:根据验证结果、故障注入位置和故障注入位置对应的可配置存储单元的类型确定失效模式。S116: Determine the failure mode according to the verification result, the fault injection location, and the type of the configurable storage unit corresponding to the fault injection location.
具体的,单位翻转注入和多位翻转注入确定失效模式的方法不同。以单位翻转注入为例,假设用户使用的内部逻辑资源的容量为l,共有m个可配置存储单元类型,产生n种失效模式,根据单位翻转注入位置、故障注入位置对应的可配置存储单元的类型以及故障注入引导起的失效模式进行总结,得到的结果如表1所示。Specifically, the methods for determining the failure mode of the single-bit flip injection and the multi-bit flip injection are different. Taking unit flipping injection as an example, assuming that the capacity of the internal logic resource used by the user is l, there are m configurable storage unit types, resulting in n types of failure modes, according to the location of the unit flipping injection and the location of the configurable storage unit corresponding to the fault injection location The types and failure modes induced by fault injection are summarized, and the results are shown in Table 1.
表1 单位翻转故障定位注入结果Table 1 Injection results of unit flipping fault location
根据表1,可以计算得到各种失效模式(Failure Mode i,FMi,1≤i≤n)对应的内部逻辑资源数量,NFMi。进一步计算得到FMi在用户逻辑资源中的比例因子,即失效因子αFMi:According to Table 1, the number of internal logic resources corresponding to various failure modes (Failure Mode i, FMi, 1≤i≤n), N FMi , can be calculated. Further calculation obtains the proportional factor of FMi in user logic resources, that is, the failure factor α FMi :
αFMi=NFMi/Ntotal α FMi =N FMi /N total
其中,Ntotal为内部逻辑资源的总容量。Wherein, N total is the total capacity of internal logical resources.
以多位翻转为例,依据用户需求,确定多位翻转故障注入组合,假设其数量为x,对应的可配置存储单元类型组合为y,产生z种失效模式。依据多位翻转注入位置、翻转位置所在可配置存储单元的类型(BRAM、LUT、触发器等及其组合)、故障注入引导起的失效模式进行总结,如表2所示。Taking multi-bit flipping as an example, determine the multi-bit flipping fault injection combination according to user requirements, assuming that the number is x, and the corresponding combination of configurable storage unit types is y, resulting in z failure modes. According to the multi-bit flip injection position, the type of configurable storage unit where the flip position is located (BRAM, LUT, flip-flop, etc. and their combination), the failure mode induced by fault injection is summarized, as shown in Table 2.
表2 多位翻转故障定位注入结果Table 2 Injection results of multi-bit flipping fault location
上述的SRAM型FPGA的故障注入方法,能够全面评价SRAM型FPGA的抗单粒子翻转性能,全面揭示失效模式,发现抗单粒子翻转薄弱环节。也可使用该方法获得的定位失效地点以便对器件进行针对性加固。The above-mentioned fault injection method for SRAM-type FPGA can fully evaluate the anti-single event upset performance of SRAM-type FPGA, fully reveal the failure mode, and find the weak link of anti-single event upset. The location of failure obtained by this method can also be used for targeted reinforcement of the device.
在另一种实施方式中,步骤S104包括:确定初始配置文件中的用户逻辑资源;区分用户逻辑资源中的未使用逻辑资源和使用中逻辑资源;确定使用中逻辑资源对应可配置存储单元的配置文件位置。In another implementation, step S104 includes: determining the user logical resources in the initial configuration file; distinguishing between unused logical resources and in-use logical resources in the user logical resources; determining the configuration of the configurable storage unit corresponding to the in-use logical resources file location.
该方法通过区分用户使用的逻辑资源和未使用的内部逻辑资源,精准定位用户使用的逻辑资源,并用用户逻辑资源中未使用逻辑资源和使用中逻辑资源进行区分,从而精准地定位使用中逻辑资源中可配置存储单元以及可配置存储单元的位置,然后针对性地在可配置存储单元中进行故障注入,能够提高SRAM型FPGA的故障注入效率。This method accurately locates the logical resources used by the user by distinguishing the logical resources used by the user from the unused internal logical resources, and distinguishes the unused logical resources and the logical resources in use among the user logical resources, so as to accurately locate the logical resources in use The configurable storage unit and the location of the configurable storage unit, and then perform fault injection in the configurable storage unit in a targeted manner, which can improve the fault injection efficiency of the SRAM FPGA.
本发明还提供一种SRAM型FPGA的故障注入装置,如图5所示包括:The present invention also provides a kind of fault injection device of SRAM type FPGA, comprises as shown in Figure 5:
初始配置获取模块102,用于获取待测FPGA的初始配置文件。The initial configuration acquiring module 102 is configured to acquire an initial configuration file of the FPGA to be tested.
分析模块104,用于获取初始配置文件中的使用中逻辑资源,并确定使用中逻辑资源对应可配置存储单元的配置文件位置。The analysis module 104 is configured to obtain the in-use logical resources in the initial configuration file, and determine the configuration file location of the configurable storage unit corresponding to the in-use logical resources.
故障位置确定模块106,用于确定故障注入位置,故障注入位置与可配置存储单元的配置文件位置对应。The fault location determination module 106 is configured to determine a fault injection location, and the fault injection location corresponds to the configuration file location of the configurable storage unit.
翻转模块108用于翻转故障注入位置的配置比特位得到故障注入配置文件。The flipping module 108 is used for flipping the configuration bits of the fault injection position to obtain the fault injection configuration file.
故障注入模块110,用于将故障注入配置文件下载到待测FPGA中。The fault injection module 110 is configured to download the fault injection configuration file into the FPGA to be tested.
该实施方式的SRAM型FPGA的故障注入装置,通过对FPGA的初始配置文件中进行分析得到使用中逻辑资源,且仅对使用中的逻辑资源进行故障注入。单粒子翻转只有发生在使用中的逻辑资源上时,才可能对FPGA正常运行产生影响。该SRAM型FPGA的故障注入装置,无需对FPGA的全部位置进行故障注入,通过仅对使用中的逻辑资源进行故障注入,能够提高SRAM型FPGA的故障注入效率,并且,测试人员根据故障注入的反馈能够快速地评价故障对FPGA功能是否有影响。The fault injection device for SRAM FPGA in this embodiment obtains logic resources in use by analyzing the initial configuration file of the FPGA, and only performs fault injection on the logic resources in use. A single event upset can only affect the normal operation of the FPGA if it occurs on a logic resource in use. The fault injection device of the SRAM type FPGA does not need to perform fault injection on all positions of the FPGA. By performing fault injection only on the logic resources in use, the fault injection efficiency of the SRAM type FPGA can be improved, and the tester can improve the fault injection efficiency according to the fault injection feedback. Can quickly evaluate whether the fault has an impact on the FPGA function.
在另一个实施例中,翻转模块108,用于翻转故障注入位置中一种类型的可配置存储单元的配置比特位得到故障注入配置文件。In another embodiment, the flipping module 108 is configured to flip configuration bits of a type of configurable storage unit in the fault injection location to obtain a fault injection configuration file.
在另一个实施例中,翻转模块,用于分别翻转故障注入位置中多种类型的可配置存储单元的配置比特位得到故障注入配置文件。In another embodiment, the flipping module is configured to respectively flip configuration bits of multiple types of configurable storage units in the fault injection location to obtain a fault injection configuration file.
在另一个实施例中,如图6所示,还包括验证模块112、判断模块114和失效分析模块116,In another embodiment, as shown in FIG. 6, a verification module 112, a judgment module 114 and a failure analysis module 116 are also included,
验证模块112,用于运行FPGA以验证FPGA是否失效并得到验证结果。The verification module 112 is configured to run the FPGA to verify whether the FPGA is invalid and obtain a verification result.
判断模块114,用于判断与故障注入位置对应的配置比特位是否全部被翻转。A judging module 114, configured to judge whether all the configuration bits corresponding to the fault injection position are reversed.
失效分析模块116,用于当故障注入位置对应的配置比特位全部被翻转时,根据验证结果、故障注入位置和故障注入位置对应的可配置存储单元的类型确定失效模式。The failure analysis module 116 is configured to determine the failure mode according to the verification result, the fault injection location, and the type of the configurable storage unit corresponding to the fault injection location when all the configuration bits corresponding to the fault injection location are flipped.
翻转模块108,还用于当故障注入位置对应的配置比特位未全部被翻转时,翻转下一故障注入位置的配置比特位得到故障配置文件。The flip module 108 is further configured to flip configuration bits at the next fault injection location to obtain a fault configuration file when not all configuration bits corresponding to the fault injection location have been flipped.
在另一个实施例中,分析模块,包括:用户获取资源获取模块1041、区分模块1042和存储单元获取模块1043。In another embodiment, the analysis module includes: a user acquisition resource acquisition module 1041 , a differentiation module 1042 and a storage unit acquisition module 1043 .
用户获取资源获取模块1041,用于确定初始配置文件中的用户逻辑资源;User acquisition resource acquisition module 1041, configured to determine user logic resources in the initial configuration file;
区分模块1042,用于区分用户逻辑资源中的未使用逻辑资源和使用中逻辑资源。A distinguishing module 1042, configured to distinguish unused logical resources and in-use logical resources among the user logical resources.
存储单元获取模块1043,用于确定使用中逻辑资源对应可配置存储单元的配置文件位置。The storage unit acquisition module 1043 is configured to determine the configuration file location of the configurable storage unit corresponding to the logic resource in use.
该装置通过区分用户使用的逻辑资源和未使用的内部逻辑资源,精准定位用户使用的逻辑资源,并用用户逻辑资源中未使用逻辑资源和使用中逻辑资源进行区分,从而精准地定位使用中逻辑资源中可配置存储单元以及可配置存储单元的位置,然后针对性地在可配置存储单元中进行故障注入,能够提高SRAM型FPGA的故障注入效率。The device accurately locates the logical resources used by the user by distinguishing the logical resources used by the user from the unused internal logical resources, and distinguishes the unused logical resources and the logical resources in use among the user logical resources, thereby accurately locating the logical resources in use The configurable storage unit and the location of the configurable storage unit, and then targeted fault injection in the configurable storage unit, can improve the fault injection efficiency of the SRAM FPGA.
以上实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610446085.5A CN106124970B (en) | 2016-06-17 | 2016-06-17 | The fault filling method and device of SRAM type FPGA |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610446085.5A CN106124970B (en) | 2016-06-17 | 2016-06-17 | The fault filling method and device of SRAM type FPGA |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106124970A true CN106124970A (en) | 2016-11-16 |
CN106124970B CN106124970B (en) | 2018-11-30 |
Family
ID=57470068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610446085.5A Active CN106124970B (en) | 2016-06-17 | 2016-06-17 | The fault filling method and device of SRAM type FPGA |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106124970B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106776177A (en) * | 2016-12-16 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of fault filling method of xfs, system and Fault Management System |
CN107092539A (en) * | 2017-02-24 | 2017-08-25 | 北京时代民芯科技有限公司 | A kind of FPGA direct fault location composite models based on configuration bit stream |
CN112596506A (en) * | 2020-12-30 | 2021-04-02 | 中国科学院空天信息创新研究院 | Fault injection method, fault injector, storage medium and fault injection system |
CN113253097A (en) * | 2021-05-31 | 2021-08-13 | 中国人民解放军国防科技大学 | SRAM type FPGA fault injection acceleration test method based on whole frame turnover |
US11378622B1 (en) | 2021-01-05 | 2022-07-05 | Raytheon Company | Methods and systems for single-event upset fault injection testing |
CN115080318A (en) * | 2022-06-14 | 2022-09-20 | 北京时代民芯科技有限公司 | FPGA fault injection and fault positioning method, device, equipment and storage medium |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050050393A1 (en) * | 2003-08-26 | 2005-03-03 | Chakraborty Tapan J. | Fault injection method and system |
CN1658381A (en) * | 2004-02-21 | 2005-08-24 | 华为技术有限公司 | Method and device for logic fault injection |
CN103198868A (en) * | 2013-04-16 | 2013-07-10 | 西北核技术研究所 | Fault simulation system and fault analysis method for single event upset |
CN103293468A (en) * | 2013-04-09 | 2013-09-11 | 北京时代民芯科技有限公司 | Fault injection system and fault injection method facilitating device fault sensitivity test |
CN103901342A (en) * | 2014-03-18 | 2014-07-02 | 北京时代民芯科技有限公司 | Accurate FPGA fault injection system and method based on mask file |
CN103984625A (en) * | 2014-05-12 | 2014-08-13 | 浪潮电子信息产业股份有限公司 | System robustness testing method based on use rate analysis |
US9208043B1 (en) * | 2013-03-15 | 2015-12-08 | Xilinx, Inc. | Method and apparatus for fault injection and verification on an integrated circuit |
CN105223494A (en) * | 2015-09-25 | 2016-01-06 | 中国人民解放军国防科学技术大学 | A kind of system single particle effect detection method based on parallel testing and system |
-
2016
- 2016-06-17 CN CN201610446085.5A patent/CN106124970B/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050050393A1 (en) * | 2003-08-26 | 2005-03-03 | Chakraborty Tapan J. | Fault injection method and system |
CN1658381A (en) * | 2004-02-21 | 2005-08-24 | 华为技术有限公司 | Method and device for logic fault injection |
US9208043B1 (en) * | 2013-03-15 | 2015-12-08 | Xilinx, Inc. | Method and apparatus for fault injection and verification on an integrated circuit |
CN103293468A (en) * | 2013-04-09 | 2013-09-11 | 北京时代民芯科技有限公司 | Fault injection system and fault injection method facilitating device fault sensitivity test |
CN103198868A (en) * | 2013-04-16 | 2013-07-10 | 西北核技术研究所 | Fault simulation system and fault analysis method for single event upset |
CN103901342A (en) * | 2014-03-18 | 2014-07-02 | 北京时代民芯科技有限公司 | Accurate FPGA fault injection system and method based on mask file |
CN103984625A (en) * | 2014-05-12 | 2014-08-13 | 浪潮电子信息产业股份有限公司 | System robustness testing method based on use rate analysis |
CN105223494A (en) * | 2015-09-25 | 2016-01-06 | 中国人民解放军国防科学技术大学 | A kind of system single particle effect detection method based on parallel testing and system |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106776177A (en) * | 2016-12-16 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of fault filling method of xfs, system and Fault Management System |
CN107092539A (en) * | 2017-02-24 | 2017-08-25 | 北京时代民芯科技有限公司 | A kind of FPGA direct fault location composite models based on configuration bit stream |
WO2018153131A1 (en) * | 2017-02-24 | 2018-08-30 | 北京时代民芯科技有限公司 | Configuration bitstream-based fpga fault injection composite model and fault injection system |
CN107092539B (en) * | 2017-02-24 | 2020-05-19 | 北京时代民芯科技有限公司 | A Composite Model of FPGA Fault Injection Based on Configuration Code Stream |
CN112596506A (en) * | 2020-12-30 | 2021-04-02 | 中国科学院空天信息创新研究院 | Fault injection method, fault injector, storage medium and fault injection system |
US11378622B1 (en) | 2021-01-05 | 2022-07-05 | Raytheon Company | Methods and systems for single-event upset fault injection testing |
CN113253097A (en) * | 2021-05-31 | 2021-08-13 | 中国人民解放军国防科技大学 | SRAM type FPGA fault injection acceleration test method based on whole frame turnover |
CN113253097B (en) * | 2021-05-31 | 2021-09-21 | 中国人民解放军国防科技大学 | SRAM type FPGA fault injection acceleration test method based on whole frame turnover |
CN115080318A (en) * | 2022-06-14 | 2022-09-20 | 北京时代民芯科技有限公司 | FPGA fault injection and fault positioning method, device, equipment and storage medium |
CN115080318B (en) * | 2022-06-14 | 2025-06-24 | 北京时代民芯科技有限公司 | FPGA fault injection and fault location method, device, equipment, and storage medium |
Also Published As
Publication number | Publication date |
---|---|
CN106124970B (en) | 2018-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106124970B (en) | The fault filling method and device of SRAM type FPGA | |
Cruz et al. | Hardware Trojan detection using ATPG and model checking | |
Farahmandi et al. | Trojan localization using symbolic algebra | |
Zhang et al. | Case study: Detecting hardware Trojans in third-party digital IP cores | |
CN102662144B (en) | A hardware Trojan horse detection method based on activity measurement | |
CN104215895A (en) | Hardware Trojan horse detection method and hardware Trojan horse detection system based on test vectors | |
CN104239616A (en) | Design method of integrated circuit and hardware trojan detection method | |
CN104101828B (en) | Anti- hardware Trojan horse circuit design method based on activation probability analysis | |
CN105548866A (en) | SRAM type FPGA test method based on irradiation test environment simulation | |
Villalta et al. | SEU emulation in industrial SoCs combining microprocessor and FPGA | |
CN104063307B (en) | A kind of method for testing software and system | |
CN103293468A (en) | Fault injection system and fault injection method facilitating device fault sensitivity test | |
US7656189B1 (en) | Trust controller for detecting unauthorized logic in a circuit design | |
CN109101819A (en) | A kind of leak detection method and terminal, storage medium | |
Janning et al. | A cost-effective FPGA-based fault simulation environment | |
WO2011139925A1 (en) | Automated verification and estimation of quiescent power supply current | |
Marchese et al. | Formal fault propagation analysis that scales to modern automotive SoCs | |
Jacob et al. | Detection of malicious circuitry using transition probability based node reduction technique | |
Cornell et al. | Combinational hardware Trojan detection using logic implications | |
CN104849648B (en) | A kind of test vector generating method for improving wooden horse activity | |
Violante et al. | Analyzing SEU effects is SRAM-based FPGAsb | |
Nunes et al. | Evaluating xilinx SEU controller macro for fault injection | |
Guzmán-Miranda et al. | FT-UNSHADES2: A platform for early evaluation of ASIC and FPGA dependability using partial reconfiguration | |
Mogollón et al. | Metrics for the measurement of the quality of stimuli in radiation testing using fast hardware emulation | |
US10268786B2 (en) | System and method for capturing transaction specific stage-wise log data |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |