CN106124970A - The fault filling method of SRAM type FPGA and device - Google Patents

Abstract

The present invention relates to a fault injection method and device for SRAM type FPGA. The method includes obtaining an initial configuration file of FPGA to be tested; obtaining in-use logic resources in the initial configuration file, and determining the location of a configurable storage unit corresponding to the in-use logic resources Configuration file position; determine the fault injection position, the fault injection position corresponds to the configuration file position of the configurable storage unit; flip the configuration bit of the fault injection position to obtain the fault injection configuration file; download the fault injection configuration file into the FPGA to be tested. The fault injection method of the SRAM FPGA does not need to perform fault injection on all positions of the FPGA, and by only performing fault injection on the logic resources in use, the fault injection efficiency of the SRAM FPGA can be improved. Can quickly evaluate whether the fault has an impact on the FPGA function.

Description

Fault injection method and device for SRAM type FPGA

technical field

The invention relates to the technical field of FPGA space reliability, in particular to a fault injection method and device for an SRAM type FPGA.

Background technique

SRAM (Static Random Access Memory, Static Random Access Memory) FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) is widely used in aerospace due to its repeatable configuration, high flexibility, and abundant resources. field. The internal resources of SRAM-type FPGAs are realized by SRAM-type storage units, and SRAM-type storage units are very sensitive to space radiation, and the single-event inversion generated by space heavy ions and protons seriously threatens its normal operation, and has become an industry research and engineering application. focus and focus.

Single event upset (Single Event Upset, SEU): Refers to the change of the logic state of the circuit due to single event radiation, that is, logic "1" becomes logic "0", or logic "0" becomes logic "1", resulting in circuit The logic function is messed up.

Single event upset is a kind of single event effect (Single Event Effects, SEE). The fault injection method is a common method to evaluate the sensitivity of FPGA single event effect. Its principle is to use hardware, software, simulation and other technologies to inject Inject faults and evaluate their impact on device performance or system operation. At present, the commonly used SRAM FPGA fault injection method in the industry uses fault random injection or bit-by-bit injection to realize the evaluation of device radiation resistance performance. However, the generation position of single event flipping in SRAM type FPGA is random. If random injection or bit-by-bit injection is used to inject faults into all positions of FPGA, it will take a lot of time to determine the fault location. Therefore, the existing SRAM type The FPGA fault injection method is inefficient and cannot quickly evaluate whether the fault has an impact on the FPGA function.

Contents of the invention

Based on this, it is necessary to provide a fault injection method and device for an SRAM FPGA capable of improving fault injection efficiency.

A kind of fault injection method of SRAM type FPGA, comprises the following steps:

Obtain the initial configuration file of the FPGA to be tested;

Obtaining the in-use logical resource in the initial configuration file, and determining the configuration file location of the configurable storage unit corresponding to the in-use logical resource;

determining a fault injection location, where the fault injection location corresponds to a configuration file location of the configurable storage unit;

Flipping the configuration bits of the fault injection position to obtain a fault injection configuration file;

Downloading the fault injection configuration file into the FPGA to be tested.

In one embodiment, the step of flipping the configuration bits of the fault injection position to obtain the fault injection configuration file includes:

A fault injection configuration file is obtained by flipping configuration bits of a type of configurable storage unit in the fault injection location.

In one embodiment, the step of flipping the configuration bits of the fault injection position to obtain the fault injection configuration file includes:

Fault injection configuration files are obtained by respectively flipping configuration bits of multiple types of configurable storage units in the fault injection location.

In one embodiment, after the step of downloading the fault injection configuration file into the FPGA to be tested, it also includes:

Operate described FPGA to verify whether described FPGA fails and obtain verification result;

When the configuration bits corresponding to the fault injection position are not all flipped, return to the step of flipping the configuration bits of the fault injection position to obtain the fault injection configuration file;

When all configuration bits corresponding to the fault injection position are flipped, a failure mode is determined according to the verification result, the fault injection position, and the type of the configurable storage unit corresponding to the fault injection position.

In one embodiment, the step of obtaining the in-use logical resources in the initial configuration file, and determining the configuration file location of the in-use logical resources corresponding to the configurable storage unit includes:

determining user logic resources in the initial configuration file;

Distinguishing between unused logical resources and in-use logical resources among the user logical resources;

Determine the configuration file location of the configurable storage unit corresponding to the logic resource in use.

A fault injection device for SRAM type FPGA, comprising:

The initial configuration acquisition module is used to obtain the initial configuration file of the FPGA to be tested;

An analysis module, configured to obtain the in-use logical resources in the initial configuration file, and determine the configuration file location of the configurable storage unit corresponding to the in-use logical resources;

A fault location determining module, configured to determine a fault injection location, where the fault injection location corresponds to the configuration file location of the configurable storage unit;

A flipping module, configured to flip configuration bits of the fault injection position to obtain a fault injection configuration file;

A fault injection module, configured to download the fault injection configuration file into the FPGA to be tested.

In one embodiment, the flipping module is configured to flip configuration bits of a type of configurable storage unit in the fault injection location to obtain a fault injection configuration file.

In one embodiment, the flipping module is configured to respectively flip configuration bits of multiple types of configurable storage units in the fault injection location to obtain a fault injection configuration file.

In one embodiment, the verification module is used to run the FPGA to verify whether the FPGA fails and obtain verification results;

A failure analysis module, configured to determine a failure mode according to the verification result, the fault injection location, and the type of the configurable storage unit corresponding to the fault injection location when the configuration bits corresponding to the fault injection location are all flipped ;

The flipping module is further configured to flip the configuration bits of the next fault injection location to obtain a fault injection configuration file when not all configuration bits corresponding to the fault injection location are flipped.

In one embodiment, the analysis module includes:

A user acquisition resource acquisition module, configured to determine the user logic resources in the initial configuration file;

A distinguishing module, configured to distinguish between unused logical resources and in-use logical resources among the user logical resources;

The storage unit acquisition module is configured to determine the configuration file location of the configurable storage unit corresponding to the logic resource in use.

In the fault injection method of the SRAM FPGA, logic resources in use are obtained by analyzing an initial configuration file of the FPGA, and fault injection is only performed on the logic resources in use. A single event upset can only affect the normal operation of the FPGA if it occurs on a logic resource in use. The fault injection method of the SRAM type FPGA does not need to perform fault injection on all positions of the FPGA. By only performing fault injection on the logic resources in use, the fault injection efficiency of the SRAM type FPGA can be improved, and the tester can improve the fault injection efficiency according to the fault injection. Can quickly evaluate whether the fault has an impact on the FPGA function.

Description of drawings

Fig. 1 is the flowchart of the fault injection method of the SRAM type FPGA of an embodiment;

FIG. 2 is a configuration bit of a configurable storage unit corresponding to a fault injection position in an embodiment;

Fig. 3 is the fault injection configuration file obtained by inverting the configuration bits shown in Fig. 2;

Fig. 4 is the flowchart of the fault injection method of the SRAM type FPGA of another kind of embodiment;

Fig. 5 is the functional module schematic diagram of the fault injection device of the SRAM type FPGA of an embodiment;

FIG. 6 is a schematic diagram of functional modules of a fault injection device for an SRAM FPGA according to another embodiment.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In one embodiment, as shown in Figure 1, a kind of fault injection method of SRAM type FPGA is provided, and the present embodiment is explained with this method being applied to computer as example, and there is a kind of application program running on this computer, by this program To realize the fault injection method of SRAM type FPGA. The method includes the following steps:

S102: Obtain an initial configuration file of the FPGA to be tested.

FPGA, that is, Field Programmable Gate Array, the user can input the user's design circuit requirements on the input device connected to the FPGA according to the actual situation on site, FPGA automatically designs the circuit according to the user's requirements, and generates the initial configuration file corresponding to the modified circuit .

S104: Obtain the in-use logical resource in the initial configuration file, and determine the configuration file location of the configurable storage unit corresponding to the in-use logical resource.

The resources contained in the FPGA are very rich, including basic logic units, DSP resources and block RAM. The logic resources in use refer to the logic resources in the FPGA used in the circuit designed according to user requirements. The configurable storage unit includes at least one of BRAM (Block Random Access Memory), LUT (Look-Up-Table, lookup table) and flip-flops. In a specific implementation, the user analyzes the content format of the initial configuration file by referring to the user manual, analyzes the logical resource in use in the initial configuration file, and the configuration file location of the logical resource in use corresponding to the configurable storage unit and enters the to the computer running the application program, so that the computer obtains the in-use logical resource in the initial configuration file, and determines the configuration file location of the configurable storage unit corresponding to the in-use logical resource.

S106: Determine the fault injection location, where the fault injection location corresponds to the configuration file location of the configurable storage unit.

In this embodiment, the configuration file location of the configurable storage unit is used as the fault injection location. In a specific embodiment, one type of configurable storage unit may be used as a fault injection object for simulating a unit flip fault. Or multiple types of configurable memory cells can be used as fault injection objects to simulate multi-bit flip faults.

S108: Flipping the configuration bit of the fault injection position to obtain the fault injection configuration file.

Specifically, according to the configurable storage unit corresponding to the fault injection position, the configuration bit of the configurable storage unit is searched for and obtained, and the configuration bit corresponding to the fault injection position is obtained. In an implementation manner, configuration bits of a configurable storage unit corresponding to a fault injection location are shown in FIG. 2 . The fault configuration file obtained by inverting the configuration bits shown in FIG. 2 is shown in FIG. 3 .

S110: Download the fault injection configuration file into the FPGA to be tested.

Specifically, the fault configuration file is downloaded to the SARM FPGA through JTAG (Joint Test Action Group; joint test working group).

In the fault injection method of the SRAM FPGA in this embodiment, logic resources in use are obtained by analyzing the initial configuration file of the FPGA, and fault injection is only performed on the logic resources in use. A single event upset can only affect the normal operation of the FPGA if it occurs on a logic resource in use. The fault injection method of the SRAM type FPGA does not need to perform fault injection on all positions of the FPGA. By only performing fault injection on the logic resources in use, the fault injection efficiency of the SRAM type FPGA can be improved, and the tester can improve the fault injection efficiency according to the fault injection. Can quickly evaluate whether the fault has an impact on the FPGA function.

In one embodiment, step S108 includes: flipping configuration bits of one type of configurable storage unit in the fault injection location to obtain a fault injection configuration file.

The configurable storage unit includes various types, for example, BRAM (Block Random Access Memory), LUT (Look-Up-Table, lookup table), and flip-flops. By flipping the configuration bits of one type of configurable memory cell, it is possible to simulate the cell flip failure of a SARM-type FPGA.

In one embodiment, step S108 includes: respectively flipping configuration bits of multiple types of configurable storage units in the fault injection location to obtain a fault injection configuration file.

By flipping the configuration bits of various types of configurable memory cells, it is possible to simulate the multi-bit flip fault of the SARM-type FPGA.

In one of the embodiments, as shown in FIG. 4, after step S110, further includes:

S112: Run the FPGA to verify whether the FPGA is invalid and obtain a verification result.

Verify that the configured injected faults cause the FPGA to fail by running the FPGA injected with the fault injection configuration file. Specifically, the verification results include failure and non-failure and specific failure modes. The failure modes obtained by different fault injection locations and the types of configurable storage units corresponding to different fault injection locations may be the same.

S114: Determine whether all the configuration bits corresponding to the fault injection position are flipped. If yes, execute step S116; if no, return to step S108.

In this embodiment, there are multiple determined fault injection locations. The configuration bits of the configurable storage units corresponding to one or a group of fault injection positions are flipped each time. After running the FPGA under test injected with the fault configuration file each time, it is judged whether all the configuration bits corresponding to the fault injection position are flipped. When the judgment is no, return to step S108 to flip the configuration bits of the fault injection positions one by one and obtain the corresponding fault injection configuration file.

S116: Determine the failure mode according to the verification result, the fault injection location, and the type of the configurable storage unit corresponding to the fault injection location.

Specifically, the methods for determining the failure mode of the single-bit flip injection and the multi-bit flip injection are different. Taking unit flipping injection as an example, assuming that the capacity of the internal logic resource used by the user is l, there are m configurable storage unit types, resulting in n types of failure modes, according to the location of the unit flipping injection and the location of the configurable storage unit corresponding to the fault injection location The types and failure modes induced by fault injection are summarized, and the results are shown in Table 1.

Table 1 Injection results of unit flipping fault location

Unit Flip Injection Position Types of Configurable Storage Units Is there any influence failure mode unit flip 1 Type 1 whether failure mode 1 Unit Flip 2 Type 2 whether failure mode 2 … … … … unit flip l type m whether failure mode n

According to Table 1, the number of internal logic resources corresponding to various failure modes (Failure Mode i, FMi, 1≤i≤n), N _FMi , can be calculated. Further calculation obtains the proportional factor of FMi in user logic resources, that is, the failure factor α _FMi :

α _FMi =N _FMi /N _total

Wherein, N _total is the total capacity of internal logical resources.

Taking multi-bit flipping as an example, determine the multi-bit flipping fault injection combination according to user requirements, assuming that the number is x, and the corresponding combination of configurable storage unit types is y, resulting in z failure modes. According to the multi-bit flip injection position, the type of configurable storage unit where the flip position is located (BRAM, LUT, flip-flop, etc. and their combination), the failure mode induced by fault injection is summarized, as shown in Table 2.

Table 2 Injection results of multi-bit flipping fault location

Multiple Bit Flip Injection Locations Types of Configurable Storage Units Is there any influence failure mode Multiple Bit Flip Combination 1 Type combination 1 whether failure mode 1 Multiple Bit Flip Combination 2 Type combination 2 whether failure mode 2 … … … … Multiple Bit Flip Combination x type combination y whether failure mode z

The above-mentioned fault injection method for SRAM-type FPGA can fully evaluate the anti-single event upset performance of SRAM-type FPGA, fully reveal the failure mode, and find the weak link of anti-single event upset. The location of failure obtained by this method can also be used for targeted reinforcement of the device.

In another implementation, step S104 includes: determining the user logical resources in the initial configuration file; distinguishing between unused logical resources and in-use logical resources in the user logical resources; determining the configuration of the configurable storage unit corresponding to the in-use logical resources file location.

This method accurately locates the logical resources used by the user by distinguishing the logical resources used by the user from the unused internal logical resources, and distinguishes the unused logical resources and the logical resources in use among the user logical resources, so as to accurately locate the logical resources in use The configurable storage unit and the location of the configurable storage unit, and then perform fault injection in the configurable storage unit in a targeted manner, which can improve the fault injection efficiency of the SRAM FPGA.

The present invention also provides a kind of fault injection device of SRAM type FPGA, comprises as shown in Figure 5:

The initial configuration acquiring module 102 is configured to acquire an initial configuration file of the FPGA to be tested.

The analysis module 104 is configured to obtain the in-use logical resources in the initial configuration file, and determine the configuration file location of the configurable storage unit corresponding to the in-use logical resources.

The fault location determination module 106 is configured to determine a fault injection location, and the fault injection location corresponds to the configuration file location of the configurable storage unit.

The flipping module 108 is used for flipping the configuration bits of the fault injection position to obtain the fault injection configuration file.

The fault injection module 110 is configured to download the fault injection configuration file into the FPGA to be tested.

The fault injection device for SRAM FPGA in this embodiment obtains logic resources in use by analyzing the initial configuration file of the FPGA, and only performs fault injection on the logic resources in use. A single event upset can only affect the normal operation of the FPGA if it occurs on a logic resource in use. The fault injection device of the SRAM type FPGA does not need to perform fault injection on all positions of the FPGA. By performing fault injection only on the logic resources in use, the fault injection efficiency of the SRAM type FPGA can be improved, and the tester can improve the fault injection efficiency according to the fault injection feedback. Can quickly evaluate whether the fault has an impact on the FPGA function.

In another embodiment, the flipping module 108 is configured to flip configuration bits of a type of configurable storage unit in the fault injection location to obtain a fault injection configuration file.

In another embodiment, the flipping module is configured to respectively flip configuration bits of multiple types of configurable storage units in the fault injection location to obtain a fault injection configuration file.

In another embodiment, as shown in FIG. 6, a verification module 112, a judgment module 114 and a failure analysis module 116 are also included,

The verification module 112 is configured to run the FPGA to verify whether the FPGA is invalid and obtain a verification result.

A judging module 114, configured to judge whether all the configuration bits corresponding to the fault injection position are reversed.

The failure analysis module 116 is configured to determine the failure mode according to the verification result, the fault injection location, and the type of the configurable storage unit corresponding to the fault injection location when all the configuration bits corresponding to the fault injection location are flipped.

The flip module 108 is further configured to flip configuration bits at the next fault injection location to obtain a fault configuration file when not all configuration bits corresponding to the fault injection location have been flipped.

In another embodiment, the analysis module includes: a user acquisition resource acquisition module 1041 , a differentiation module 1042 and a storage unit acquisition module 1043 .

User acquisition resource acquisition module 1041, configured to determine user logic resources in the initial configuration file;

A distinguishing module 1042, configured to distinguish unused logical resources and in-use logical resources among the user logical resources.

The storage unit acquisition module 1043 is configured to determine the configuration file location of the configurable storage unit corresponding to the logic resource in use.

The device accurately locates the logical resources used by the user by distinguishing the logical resources used by the user from the unused internal logical resources, and distinguishes the unused logical resources and the logical resources in use among the user logical resources, thereby accurately locating the logical resources in use The configurable storage unit and the location of the configurable storage unit, and then targeted fault injection in the configurable storage unit, can improve the fault injection efficiency of the SRAM FPGA.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. a fault filling method for SRAM type FPGA, comprises the following steps:

Obtain the initial configuration file of FPGA to be measured；

Obtain logical resource in the use in described initial configuration file, and determine that in described use, logical resource correspondence can configure The configuration file position of memory element；

Determining direct fault location position, described direct fault location position is corresponding with the configuration file position of described configurable memory element；

The configuration bit position overturning described direct fault location position obtains direct fault location configuration file；

Described direct fault location configuration file is downloaded in described FPGA to be measured.

The fault filling method of SRAM type FPGA the most according to claim 1, it is characterised in that

The configuration bit position of described upset described direct fault location position obtains the step of direct fault location configuration file and includes:

Overturn the configuration bit position of a type of configurable memory element in described direct fault location position to obtain direct fault location and join Put file.

The fault filling method of SRAM type FPGA the most according to claim 1, it is characterised in that the described fault of described upset The configuration bit position of injection phase obtains the step of direct fault location configuration file and includes:

Overturn the configuration bit position of polytype configurable memory element in described direct fault location position respectively and obtain fault note Enter configuration file.

The fault filling method of SRAM type FPGA the most according to claim 1, it is characterised in that by described direct fault location After configuration file downloads to the step in described FPGA to be measured, also include:

Run described FPGA to verify whether described FPGA lost efficacy and be verified result；

When the configuration bit position that described direct fault location position is corresponding is the most all reversed, returns and overturn described direct fault location position Configuration bit position obtain the step of direct fault location configuration file；

When the configuration bit position that described direct fault location position is corresponding is all reversed, according to described the result, described fault The type of the configurable memory element that injection phase is corresponding with described direct fault location position determines failure mode.

The fault filling method of SRAM type FPGA the most according to claim 1, it is characterised in that described acquisition is described initially Logical resource in use in configuration file, and determine that in described use, logical resource correspondence can configure the configuration literary composition of memory element The step of part position includes:

Determine the user logic resource in described initial configuration file；

Distinguish in described user logic resource do not use logical resource and use in logical resource；

Determine that in described use, logical resource correspondence can configure the configuration file position of memory element.

6. the fault injection device of SRAM type FPGA, it is characterised in that including:

Initial configuration acquisition module, for obtaining the initial configuration file of FPGA to be measured；

Analyze module, for obtaining logical resource in the use in described initial configuration file, and determine logic in described use Resource correspondence can configure the configuration file position of memory element；

Abort situation determines module, is used for determining direct fault location position, and described direct fault location position is single with described configurable storage The configuration file position of unit is corresponding；

Flip module, obtains direct fault location configuration file for overturning the configuration bit position of described direct fault location position；

Direct fault location module, for downloading to described direct fault location configuration file in described FPGA to be measured.

The fault injection device of SRAM type FPGA the most according to claim 6, it is characterised in that

Described flip module, for overturning the configuration bit of a type of configurable memory element in described direct fault location position Position obtains direct fault location configuration file.

The fault injection device of SRAM type FPGA the most according to claim 6, it is characterised in that described flip module, uses Direct fault location is obtained in overturning the configuration bit position of polytype configurable memory element in described direct fault location position respectively Configuration file.

The fault injection device of SRAM type FPGA the most according to claim 6, also includes:

Authentication module, is used for running described FPGA to verify whether described FPGA lost efficacy and be verified result；

Failure analysis module, for when the configuration bit position that described direct fault location position is corresponding is all reversed, according to described The type of the configurable memory element that the result, described direct fault location position are corresponding with described direct fault location position determines inefficacy Pattern；

Described flip module, is additionally operable to when the configuration bit position that described direct fault location position is corresponding is the most all reversed, upset The configuration bit position of next described direct fault location position obtains direct fault location configuration file.

The fault injection device of SRAM type FPGA the most according to claim 6, it is characterised in that described analysis module, bag Include:

User obtains source obtaining module, for determining the user logic resource in described initial configuration file；

Discriminating module, for distinguish in described user logic resource do not use logical resource and use in logical resource；

Memory element acquisition module, for determining that in described use, logical resource correspondence can configure the configuration file position of memory element Put.